KR100237486B1 - Apparatus for rearranging data output from a frame memory - Google Patents

Abstract

The present invention relates to an output data rearrangement apparatus of a frame memory.

The apparatus of the present invention, in the frame memory 100 of the field structure that stores the pixel data for reference in motion compensation in macroblock units, the pixel data for the color difference signal of the predicted macroblock is read from the frame memory. In order to reorder after shipment, the first FIFO 50 for storing two pixel data, the second to fifth FIFOs 51 to 54 for storing four pixel data, and the reference field ref_field are used as control signals. A macro predicted by shifting the multiplexer 60 to select and output one of the second to fifth FIFOs 51 to 54 by a predetermined number of times according to the pixel address of the reference point of the predicted macroblock. And a data sorting unit 70 for extracting effective pixel data corresponding to the block, in accordance with the pixel address of the reference point of the macroblock predicted in the color difference signal. By for shifting left by 5, and then up to a reading unit in the sub-box over a sub-block time, it is possible to rearrange the pixel data corresponding to the predicted macroblock.

Description

Apparatus for rearranging data output from a frame memory

The present invention relates to a motion compensation device, and more particularly, to an apparatus for rearranging output data of a frame memory.

The motion compensation technique used in the Moving Picture Experts Group (MPEG) -2 standard is to reduce temporal redundancy by estimating and compensating for motion between two adjacent temporal pictures in macroblock units. That is, in the motion estimation and compensation process, a neighboring image is compared with the current image to detect a motion vector, which is information about an object's motion, and the current image is predicted using the motion vector.

In an MPEG-2 video encoder using such a motion compensation technique, the P picture performs forward motion compensation on the basis of the I picture or P picture of the previous picture with respect to the current picture, and the B picture performs the current picture. The best one is selected from among motion compensation blocks obtained by performing forward motion compensation, reverse motion compensation, and interpolated motion compensation based on the I picture or P picture of the previous picture and the I picture or P picture of the next picture.

The frame memory is used to store the I picture or P picture of the previous picture and the I picture or P picture of the next picture as the reference picture for motion compensation. In addition, the frame memory is used to temporarily store a decoded picture and fetch it according to the display order since the decoding order and the display order are different in the MPEG-2 video decoder.

However, the frame memory as described above has a capacity to store at least three frames of image data according to the I picture and the P picture or the distance M between the P picture and the P picture, and therefore, the price is expensive, and thus, the entire picture. In addition to raising the price of the decoder, there is a problem that the delay time from the completion of decoding to the display increases.

Accordingly, the present invention has been made to solve the above problems, and includes a region for storing reference image data, a region for storing decoded image data for display, and an encoded bitstream input to an image decoder. In a frame memory in which an area to be stored is implemented on one memory module, in the case of a color difference signal, pixel data corresponding to a macroblock predicted by a start address and a motion vector of a current macroblock is sub-sized over up to five subblocks. It is an object of the present invention to provide an apparatus for rearranging pixel data corresponding to a predicted macroblock after reading in a box unit.

An apparatus of the present invention for providing the above object is a frame memory for storing pixel data for reference in motion compensation in macroblock units, the pixel data of the first and third sub-blocks from the frame memory A first FIFO that reads and stores the blocks in sub-box units over a block, and 2 which reads the second and fourth sub blocks in sub-box units over one sub block from two pixel data and frame memory output from the first FIFO; A second to fifth FIFO for storing the pixel data, a multiplexer for selecting one of the outputs of the second to fifth FIFOs using a reference field (ref_field) as a control signal, and two sub-blocks from the multiplexer Pixel data output in sub-box order and pixel data output in sub-box order across one sub-block from the frame memory And a data sorting unit which extracts valid pixel data corresponding to the predicted macroblock by not shifting or shifting the pixel once according to the pixel address of the reference point of the predicted macroblock.

1 is a diagram showing the structure of a frame memory adopted in the present invention;

FIG. 2 is a diagram illustrating an example of a method for setting a RAS box for one frame in the frame memory shown in FIG. 1;

3 is a view showing an example of a macroblock structure in the RAS box shown in FIG.

4 is a diagram illustrating an example of a position of a predicted macroblock in a color difference signal of an upper field;

5 is a block diagram showing the configuration of an output data rearrangement apparatus of a frame memory according to the present invention.

＊ Explanation of symbols for main parts of drawing

50 ~ 54: FIFO 60: Multiplexer

70: data sorting unit

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates a structure of a frame memory adopted in the present invention, in which the frame memory 100 includes a restored image data write operation, a data read operation for motion compensation, and a data read operation for display to a memory controller (not shown). Is controlled by The frame memory 100 has two memory banks, bank 1 and bank 2, bank 1 has first and second frame storage areas 100-1 and 100-2, and bank 2 stores third and fourth frames. There are regions 100-3 and 100-4. Here, the first to fourth frame storage areas 100-1, 100-2, 100-3, and 100-4 have a capacity for storing pixel data of one frame, respectively, and the first to fourth frame storage areas 100-1, 100-. 2,100-3 and 100-4 each have 1,024 row addresses, and have a column address of 256 words (where 1 word is 8 bits). One address stores eight Y pixels, two Cr pixels, two Cb pixels, and a total of 12 pixel data. Here, 1,024 row addresses mean the number of RAS boxes. The 256-word column address is derived by eight macroblocks per one RAS box * 32 boxes per macroblock (= 256 boxes).

The actual physical row address of the frame memory 100 is 000 _H to 3FF _H , 400 _H to 7FF _H for the first to fourth frame storage areas 100-1 to 100-4, respectively. , 800 _H to BFF _H and C00 _H to FFF _H. However, the first to fourth frame storage regions 100-1 to 100-4 exist independently, and the second and fourth frames corresponding to the macroblocks located at predetermined row addresses of the first frame storage region 100-1 are respectively provided. The macroblocks of the third frame storage areas 100-2 and 100-3 have the same row address. As such, the row address in the first to third frame storage areas 100-1 to 100-3 is referred to as a virtual row address. Then, based on the scheduling order of the frame memory 100 as shown in FIG. 2 during motion compensation, an address used to convert a virtual row address in a corresponding storage area in which a reference image is located into a physical row address is framed. It is called the frame offset address and is called RA [11:10]. That is, if RA [11:10] is '00', the first frame storage area 100-1, if '01', the second frame storage area 100-2, and if the '10', the third frame storage area 100 -3) and '11' indicate the fourth frame storage areas 100-4, respectively.

Here, the first and second frame storage areas 100-1 and 100-2 are used to store reconstructed I-picture or motion-compensated P-picture image data for use as a reference image for motion compensation and simultaneously for display. The three-frame storage area 100-3 is used to store the motion compensated B-picture image data, and the fourth frame storage area 100-4 stores the encoded bitstream input to the image decoder in units of predetermined bits. Used to save.

FIG. 2 illustrates an example of a RAS box setting method for one frame in the frame memory 100 shown in FIG. 1. For example, when one frame includes 1,920 pixels * 1,088 pixels, 15 RAS boxes * 68 It is divided into RAS boxes, a total of 1,020 Row Address Strobe (RAS) boxes. That is, the number of the RAS box is the row address (RA) of the frame memory 100. Here, one RAS box is composed of eight macroblocks * 1 macroblocks and a total of eight macroblocks MB0 to MB7. Each macroblock is divided into four blocks b0 to b3 when the luminance Y block is taken as an example.

FIG. 3 shows an example of a macroblock structure in the RAS box shown in FIG. 2, with four luminance (Y) blocks b0 to b3, one color difference (Cr) block, and one color difference (Cb) block. Four luminance (Y) blocks are composed of eight boxes (b0-0 to b0-7, b1-0 to b1-7, b2-0 to b2-7, and b3-0 to b3-7), respectively. Each of the two color difference (Cr, Cb) blocks has eight sub boxes (sb0-0 to sb0-7, sb1-0 to sb1-7, sb2-0 to sb2-7, and sb3-0 to sb3-7). It consists of. 8 pixel data in 8 * 1 format is included in each box constituting the Y block, 2 pixel data in 2 * 1 format is formed in each sub box constituting the Cr block, and 2 * is in each sub box constituting the Cb block. There are two pixel data in one format.

Since the frame memory applied to the present invention is mapped to a field structure, FIG. 4 shows an example of pixel data of a color difference signal to be read within a predicted macroblock range in an upper field, and each sub box is represented as an address. Are distinguished. Herein, the color difference signal of the upper field is divided into four two-pixel * four-pixel structures, which are called subblocks.

FIG. 5 is a block diagram showing a configuration of an output data rearrangement apparatus of a frame memory according to the present invention, and includes first to fifth FIFOs 50 to 54, a multiplexer 60, and a data sorting unit 70. .

Then, the operation and effects of the present invention will be described in detail with reference to FIGS. 1 to 5. Here, the luminance signal is taken as an example when the picture to be referred to is a field picture and the motion type is field estimation and compensation. Also, a case in which pixel data of a color difference signal to be read in the predicted macroblock range is located as shown in FIG. 4 and read out in units of 4 pixels * 4 pixels, that is, 2 sub blocks. Here, for convenience of description, the five subblocks in which the predicted macroblocks of the color difference signal are located are called first to fifth subblocks.

In FIG. 4, pixel data corresponding to the color difference signal is read in sub box units, that is, in units of 2 pixels. As such, when pixel data is read in units of sub-boxes, four sub-boxes should be read over a total of five sub-blocks except that the reference point RP is placed at the start of each macro block. Pixel data are read. The present invention is to extract the pixel data of the color difference signal corresponding to the predicted macroblock MBp from the pixel data read out in units of sub boxes over up to five sub blocks in the corresponding storage area of the frame memory.

In FIG. 5, the first FIFO 50 sequentially reads out and stores pixel data in a sub box unit from a frame memory (not shown) over one sub block, and stores each FIFO except for the first FIFO 50. Reference numerals 51 to 54 are for storing pixel data of a sub box unit over two sub blocks and outputting pixel data of the corresponding block. Here, four FIFOs 51 to 54 except for the first FIFO 50 are used for the fields to be referred to when the motion shape is B estimation and compensation or 16 * 8 estimation and compensation in the B picture. That is, the second FIFO 51 stores the upper field of the I picture or the P picture of the previous picture with respect to the current picture of the B picture, and the third FIFO 52 stores the lower field of the I picture or the P picture of the previous picture. The fourth FIFO 53 stores the upper field of the I picture or the P picture of the next picture, and the fifth FIFO 54 stores the lower field of the I picture or the P picture of the next picture.

The multiplexer 60 selectively outputs pixel data across two sub-blocks stored in the second to fifth FIFOs 52 to 54 as a reference field ref_field as a control signal. Therefore, when the field to be referred to for the B picture is the upper field of the I picture or the P picture of the previous picture, the multiplexer 60 selects the output of the second FIFO 51.

The data sorting unit 70 outputs pixel data (ie, four pixel data) over two sub-blocks supplied from the multiplexer 60 with respect to the color difference signal of the predicted macroblock MBp and 1 directly output from the frame memory. The pixel data for the two sub blocks of the color difference signal of the macroblock MBp predicted from the pixel data (that is, the two pixel data) over the two sub blocks is taken into consideration and extracted up to half pixels. To this end, the pixel address P.A for the reference point R.P of the predicted macroblock MBp is used.

Data sorting unit 70 includes a pixel address (PA) in accordance to perform left shifting operation times up to one, For example, if the pixel address of the reference point (RP) 00 ₂ times 1 when the shifting operation is not 01, ₂ The shifting operation is performed. That is, the data sorting unit 70 extracts five effective pixel data in consideration of half a pixel by shifting six pixel data according to the pixel address PA or by shifting one pixel to the left.

If the pixel data to be read in the color difference signal of the predicted macroblock is located as shown in FIG. 4, the first through third subblocks from 0 to 14 are first read to read the first two subblocks. Let's look at the case of reading pixel data.

The first FIFO 50 receives the pixel data of the first sub block (addresses 0, 2, 4, 6) from the frame memory in units of sub boxes, and the second FIFO 51 stores the first FIFO 50. Pixel data of addresses 0 to 6 and pixel data of second sub blocks (addresses 1, 3, 5, and 7) directly output from the frame memory are received and stored in the unit of the sub box. The pixel data of the third sub-block 8 (10, 12, 14), which is the next sub-block, is directly output from the frame memory and transferred to the data sorting unit 70.

When the multiplexer 60 selects the output of the second FIFO 51 according to the reference field ref_field, the data sorting unit 70 outputs four pixel data and a frame at address 0 and address 1 output from the multiplexer 60. By receiving two pixel data of address 8 outputted from the memory and shifting by one pixel to the left or not shifting according to the pixel address PA, five effective pixel data are extracted in consideration of half a pixel.

Next, the next two sub-blocks that are located across the third to fifth sub-blocks are read. In this case, since the pixel data of the third sub-block is also used, the pixel of the third sub-block when the first two sub-blocks are read. Store and use the data.

In order to read the next two sub-blocks located across the third to fifth sub-blocks, the first FIFO 50 frames the pixel data of the third sub-blocks (addresses 8, 10, 12, and 14) in sub-box units. The second FIFO 51 receives the data from the memory and stores the pixel data from 8 to 14 output by the first FIFO 50 and the fourth sub block 9,11 that is directly output in the sub-box unit from the frame memory. 13, 15) to receive and store the pixel data. The pixel data of the fifth sub block 16, 18, 20, and 22, which is the next sub block, is directly output from the frame memory and transferred to the data sorting unit 70.

When the multiplexer 60 selects the output of the second FIFO 51 according to the reference field ref_field, the data sorting unit 70 outputs four pixel data and a frame of eight addresses and nine addresses output from the multiplexer 60. By receiving two pixel data of address 16 outputted from the memory and shifting by one pixel to the left without shifting according to the pixel address PA, five effective pixel data are extracted in consideration of half a pixel.

On the other hand, the above detailed description is intended to describe particular embodiments presented herein and is not intended to limit the present invention. Those skilled in the art may make various changes and modifications according to the structure of the RAS box, the structure of the macroblock block, the picture type, and the motion compensation form within the spirit of the present invention with reference to the above description and drawings.

As described above, when the apparatus reads the macroblock predicted by the start address and the motion vector of the current macroblock to be motion compensated from the corresponding storage region of the frame memory, the macro predicted the color difference signal. According to the pixel address of the block, the readout is performed in units of subboxes up to five sub-blocks, and then shifted to the pixel data corresponding to the predicted macroblock by not shifting or shifting to the left once.

Claims (3)

In the frame memory (100) for storing pixel data for reference in motion block compensation in motion compensation, A first FIFO 50 that reads and stores pixel data of the first and third sub-blocks from the frame memory in sub-box units over one sub-block; Second to fifth data for storing two pixel data output from the first FIFO 50 and two pixel data obtained by reading the second and fourth subblocks from the frame memory in sub box units over one sub block; FIFOs 51-54; A multiplexer 60 for selecting one of the outputs of the second to fifth FIFOs 51 to 54 using a reference field ref_field as a control signal; And Pixel data output in the sub box order from the multiplexer 60 over two sub blocks and pixel data output in the sub box order from one frame memory to the pixel address of the reference point of the predicted macroblock Therefore, the data sorting unit 70 of the frame memory, characterized in that it does not shift or shifts to the left once, extracting the effective pixel data corresponding to the predicted macroblock. The method of claim 1, wherein the one frame picture stored in the frame memory 100 comprises a plurality of RAS boxes, the RAS box consists of eight macroblocks, the macroblock is one block for the color difference block Wherein the block has a format of 4 sub blocks * 2 sub blocks, the sub block has a format of 1 sub box * 4 sub boxes, and the sub box has a format of 2 pixels * 1 pixels. Output data rearrangement device in memory. The second and fifth FIFOs 51 to 54 are higher than an I picture or a P picture to be referred to, respectively, when the motion pattern in the B picture is field estimation and compensation or 16 * 8 estimation and compensation. Or storing subfields.

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