KR100248866B1 - High voltage generating circuit of a non-volatile semiconductor memory - Google Patents

Abstract

The present invention relates to a high voltage generation circuit of a nonvolatile semiconductor memory device for maintaining a constant high voltage even when an external power supply voltage as a single power source changes. The high voltage generation circuit includes a charge pump unit generating a high voltage higher than a power supply voltage in response to the first and second clock signals, and first and second detectors connected to the charge pump unit. The charge pumping unit includes a load transistor connected between a power supply terminal receiving the power supply voltage and a first node; Pumping NMOS transistors connected in series between the first node and an output terminal for outputting the high voltage, the drain terminals of each gate terminal being electrically connected to each other; Each having capacitors having one end connected to a connection node of a gate terminal and a drain terminal of a corresponding NMOS transistor, and the other terminal alternately connected to first and second input terminals receiving the first and second clock signals; . The first detector is connected to an i-th connection node of the connection terminals of the gate terminal and the drain terminal of the NMOS transistors, and detects whether the power supply voltage exists in a first section lower than a predetermined level, and detects the detected result. The i-th connection node is connected to the power terminal accordingly. The second detector is connected to an (i + j) th node of the connection nodes of the gate terminal and the drain terminal of the NMOS transistors, and detects whether the power supply voltage is present in a second section higher than a preset level. Then, according to the detection result, the (i + j) th connection node is connected to the power terminal.

Description

A high voltage generation circuit of a nonvolatile semiconductor memory device. (a circuit of generating a high voltage of non volatile semiconductor memory device)

The present invention relates to a high voltage generating circuit of a nonvolatile semiconductor memory device, and more particularly, to a high voltage generating circuit of a nonvolatile semiconductor memory device for maintaining a constant high voltage stepped up even when an external power supply voltage as a single power source changes. .

The memory cells of the EEPROM are largely divided into a Floating Gate Tunnel Oxide (FLOTOX) type and a Metal Nitride Oxide Semiconductor (NMOS) type. The FLOTOX type EEPROM cell has a floating gate that is electrically insulated from the surroundings, and can store "1" or "0" level data by injecting or emitting electrons into the floating gate. Usually, although not shown in the figure, the source and drain regions of N-type impurities are formed in the EEPROM cell with a channel between the P-type semiconductor substrate and the semiconductor substrate. A gate oxide film, a floating gate, an ONO film, and a control gate are sequentially formed over a portion of the source and drain regions over the channel.

In a conventional flash memory operation, the flash memory cell is programmed by a hot electron injection method in which electrons are injected into the floating gate in a channel region adjacent to the drain region. In general, the injection method grounds the source region and the P-type semiconductor substrate region, and applies a high high voltage (eg, +12 volts) to the control gate. The drain region is then applied by applying an appropriate amount of voltage (e.g., 6-7 volts) to generate hot electron injection. A negative charge is sufficiently accumulated in the floating gate by the program method, and the negative potential of the floating gate serves to increase the threshold voltage of the memory cell during a series of read operations.

Primarily, a read operation applies 1-2 volts to the drain region of a memory cell and applies a constant voltage or a power supply voltage VCC to the control gate. The source region is formed by applying zero volts. The read operation as described above is performed. The memory cell having a high threshold voltage by the program operation prevents current from being injected from the drain region to the source region, and the memory cell is said to be "off". In addition, according to the operation of the flash memory, F-N tunneling (Fowler-Nordheim tunneling) from the source region to the control gate occurs, the flash memory cell is erased. The general tunneling method is achieved by applying a high high voltage (eg, +12 volts) to the source region and applying 0 volts to the control gate and the semiconductor substrate. At this time, the drain region is in a high impedance state (eg, a floating state) in order to maximize the effect of erasing.

As described above, a strong electric field is formed between the control gate and the source region, thereby causing the FN tunneling to release negative charge in the floating gate to the source region. . Typically, the F-N tunneling occurs when an electric field of 6-7 MV / cm is applied between the gate insulating layers. This is because F-N tunneling is possible between the floating gate and the source region because a thin gate insulating film of 100 kΩ or less is formed. Negative charge is discharged from the floating gate to the source region by the erase method, and serves to lower the threshold voltage of the memory cell during a series of read operations. In a typical flash memory cell array configuration, each source region is commonly connected for high integration of memory. As a result, a plurality of cells are simultaneously erased by the erasing method, and the erasing unit is determined according to a region to which each source region is connected.

Devices incorporating EPROM or EEPROM typically use a single 5 volt external supply voltage. Therefore, in order to perform the above-described operation, a high voltage generation circuit capable of multiplying a power supply voltage of 5 volts to a high voltage of approximately 20 volts should be incorporated. The high voltage generator circuit is generally made using a capacitor using a MOSFET and a pump for pumping (or boosting) a few MHz. However, when the external power supply voltage changes, the boosted voltage is slightly different since the high voltage level boosted (pumped) is affected by the power supply voltage. As a result, electrons are injected into the floating gate of the EEPROM cell or the degree of injection of the injected electrons is changed, thereby causing a problem in that the characteristics of the EEPROM cell are changed due to a change in the power supply voltage.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and to provide a high voltage generation circuit of a nonvolatile semiconductor memory device for maintaining a constant high voltage even when an external power supply voltage as a single power source changes.

1 is a block diagram showing a configuration of a high voltage generation circuit of a nonvolatile semiconductor memory device according to the present invention;

* Explanation of symbols on the main parts of the drawings

100: charge pumping unit 200: first detection unit

220: first detection means 240: first switching means

300: second detection unit 320: second detection means

340: second switching means

According to one aspect of the present invention for achieving the above object, a charge pump for generating a high voltage of a higher level than the power supply voltage in response to the first and second clock signals of the high voltage generation circuit of the nonvolatile semiconductor memory device Contains wealth. The charge pumping unit is connected between a power supply terminal receiving the power supply voltage and a first node; A series connection between the first node and an output terminal for outputting the high voltage, respectively corresponding to pumping NMOS transistors electrically connected to respective gate terminals and drain terminals, each of which corresponds to a gate terminal of the corresponding NMOS transistor And capacitors having one terminal connected to the connection node of the drain terminal and the other terminal alternately connected to the first and second input terminals receiving the first and second clock signals. The high voltage generation circuit of the present invention further includes a first detector and a second detector. The first detector is connected to an i-th (i is a positive integer) connection node of the connection terminals of the gate terminal and the drain terminal of the NMOS transistors, and determines whether the power supply voltage is present in a first section lower than a preset level. The i-th connection node is connected to the power terminal according to the detection result. Here, the voltage pumped by the NMOS transistors and the corresponding capacitors connected between the load transistor and the i-th connection node when the i-th connection node is connected to the power terminal through the first detection unit is the power supply. Discharged to the terminal. The second detector is connected to a (i + j) th (j is a positive integer) connection node of the connection nodes of the gate terminal and the drain terminal of the NMOS transistors, and a second period in which the power supply voltage is higher than a preset level. Is detected, and the (i + j) th connection node is connected to the power supply terminal according to the detection result. Where the (i + j) th connection node is pumped by NMOS transistors and capacitors connected between the load transistor and the (N + M) th connection node when the (i + j) th connection node is connected to the power terminal through the second detector. Voltage is discharged to the power supply terminal.

In this embodiment, the first detecting unit detects whether or not the power supply voltage is lower than a predetermined level and generates detection signals as a detection result; Connected between the power supply terminal and the ith connection node and switched on / off according to the detection signal;

It includes a transistor.

In this embodiment, the second detecting unit comprises: detecting means for detecting whether the power supply voltage is higher than a predetermined level and generating a detection signal as a detection result; And an NMOS transistor connected between the power supply terminal and the (i + j) th connection node and switched on / off according to the detection signal.

By such a circuit, even when the external power supply voltage, which is a single power supply, is maintained, the high voltage boosted is kept constant so that the degree of electron injection and electron emission can be kept constant during program and erase operations in the EEPROM cell to which the high voltage is applied. It became.

Hereinafter, reference will be made in detail with reference to FIG. 1.

The novel high voltage detection circuit of the present invention shown in FIG. 1 detects a low voltage (LOW VCC) detection circuit 200 for detecting a voltage level lower than the power supply voltage and a voltage level lower than the power supply voltage (Vcc). The high voltage VCC detection circuit 300 is implemented to obtain a constant high voltage Vpp regardless of a change in the power supply voltage Vcc. That is, when the power supply voltage Vcc is present in the first section at a level lower than that of the power supply voltage Vcc, the low voltage detection circuit 200 detects it so that predetermined pumping capacitors are further connected in series. Boosts (Vpp) a predetermined level. In addition, when the power supply voltage Vcc is present in the second section at a higher level than the power supply voltage Vcc, the high voltage detection circuit 300 detects this and reduces the pumping capacitors by a predetermined number. This prevents over pumping. Thereby, even if the power supply voltage Vcc changes, the level of the high voltage Vpp output from the high voltage generation circuit can be kept constant.

1 is a block diagram illustrating a configuration of a high voltage generation circuit of a nonvolatile semiconductor memory device according to an exemplary embodiment of the present invention. Referring to FIG. 1, a charge pumping unit 100, a first detection unit (or low voltage detection unit) 200, and a second detection unit (or high voltage detection unit) 300 are provided in a high voltage generation circuit.

The charge pumping unit 100 performs a pumping operation according to the first and second clock signals CLK and CLK when the power supply voltage Vcc is supplied, and each of the load transistors LT operating as a diode, A plurality of pumping transistors Tl-Tn (n is a positive integer) having a gate, a terminal, a source terminal and a drain terminal, and the transistors Tl-Tn and the transistors Tl-Tn Each of the pumping capacitors means Cl-Cn. The channel of the load transistor LT is formed between the power supply terminal 1 and the node 1 N1, and the gate terminal of the transistor LT is connected to the power supply terminal 1. The channels of the transistors Tl-Tn are connected in series between the node 1 N1 and the terminal 4 for outputting the high voltage Vpp, and the gate terminal of each transistor Tl-Tn has its own drain terminal. Is connected to. One terminal of each capacitor Cl-Cn is connected to a drain terminal of a corresponding pumping transistor, and the other terminal is input terminals 2 and 3 which receive the first and second clock signals CLK and CLK. Are alternately connected).

1, the first detector (or low voltage detector) 200 detects whether the power supply voltage Vcc is lower than a preset voltage level and outputs the first signal A as a detection result. . The first detector 200 includes an NMOS transistor 10 that operates as the first detector 220 and the switch 240. The first detecting means 220 detects whether or not the power low voltage Vcc is lower than a preset voltage level, and outputs the first detection signal Dl as a detection result. The second detector (or high voltage detector) 300 detects whether the power supply voltage Vcc is higher than a preset voltage level and outputs a second signal B as a detection result. The second detector 300 includes an NMOS transistor 20 that operates as the second detector 320 and the switch 340. The second detecting means 320 detects whether or not the power supply voltage Vcc is higher than a preset voltage level, and outputs the second detection signal Dl as a detection result.

Hereinafter, the operation of the high voltage generation circuit according to the present invention will be described in detail with reference to FIG. The high voltage generation circuit according to the present invention is for generating a high level of high voltage Vpp by adjusting the number of pumping capacitor means in accordance with the change of the power supply voltage Vcc.

First, when the power supply voltage Vcc is present in a section of a pre-set voltage level, the first signal A output from the first detector 200 is maintained at a logic high level. Specifically, when the power supply voltage Vcc is present in the section of the pre-set voltage level, the first detection unit 220 of the first detection unit 200 detects the first detection signal Dl having a logic high level. ), Which causes the NMOS transistor 10 to turn on. The second detection unit 320 of the second detection unit 300 detects this and outputs a second detection signal D2 having a logic low level, which causes the NMOS transistor 20 to be turned off. do. As a result, node 2 N2 of the charge pumping unit 100 is connected to the power supply terminal 1 through the turned-on NMOS transistor 10, while node 3 N3 of the charge pumping unit 100 is connected. Is not connected to the power supply terminal 1.

Under these conditions, since the node 2 (N2) is connected to the power supply terminal 1 through the NMOS transistor 10 of the first detector 200, the transistors T1 and T2 and the capacitors C1 and C2. The voltage pumped by is discharged to the power supply terminal 1 through the NMOS transistor 10. Therefore, when the first and second clock signals CLK and CLK are applied, the pumping NMOS transistor T3 of the charge pumping unit 100 operates as a load transistor, and the transistors T4-Tn and corresponding ones. Only capacitors C3-Cn are involved in the pumping operation of the charge pumping unit 100.

Next, when the power supply voltage Vcc is present in the first section lower than the previously set voltage level, the first detection unit 220 of the first detection unit 200 detects the first voltage of the logic low level. The detection signal D1 is output, which causes the NMOS transistor 10 to be turned off. Similarly, the second detection unit 320 of the second detection unit 300 detects this and outputs the second detection unit signal D2 having a logic low level, which causes the NMOS transistor 20 to be turned off. As a result, nodes 2 (N2) and node 3 (N3) of the charge pumping unit 100 are not connected to the power supply terminal 1 because the NMOS transistors 10 and 20 are turned off.

Under these conditions, when the first and second clock signals CLK and CLK are applied, the load transistor LT provided to the charge pumping unit 100, the pumping NMOS transistors T1 -Tn, and the corresponding Capacitors (C1-Cn) are involved in the mode pumping operation. Therefore, the voltage level of the high voltage Vpp, which decreases as the power supply voltage Vcc is lowered, will be increased by the voltage level pumped by the transistors T1, T2 and the corresponding capacitors C1, C2.

In summary, the level of the high voltage Vpp output when the power supply voltage Vcc is lower is lower than the level of the high voltage Vpp output when the power supply voltage Vcc is present in a predetermined section. According to the present invention for solving this problem, all the pumping NMOS transistors (T1-Tn) and the corresponding capacitors (C1-Cn) provided in the charge pumping unit 100 is lowered by the pumping operation, The high voltage can be maintained at the required level.

Finally, when the power supply voltage Vcc is present in the second section higher than the previously set voltage level, the first detection unit 220 of the first detection unit 200 detects the first detection signal having a logic high level. Outputs D1, which causes the NMOS transistor 10 to be turned on. The second detection means 320 of the second detection unit 300 detects this and outputs the second detection signal D2 having a logic high level, which causes the NMOS transistor 20 to be turned on. As a result, nodes 2 (N2) and 3 (N3) of the charge pumping unit 100 are connected to the power supply terminal 1 through the turned-on NMOS transistors 10 and 20, respectively.

Under these conditions, when the first and second clock signals CLK and CLK are applied, the pumping NMOS transistor T5 operates as a load transistor, and the pumping NMOS transistors T6-Tn and corresponding capacitors. Only C5-Cn is involved in the pumping operation of the charge pumping unit 100. Therefore, as the power supply voltage Vcc increases, the voltage level of the high voltage Vpp will be lowered by the voltage level pumped by the transistors T1-T4 and the corresponding capacitors C1, C4. The reason that the transistors T1-T4 and the corresponding capacitors C1, C4 do not affect the pumping operation is that the transistors T1-T4 and the corresponding capacitors are turned on through the turned on NMOS transistors 10, 20. This is because the voltage pumped by the fields C1 and C4 is discharged.

In summary, the level of the high voltage Vpp that is output when the power supply voltage Vcc is high becomes higher than the level of the high voltage Vpp that is output when the power supply voltage Vcc is present in a predetermined section. According to the present invention to solve this problem, the pumping NMOS transistors (T1-T4) and the corresponding capacitors (C1-C4) do not affect the pumping operation, thereby over-pumping the high voltage It can be maintained at the required level.

As described above, by adjusting the number of NMOS transistors and corresponding capacitors that affect the pumping operation according to the result of detecting the level of the power supply voltage, it is possible to prevent the change of the high voltage level caused when the power supply voltage is changed. Can be.

Claims (3)

In response to the first and second clock signals CLK and CLK, a high voltage Vpp having a level higher than the power supply voltage Vcc is generated and the power supply terminal 1 and the first receiving the power supply voltage Vcc are provided. A load transistor LT connected between the nodes N1; Pumping NMOS transistors T1-Tn connected in series between the first node N1 and an output terminal 4 for outputting the high voltage Vpp, and each gate terminal and a drain terminal are electrically connected. ), A terminal corresponding to each of the NMOS transistors T1 -Tn, respectively, connected to a connection node of a gate terminal and a drain terminal of a corresponding NMOS transistor, and the first and second clock signals CLK, In a high voltage generation circuit of a nonvolatile semiconductor memory device including a charge pumping unit (100) having capacitors (C1-Cn) having other terminals alternately connected to first and second input terminals receiving CLK): One of the connection nodes of the gate and drain terminals of the NMOS transistors T1 -Tn is connected to an i (i is a positive integer) connection node N2, and the power supply voltage Vcc is lower than a preset level. Present in the first section The detection of whether or not according to the detection result of the first detection unit (200) coupled to the power supply terminal (1) for the i beonjae connection node (N2) and; NMOS transistors connected between the load transistor LT and the i-th connection node N2 when the i-th connection node N2 is connected to the power supply terminal 1 through the first detection unit 200; The voltage pumped by the corresponding capacitors is discharged to the power supply terminal 1; A second (i + j) th (j is a positive integer) connection node N3 among the connection nodes of the gate terminal and the drain terminal of the NMOS transistors, and the second power supply voltage Vcc is higher than a preset level; A second detection unit 300 which detects whether or not present in the section and connects the (i + j) th connection node N3 to the power terminal 1_ according to the detection result, and the (i + j) the connection node N3 is connected between the load transistor LT and the (N + M) th connection node N3 when the second connection node N3 is connected to the power supply terminal 1 through the second detection unit 300. A voltage pumped by NMOS transistors and capacitors is discharged to the power supply terminal (1). 2. The apparatus of claim 1, wherein the first detection unit (200) comprises: detection means (220) for detecting whether the power supply voltage (Vcc) is lower than a predetermined level and generating a detection signal (D1) as a detection result thereof; And a NMOS transistor 10 connected between the power supply terminal 1 and the i-th connection node N2 and switched on / off according to the detection signal D1. High voltage generator circuit. 2. The apparatus of claim 1, wherein the second detector (300) comprises: detection means (320) for detecting whether the power supply voltage (Vcc) is higher than a predetermined level and generating a detection signal (D2) as a detection result thereof; And an NMOS transistor 20 connected between the power supply terminal 1 and the (i + j) th connection node N3 and switched on / off according to the detection signal D2. A high voltage generation circuit of a volatile semiconductor memory device.