KR100243168B1 - Audio/video synchronizing circuit of digital receiver for simultaneously receiving multiful channel and method therefor - Google Patents

Abstract

The present invention discloses an audio / video synchronization circuit and a method of a digital receiver for receiving multiple channels simultaneously. The synchronization circuit of the present invention uses a program clock reference (PCR) value of one channel to control the oscillation frequency oscillating therein to generate a system clock signal. A decoding controller for generating a control signal for controlling the decoding of the compression-encoded video and audio signals of the other channel based on the difference value of?, And controlling the decoding of the other channel using the system clock signal for one channel. Therefore, the circuit is simplified because only one channel of PLL circuit is used.

Description

Audio / Video Synchronization Circuit and Method of Digital Receiver Receiving Multiple Channels Simultaneously

The present invention relates to an audio / video synchronization circuit and a method thereof in a digital receiver, and more particularly, to a circuit and a method for synchronizing an audio / video signal when simultaneously decoding a plurality of broadcast channels encoded by MPEG, which is a high compression coding scheme. will be.

Increasingly, the number of broadcast channels has increased and broadcast receivers that receive multiple broadcast channels simultaneously in one receiver have been released. An example is a broadcast receiver in which functions such as a picture in picture (PIP), a double window, and the like are incorporated.

In addition, broadcasting is also being converted from conventional analog broadcasting to digital broadcasting. Accordingly, a digital receiver that receives a bit string encoded by a high compression coding scheme (MPEG) will be commercialized soon. In such a digital receiver, it is desirable to have a function of receiving two or more channels simultaneously and displaying a plurality of screens such as a PIP or a double window. In this case, audio / video synchronization is necessary in order to display signals of multiple channels on multiple screens.

Accordingly, an object of the present invention is to use an audio and video signal of another channel by using a system clock signal generated based on a program clock reference (PCR) value of one channel when receiving and decoding multiple channels simultaneously. It is to provide an audio / video synchronization circuit for synchronizing the.

Another object of the present invention is to provide an audio / video synchronization method for synchronizing audio and video signals of another channel using a system clock signal generated based on a PCR value of one channel when receiving and decoding multiple channels simultaneously. There is.

In order to achieve the above object, the audio / video synchronization circuit according to the present invention comprises a program clock reference (PCR) value of any one channel in a digital receiver for recovering two or more compressed coded video and audio signals. System clock restorer that generates the system clock signal by controlling the oscillation frequency that is oscillated internally, based on the difference between the PCR value of the other channel and the system clock signal. And a decoding controller for generating a control signal for controlling decoding.

In order to achieve the above object, an audio / video synchronization method according to the present invention is a method of synchronizing two or more received compression-coded video and audio signals with each other in reconstruction. Extracting a bit string and a program clock reference (PCR) value, generating a system clock signal using a PCR value of one channel, and decoding a compressed / encoded video / audio signal of one channel using the system clock signal. And generating a control signal for controlling decoding of the compression-coded video / audio signal of another channel based on the difference value between the PCR value of the other channel and the system clock signal.

1 is a block diagram of a digital receiver to which the present invention is applied.

2 is a block diagram for PCR processing of a transport stream processor when receiving one channel for better understanding of the present invention.

3 is a block diagram according to an embodiment of an audio / video synchronization circuit according to the present invention.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the audio / video synchronization circuit and method of a digital receiver for receiving multiple channels at the same time according to the present invention.

In FIG. 1, which is a block diagram of a digital receiver according to the present invention, several NIMs (Network Interface Modules) may exist in order to receive digital information compressed by MPEG through various transmission methods such as cable, telephone line, satellite, and wireless. have. That is, the image compressed bit string transmitted through various transmission methods is received.

Examples of the NIM corresponding to the satellite signal include an antenna, a low noise block down converter (NBN), a tuner, a quadrature phase shift keying (QPSK) demodulator, and an error correction decoder. Therefore, there is a NIM for each method corresponding to various transmission methods. Here, NIM may be referred to as a channel demodulator.

For example, in order to support the PIP and the double window function, the bit streams of the two channels are simultaneously received and the video decoding process is performed to synthesize the restored images of the two channels and output the synthesized video signal.

That is, a broadcast signal transmitted as a satellite signal is input to the bit stream through the first and second NIMs 110 and 120, which is a compressed coded bit stream. The form is in the form of a transport stream (TS) bit string.

If the audio / video PID of the selected channel according to the channel selection key data is supplied from the microprocessor 170, the TS processor 130 selects the two-channel TS having the PID corresponding to the selected two channels and selects the two-channel TS from the selected two-channel TS. The audio / video bit stream of each channel is extracted and transmitted to the first MPEG A / V decoder 140 and the second MPEG A / V decoder 150.

The first MPEG A / V decoder 140 decodes the audio / video bit stream of the first channel to apply an analog audio signal of the first channel to a voice output device such as a speaker, and The analog image signal is applied to the image synthesizer 160.

The second MPEG A / V decoder 150 decodes the audio / video bit stream of the second channel to apply the analog audio signal of the second channel to the audio output device, and restores the analog video signal of the second channel. Is applied to the image synthesizer 160. The image synthesizer 160 synthesizes the analog video signal of the first channel and the video signal of the second channel according to the control signal for the PIP or the double window mode applied from the microprocessor 170 to display the PIP screen or the double window screen. Indicated by.

Here, the microprocessor 170 receives the status information such as the arrival of the PCR value of each channel from the TS processor 130, and transmits an appropriate control signal for the status information to the TS processor 130, the first and Receive status information related to decoding from the second MPEG A / V decoders 140 and 150, and transmit appropriate control signals for the status information to the first and second MPEG A / V decoders 140 and 150.

In order to facilitate the understanding of the present invention, a process of PCR that can be processed in a TS processor when the digital receiver receives a conventional 1 channel will be described with reference to FIG. 2.

In Fig. 2, the transmitter 210 uses one oscillator (denoted as OSC: 211) and uses the 27 MHz oscillation frequency generated by the OSC 211 to generate an image and an image from the audio / video encoder 212. The voice data is compressed. The receiver 220 also generates a 27 MHz system time clock signal (hereinafter referred to as a system clock signal) synchronized with an oscillation frequency of 27 MHz used by the transmitter 210 to restore the received signal normally. have. In this way, the transmitter 210 transmits the PCR to use the PLL (Phase Locking Loop) circuit as a reference for restoring the system clock signal of 27 MHz in the receiver 220.

That is, the PCR counter 213 of the transmitter 210 inputs and counts the oscillation frequency oscillated by the OSC 211 as a clock signal, and periodically multiplexes the PCR value obtained by sampling the value of the PCR counter 213. The audio / video encoder 212 multiplexes the encoded audio / video bit stream by 214 and transmits the same to the transport stream.

Then, the demultiplexer 221 of the receiver 220 extracts the PCR value and the audio / video bit string from the transport stream, and temporarily stores the PCR values in the buffer 222, and the audio / video bit string is an audio / video decoder. To 228.

The PCR value first arriving through the buffer 222 is applied to the counter 223. The counter 223 continuously increases the count value by an oscillation frequency generated by a voltage controlled crystal oscillator (VCXO) 227 having the same frequency as that of the oscillator 211 of the transmitter 210 as the center frequency. Here, the oscillation frequency generated by the VCXO 227 becomes the system clock signal.

The PCR value that arrives continuously in addition to the initially arrived PCR value is obtained from the subtractor 224 to obtain a difference from the count value that is increased by the VCXO 227 applied from the counter 223, and the difference value is PWM (Pulse Width). Modulation) is applied to the controller 225. The PWM controller 225 generates a PWM signal corresponding to the difference value. The low pass filter (LPF) 226 drives the VCXO 227 as an analog voltage signal obtained by low pass filtering the PWM signal. Here, PWM controller 225, LPF 226 and VCXO 227 are PLL circuits.

At this time, when the PCR value arriving at the receiver 220 is greater than the count value of the counter 223 at the time of arrival of the PCR value, that is, the oscillator 211 of the transmitter 210 is faster than the VCXO 227 of the receiver 220. Since it is operating at a frequency, the value input to the PWM controller 225 has a positive value. The PWM controller 225 generates a PWM signal that drives the VCXO 227 to operate at a higher frequency, with the counter 223 also increasing the count rate by the VCXO 227.

In the opposite case, that is, when the PCR value arriving at the receiver 220 is smaller than the count value of the counter 223 at the time of arrival of the PCR value, the oscillator 211 of the transmitter 210 causes the VCXO 227 of the receiver 220 to be reached. Since it operates at a slower frequency than), the value input to the PWM controller 226 has a negative value.

When the PWM controller 226 generates a PWM signal for driving the VCXO 227 to operate at a lower frequency, the VCXO 227 generates a frequency signal that lowers the rate of increase of the count value of the counter 223. This allows the VCXO 227 of the receiver 220 to synchronize at the same frequency as the oscillator 211 of the transmitter 210.

On the other hand, when the digital receiver as shown in FIG. 1 should simultaneously perform audio / video decoding of two channels, the system clock signal of each channel used for audio / video decoding of each channel is generated as shown in FIG. A PCR processor having the same complexity with the configuration as described above is required, and when two expensive VCXOs are used, the unit cost increases.

In addition, when two video signals are mixed, they have different oscillation frequencies generated from different VCXOs, and the vertical / horizontal sync frequencies detected using them are different from one channel to another. In a video synthesizer for synthesizing a video signal of a channel, a frame memory for storing a video signal of one channel will be required.

To overcome this disadvantage, i.e. using one PLL circuit and removing the frame memory necessary for the synthesis of video signals having different vertical / horizontal sync frequencies by different oscillation frequencies, as shown in FIG. We propose the same audio / video synchronization circuit.

In FIG. 3, the same reference numerals are assigned to the first and second MPEG A / V decoders 140 and 150 and the microprocessor 170 that are identical to the blocks shown in FIG. In addition, the first and second PCR processors 180 and 190 may be included in the TS processor 130 shown in FIG. 1. Each component of the first and second PCR processors 180 and 190 may be implemented by software of the microprocessor 170 except for the VCXO 186.

Operation of the buffer 181, the first counter 182, the subtractor 183, the PWM controller 184, the LPF 185, and the VCXO 186 of the first PCR processor 180 may be performed by using the buffers illustrated in FIG. 2. Since the operation is the same as that of the VCXO 222-227, detailed operation description thereof will be omitted. The 27 MHz system clock signal generated by the VCXO 186 of the first PCR processor 180 is applied to the first MPEG A / V decoder 140 and used as a driving clock signal for decoding. This first PCR processor 180 may also be referred to as a system clock recoverer.

Meanwhile, the second buffer 191 of the second PCR processor 190 temporarily stores the PCR value of the second channel extracted from the TS processor 130 shown in FIG. 1, and the first PCR value arrives at the second value. It is loaded into the counter 192.

Thereafter, the second counter 192 counts according to the clock signal of the 27 MHz frequency generated by the VCXO 186 and continuously increases the count value until the next PCR value arrives. The register 193 stores the count value of the second counter 192 each time a PCR value arrives.

Therefore, from the PCR value of the second arriving second channel, the second counter at the point in time at which the PCR value arrived from the subtractor 194 through the buffer 191 and the PCR value of the second channel applied from the register 193 arrive. The difference between the count value (192) and the second counter value (PCR value) is obtained. The newly arrived PCR value is loaded into the second counter 192, and the second counter 192 starts from the newly arrived PCR value. The count value is increased according to the clock signal of the 27 MHz frequency applied from 186).

This operation is repeated for successively arriving PCR values. At this time, the difference value (second counter value-PCR value) is continuously accumulated in the microprocessor 170.

The cumulative value from PCR_0, the first PCR accumulated in the microprocessor 170, to the n + 1th PCR_n, is as follows.

Cumulative Value = (PCR_1-Counter2_1) + (PCR_2-Counter2_2) + ... + (PCR_n-Counter2_n)

Here, the counter 2_n is the count value of the second counter 192 when the n + 1th PCR value arrives.

The microprocessor 170 sets thresholds for video decoding and audio decoding of the second channel, respectively, and processes as follows when the accumulated value exceeds the threshold.

In the case of an image signal, when the cumulative value exceeds a positive threshold, it means that the oscillation frequency generated by the second channel transmitter (not shown) is higher than the frequency generated by the VCXO 186 for the first channel. In this case, a skip command (Skip) to discard the video signal of one screen and display the next screen is applied to the second MPEG A / V decoder 150, and the cumulative value and the positive threshold are subtracted by subtracting the cumulative value by a positive threshold. Compare

On the contrary, if the cumulative value exceeds the negative threshold, it means that the oscillation frequency of the second channel transmitter is lower than the VCXO 186 for the first channel. In this case, the current screen is repeated one more time. A command (Repeat) is applied to the second MEPG A / V decoder 150, the absolute value of the negative threshold is added to the accumulated value, and the accumulated value and the negative threshold are again compared.

In the case of a voice signal, when the cumulative value exceeds a positive threshold, it means that the oscillation frequency of the second channel transmitter is higher than the VCXO 186 for the first channel, and in this case, discards a part of the voice signal without hearing. Applies a command to the second MPEG A / V decoder 150, subtracts the accumulated value by a positive threshold, and compares the accumulated value with the positive threshold again.

If the cumulative value exceeds the negative threshold, it means that the oscillation frequency of the second channel transmitter is lower than the VCXO 186 for the first channel. In this case, the second MPEG command to repeatedly listen to a part of the voice signal is performed. The A / V decoder 150 is applied to the A / V decoder 150. The absolute value of the negative threshold is added to the accumulated value, and then the accumulated value is compared with the negative threshold.

The second PCR processor 190 and the microprocessor 170 illustrated in FIG. 3 may be referred to as a decoding controller.

Since the present invention controls the decoding of another channel by using the system clock signal for one channel, only the PLL circuit of one channel is used, and the circuit is simplified because no separate frame memory is required. Since the same vertical and horizontal frequencies have the same effect, it is easy to mix video signals of two channels.

Claims (10)

A digital receiver for recovering two or more compressed coded video and audio signals received: A system clock recoverer for generating a system clock signal by controlling an oscillation frequency oscillating therein by using a program clock reference (PCR) value of one channel; And And a decoding controller for generating a control signal for controlling decoding of the compressed coded video and audio signals of the other channel based on the difference between the PCR value of the other channel and the system clock signal. Synchronization circuit. The method of claim 1, wherein the decoding controller, A counter that loads each time a PCR value of the other channel is received and counts according to the system clock signal to supply a count value; A subtractor for detecting a difference between the received PCR value and the count value of the other channel; And And a control signal generator which accumulates the difference value and compares the accumulated value with a threshold to generate a control signal that skips or repeats decoding of the audio and video signals of the other channel. 3. The audio / video synchronization circuit as claimed in claim 2, wherein the control signal generator is a microprocessor. The method of claim 3, wherein the microprocessor, The respective thresholds for decoding the video signal and the decoding of the audio signal are set to control the decoding of the video signal and the decoding of the audio signal when the absolute value and the set threshold are exceeded. Circuit. The method of claim 4, wherein the microprocessor, In the case of a video signal, if the cumulative value exceeds a positive threshold, a skip control signal is generated to discard the video signal of the current screen and display the next screen. And an iterative control signal for repeatedly displaying. The method of claim 4, wherein the microprocessor, In the case of a voice signal, when the cumulative value exceeds a positive threshold, a control signal is generated that does not hear a part of the voice signal. When the cumulative value exceeds a negative threshold, the partial listening part of the voice signal is repeatedly listened to. And an audio / video synchronization circuit for generating a control signal. A method of synchronizing two or more received compressed coded video and audio signals with each other: (a) extracting a video / audio bit stream and a program clock reference (PCR) value from the transport stream of each channel; (b) generating a system clock signal using a PCR value of one channel and controlling decoding of the compression-encoded video / audio signal of the one channel using the system clock signal; And (c) generating a control signal for controlling the decoding of the compression-coded video / audio signal of the other channel based on the difference between the PCR value of the other channel and the system clock signal. How to sync / video. The method of claim 7, wherein step (c) is (c1) loading each time a PCR value of the other channel is received and counting according to the system clock signal to supply a count value; (c2) detecting a difference between the PCR value of the other channel and the count value; And (c3) accumulating the detected difference value and comparing the accumulated value with a threshold value to generate a skip / repeat control signal for controlling decoding of the audio and video signals of the other channel. Way. The method of claim 8, wherein in step (c3), In the case of a video signal, if the cumulative value exceeds a positive threshold, a skip control signal for discarding the video signal of the current screen and displaying the next screen is generated, and the cumulative value obtained by subtracting the cumulative value by a threshold value is reset again. On the contrary, if the cumulative value exceeds the negative threshold, the control signal is repeatedly generated to display the current screen repeatedly and the absolute value of the negative threshold is added to the cumulative value and the cumulative value is compared again with the threshold. Audio / video synchronization method characterized in that The method of claim 8, wherein in step (c3), In the case of the voice signal, if the cumulative value exceeds a positive threshold, a control signal is generated to discard the voice signal without a part of the voice signal. On the contrary, when the cumulative value exceeds the negative threshold, a control signal for repeatedly listening to a partial region of the voice signal is generated and the cumulative value obtained by adding the absolute value of the negative threshold to the cumulative value is negative. Comparing the thresholds of the audio / video again.

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