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KR100257855B1 - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR100257855B1
KR100257855B1 KR1019970081139A KR19970081139A KR100257855B1 KR 100257855 B1 KR100257855 B1 KR 100257855B1 KR 1019970081139 A KR1019970081139 A KR 1019970081139A KR 19970081139 A KR19970081139 A KR 19970081139A KR 100257855 B1 KR100257855 B1 KR 100257855B1
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South Korea
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gate
ion implantation
semiconductor device
peripheral circuit
contact plug
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Korean (ko)
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KR19990060893A (en
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진승우
이동호
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to reduce the cell leakage current by reducing a width of a depletion area thereby reducing a size of an electric field. CONSTITUTION: A gate(3) and a low density junction section(4) are formed at a cell area and a peripheral circuit area. An insulating layer spacer(5A) is formed only at both sides of the gate(3) in the peripheral circuit area. A high density junction section(6) is formed on a semiconductor substrate(1) at both sides of the gate(3) in the peripheral circuit area. After forming an interlayer dielectric(7), a bit line(9) and a charge storage electrode contact hole are respectively formed. The low density junction section(4) in the cell area is exposed by the bit line(9). Then, a contact plug ion implanting process and a heat treatment process are carried out.

Description

반도체 소자의 제조 방법Manufacturing Method of Semiconductor Device

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 셀 누설 전류(cell leakage current)를 줄여 반도체 소자의 리프레쉬(refresh) 특성을 개선하므로 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of improving cell reliability by reducing cell leakage current and improving refresh characteristics of the semiconductor device. .

종래 반도체 소자의 제조 방법은 셀 지역 및 주변 회로 지역의 반도체 기판에 게이트를 형성하고, 게이트 양측의 반도체 기판에 저농도 이온 주입으로 저농도 접합부를 형성하고, 게이트 측벽에 스페이서(spacer)를 형성하고, 주변 회로 지역만 개방시켜 고농도 이온 주입 공정으로 고농도 접합부를 형성하고, 셀 지역 및 주변 회로 지역 전체에 제 1 층간 절연막을 형성하고, 셀 지역에 비트 라인(bit line)을 형성한 후, 제 2 층간 절연막을 형성하고, 셀 지역에 전하저장전극( storage node)을 형성하는 공정 순으로 이루어진다.In the conventional method of manufacturing a semiconductor device, a gate is formed in a semiconductor substrate in a cell region and a peripheral circuit region, a low concentration junction is formed by low concentration ion implantation in semiconductor substrates on both sides of the gate, a spacer is formed in the gate sidewall, Only the circuit area is opened to form a high concentration junction by a high concentration ion implantation process, a first interlayer insulating film is formed in the cell area and the entire peripheral circuit area, a bit line is formed in the cell area, and then a second interlayer insulating film is formed. And forming a storage node in the cell region.

상기의 공정에서, 스페이서를 형성하기 위한 식각 공정시 저농도 접합부가 식각 손상(etch damage)을 당하게 되어 소자 동작시 셀 누설 전류가 증가되는 문제가 발생된다. 셀 누설 전류를 감소시키기 위하여, 전하저장전극용 콘택홀 형성 후에 노출된 접합부에 콘택 플러그(contact plug) 이온 주입 공정을 실시한다. 종래 콘택 플러그 이온 주입 공정은 LDD 조건으로 진행하거나, 더블 이온 주입(double implant)으로 진행하지만 만족스러운 셀 누설 전류 감소를 얻을 수 없어 리프레쉬 특성을 향상시킬 수 없다. 또한, 단차가 약 10000Å 정도로 커지기 때문에 콘택 마진 확보가 어려워 소자가 고집적화 될수록 오배열(misalign)이 일어나기 쉬우므로 포토리소그라피(photolithography) 공정에서 크리티클(critical)한 공정으로 분류된다.In the above process, during the etching process for forming the spacer, the low-concentration junction is subjected to etch damage, thereby causing a problem of an increase in cell leakage current during device operation. In order to reduce cell leakage current, a contact plug ion implantation process is performed on the exposed junction after the formation of the contact hole for the charge storage electrode. Conventional contact plug ion implantation processes proceed to LDD conditions or double ion implantation, but satisfactory cell leakage current reduction cannot be obtained, and thus the refresh characteristics cannot be improved. In addition, since the step height is increased to about 10000Å, it is difficult to secure contact margins, so that misalignment is more likely to occur as the device is highly integrated, and thus, it is classified as a critical process in a photolithography process.

따라서, 본 발명은 셀 누설 전류를 줄여 반도체 소자의 리프레쉬 특성을 개선시키므로 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving cell reliability by reducing cell leakage current and improving refresh characteristics of the semiconductor device.

이러한 목적을 달성하기 위한 본 발명의 반도체 소자 제조 방법은 셀 지역 및 주변 회로 지역 각각에 게이트 및 저농도 접합부를 형성하는 단계; 상기 주변 회로 지역의 게이트 양측부에만 절연막 스페이서를 형성하고, 상기 주변 회로 영역의 게이트 양측의 반도체 기판에 고농도 접합부를 형성하는 단계; 층간 절연막을 형성한 후, 셀 지역의 저농도 접합부가 노출되는 비트 라인 및 전하전장전극용 콘택홀을 각각 형성하는 단계; 및 듀얼 틸트를 이용한 더블 이온 주입으로 콘택 플러그 이온 주입 공정 및 열처리를 실시하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving this object comprises the steps of forming a gate and a low concentration junction in each of the cell region and the peripheral circuit region; Forming insulating film spacers only on both sides of the gate of the peripheral circuit region, and forming a high concentration junction on the semiconductor substrate on both sides of the gate of the peripheral circuit region; Forming an interlayer insulating film, and then forming bit line and contact hole for a charge-electrode electrode, each of which exposes a low concentration junction of a cell region; And performing a contact plug ion implantation process and heat treatment by double ion implantation using dual tilt.

도 1(a) 내지 도 1(e)는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도.1A to 1E are cross-sectional views of devices for explaining a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2는 종래 LDD 조건으로 콘택 플러그 이온 주입 공정을 실시한 후에 저농도 접합부의 셀 누설 전류를 측정한 데이터.Figure 2 is a data measurement of the cell leakage current of the low-concentration junction after performing the contact plug ion implantation process under the conventional LDD conditions.

도 3은 종래 더블 이온 주입(틸트 이온 주입 없이) 조건으로 콘택 플러그 이온 주입 공정을 실시한 후에 저농도 접합부의 셀 누설 전류를 측정한 데이터.Figure 3 is a data measurement of the cell leakage current of the low-concentration junction after performing the contact plug ion implantation process under the conditions of conventional double ion implantation (without tilt ion implantation).

도 4는 본 발명의 듀얼 틸트 더블 이온 주입 조건으로 콘택 플러그 이온 주입 공정을 실시한 후에 저농도 접합부의 셀 누설 전류를 측정한 데이터.Figure 4 is a data measuring the cell leakage current of the low-concentration junction after the contact plug ion implantation process under the dual tilt double ion implantation conditions of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>

1: 반도체 기판 2: 필드 산화막1: semiconductor substrate 2: field oxide film

3: 게이트 4: 저농도 접합부3: gate 4: low concentration junction

5: 절연막 5A: 절연막 스페이서5: insulating film 5A: insulating film spacer

6: 고농도 접합부 7: 제 1 층간 절연막6: high concentration junction portion 7: first interlayer insulating film

8: 콘택홀 9: 비트 라인8: contact hole 9: bit line

10: 콘택 플러그 11: 제 2 층간 절연막10: contact plug 11: second interlayer insulating film

12: 전하저장전극 13: 유전체막12: charge storage electrode 13: dielectric film

14: 플레이트 전극14: plate electrode

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1(a) 내지 도 1(e)는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도이다.1A to 1E are cross-sectional views of devices for explaining a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 1(a)를 참조하면, 반도체 기판(1)에 필드 산화막(2)을 형성하여 액티브 영역(active region)을 확정하고, 셀 지역 및 주변 회로 지역 각각에 게이트(3)를 형성한 후, 저농도 이온 주입 공정으로 각 게이트(3) 양측의 반도체 기판(1)에 저농도 접합부(4)를 형성한다. 게이트(3)를 포함한 전체 구조상에 스페이서용 절연막(5)을 형성한다.Referring to FIG. 1A, after forming a field oxide film 2 in a semiconductor substrate 1 to determine an active region, and forming a gate 3 in each of a cell region and a peripheral circuit region, The low concentration junction 4 is formed in the semiconductor substrate 1 on each side of each gate 3 by a low concentration ion implantation process. The insulating film 5 for spacers is formed on the whole structure including the gate 3.

스페이서용 절연막(5)은 산화물(oxide), 언도프트 폴리실리콘(undoped polysilicon) 및 질화물(nitride)중 적어도 어느 하나로 형성된다.The spacer insulating film 5 is formed of at least one of oxide, undoped polysilicon, and nitride.

도 1(b)를 참조하면, 주변 회로 지역만 개방되도록 마스킹한 후, 스페이서 식각 공정을 통해 주변 회로 영역의 게이트(3) 양측부에 절연막 스페이서(5A)를 형성하고, 고농도 이온 주입 공정으로 주변 회로 영역의 게이트(3) 양측의 반도체 기판(1)에 고농도 접합부(6)를 형성한다. 셀 지역에는 게이트(3)와 저농도 접합부(4)로 된 트랜지스터가 구성되고, 주변 회로 지역에는 게이트(3)와 저농도 접합부(4)와 고농도 접합부(6)로 된 LDD 구조의 트랜지스터가 구성된다.Referring to FIG. 1B, after masking only the peripheral circuit region to be opened, an insulating layer spacer 5A is formed at both sides of the gate 3 of the peripheral circuit region through a spacer etching process, and the peripheral region is subjected to a high concentration ion implantation process. The high concentration junction 6 is formed in the semiconductor substrate 1 on both sides of the gate 3 of the circuit region. In the cell region, a transistor having a gate 3 and a low concentration junction 4 is formed, and in the peripheral circuit region, a transistor having an LDD structure having a gate 3, a low concentration junction 4 and a high concentration junction 6 is formed.

도 1(c)를 참조하면, 트랜지스터를 포함한 전체 구조상에 제 1 층간 절연막(7)을 형성한 후, 콘택 공정을 통해 제 1 층간 절연막(7)의 선택된 부분을 셀 지역의 접합부(4)가 노출되는 시점까지 식각 하여 비트 라인 및 전하전장전극용 콘택홀(8)을 각각 형성한다. 접합부(4)의 셀 누설 전류를 줄이기 위하여, 콘택 플러그 이온 주입(contact plug implant) 공정을 실시하되, 콘택 플러그 이온 주입 공정은 듀얼 틸트(dual tilt)를 이용한 더블(double) 콘택 플러그 이온 주입 방법으로 진행한다.Referring to FIG. 1C, after the first interlayer insulating film 7 is formed over the entire structure including the transistors, the selected portion of the first interlayer insulating film 7 is formed through a contact process. The bit line and the charge-electrode electrode contact holes 8 are formed by etching until the exposed point. In order to reduce the cell leakage current of the junction portion 4, a contact plug implant process is performed, but the contact plug ion implantation process is a double contact plug ion implantation method using dual tilt. Proceed.

전하저장전극용 콘택홀(8)을 비트 라인용 콘택홀(8) 형성시 동시에 형성하므로 전하저장전극 콘택 단차를 줄일 수 있으며, 이 단차는 약 6000Å 정도로 기존의 10000Å에 비하여 약 4000Å 정도를 줄일 수 있다. 따라서, 이후에 실시되는 듀얼 틸트 더블 콘택 방식의 콘택 플러그 이온 주입을 용이하게 한다. 듀얼 틸트 더블 콘택 방식을 이용한 콘택 플러그 이온 주입 공정은 먼저, 90 내지 200 KeV의 에너지로 불순물 이온 예를 들어, 인(P)일 경우 2E12 내지 5E13 ions/cm2도우즈 하여 틸트 범위(tilt range)를 0°내지 15°로 하고, 트위스트 범위(twist range)를 0°내지 50°로 하여 진행하고, 그 다음 10 내지 50 KeV의 에너지로 불순물 이온 예를 들어, 인(P)일 경우 2E12 내지 5E13 ions/cm2도우즈 하여 틸트 범위(tilt range)를 0°내지 2°로 하고, 트위스트 범위(twist range)를 0°내지 50°로 하여 진행한다. 이와 같이 듀얼 틸트 더블 콘택 방식을 이용하여 저농도 접합부(4)에 콘택 플러그 이온을 주입하므로 저농도 접합부(4)가 형성되는 게이트(3) 하단 부위까지 카운터 도핑(counter doping)이 가능하게 된다.Since the charge storage electrode contact hole 8 is formed at the same time as the bit line contact hole 8 is formed, the charge storage electrode contact step can be reduced, and this step can be reduced to about 6000 mW by about 6000 mW compared to the existing 10000 mW. have. Therefore, the contact plug ion implantation of the dual tilt double contact method to be performed later is facilitated. The contact plug ion implantation process using the dual tilt double contact method first starts the tilt range by doping 2E12 to 5E13 ions / cm 2 with impurity ions, for example, phosphorus (P) at an energy of 90 to 200 KeV. To 0 ° to 15 °, the twist range to 0 ° to 50 °, and then at an energy of 10 to 50 KeV for impurity ions, e.g., phosphorus (P) 2E12 to 5E13 Dosing at ions / cm 2 advances the tilt range from 0 ° to 2 ° and the twist range from 0 ° to 50 °. As such, since contact plug ions are implanted into the low concentration junction 4 using the dual tilt double contact method, counter doping is possible to the lower portion of the gate 3 where the low concentration junction 4 is formed.

도 1(d)를 참조하면, 콘택 플러그 이온 주입 공정후, 750 내지 1050℃의 온도에서 5 내지 60초간 열처리하고, 전도성 물질 증착 및 패터닝 공정으로 비트 라인(9)을 형성하며, 비트 라인(9) 형성시 전하저장전극의 콘택 플러그(10)도 동시에 형성된다.Referring to FIG. 1 (d), after the contact plug ion implantation process, heat treatment is performed at a temperature of 750 to 1050 ° C. for 5 to 60 seconds, and a bit line 9 is formed by a conductive material deposition and patterning process. ), The contact plug 10 of the charge storage electrode is also formed at the same time.

도 1(e)를 참조하면, 비트 라인(9)이 형성된 전체 구조상에 제 2 층간 절연막(11)을 형성한 후, 제 2 층간 절연막(11)의 선택된 부분을 식각 하여 콘택 플러그(10)를 노출시키고, 노출된 콘택 플러그(10)에 연결되는 전하저장전극(12)을 형성한다. 이후, 전하저장전극(12)상에 유전체막(13) 및 플레이트 전극(14)을 형성하여 캐패시터가 완성된다.Referring to FIG. 1E, after forming the second interlayer insulating layer 11 on the entire structure in which the bit line 9 is formed, the contact plug 10 is formed by etching the selected portion of the second interlayer insulating layer 11. And a charge storage electrode 12 connected to the exposed contact plug 10. Thereafter, the dielectric film 13 and the plate electrode 14 are formed on the charge storage electrode 12 to complete the capacitor.

도 2 내지 도 4는 64M를 근거로 10K 셀 어레이에서 종래 콘택 플러그 이온 주입 공정 및 본 발명의 콘택 플러그 이온 주입 공정후에 저농도 접합부의 셀 누설 전류를 측정한 데이터이다.2 to 4 are data of measuring the cell leakage current of the low concentration junction after the conventional contact plug ion implantation process and the contact plug ion implantation process of the present invention in a 10K cell array based on 64M.

도 2는 종래 LDD 조건으로 콘택 플러그 이온 주입 공정을 실시한 후에 저농도 접합부의 셀 누설 전류를 측정한 데이터이고, 도 3은 종래 더블 이온 주입(틸트 이온 주입 없이) 조건으로 콘택 플러그 이온 주입 공정을 실시한 후에 저농도 접합부의 셀 누설 전류를 측정한 데이터이며, 도 4는 본 발명의 듀얼 틸트 더블 이온 주입 조건으로 콘택 플러그 이온 주입 공정을 실시한 후에 저농도 접합부의 셀 누설 전류를 측정한 데이터이다.FIG. 2 shows data of measuring a cell leakage current of a low concentration junction after performing a contact plug ion implantation process under a conventional LDD condition, and FIG. 3 after performing a contact plug ion implantation process under a conventional double ion implantation (without tilt ion implantation). It is the data which measured the cell leakage current of the low concentration junction, and FIG. 4 is the data which measured the cell leakage current of the low concentration junction after performing the contact plug ion implantation process on the dual tilt double ion implantation conditions of this invention.

측정 데이터에서 알 수 있듯이, 본 발명의 듀얼 틸트 더블 콘택 방식을 이용하여 저농도 접합부에 콘택 플러그 이온을 주입하므로 저농도 접합부가 형성되는 게이트 하단 부위까지 카운터 도핑이 가능하게 되어 공핍 영역 폭을 줄여 전기장을 감소시켜 셀 누설 전류가 줄어듦을 알 수 있다. 이 측정 데이터는 T-SUPREM4를 이용한 시뮬레이션 결과와도 일치한다.As can be seen from the measurement data, contact plug ions are injected into the low concentration junction using the dual tilt double contact method of the present invention, so that counter doping is possible to the lower portion of the gate where the low concentration junction is formed, thereby reducing the width of the depletion region to reduce the electric field. It can be seen that the cell leakage current is reduced. This measurement data is also consistent with the simulation results using T-SUPREM4.

상술한 바와 같이, 본 발명은 종래 스페이서 식각 공정에 의해 발생되는 저농도 접합부의 손상이 방지되어 셀 누설 전류의 요인을 최소화시키므로 리프레쉬 특성을 향상시킬 수 있으며, 콘택홀의 단차를 줄이므로 콘택 마진이 확보되어 오배열과 장시간의 식각으로 인한 식각 타겟 변화(etch target variation)가 줄어 접합부의 식각 손상을 줄일 수 있다. 또한 듀얼 틸트 더블 방식으로 콘택 플러그 이온을 주입하므로 저농도 접합부가 형성되는 게이트 하단 부위까지 카운터 도핑이 가능하게 되어 공핍 영역 폭을 줄여 전기장을 감소시켜 셀 누설 전류를 개선하여 소자의 리프레쉬 특성을 향상시킬 수 있다.As described above, the present invention can prevent the damage of the low concentration junction caused by the conventional spacer etching process, thereby minimizing the factor of cell leakage current, thereby improving the refresh characteristics, and reducing the step height of the contact hole, thereby ensuring a contact margin. Etch target variation due to misalignment and prolonged etching may be reduced to reduce etch damage of the junction. In addition, the contact plug ions are implanted in a dual tilt double method, which allows counter doping to the lower gate portion where the low-concentration junction is formed, thereby reducing the depletion area width, reducing the electric field, and improving cell leakage current, thereby improving device refresh characteristics. have.

Claims (5)

셀 지역 및 주변 회로 지역 각각에 게이트 및 저농도 접합부를 형성하는 단계;Forming a gate and a low concentration junction in each of the cell region and the peripheral circuit region; 상기 주변 회로 지역의 게이트 양측부에만 절연막 스페이서를 형성하고, 상기 주변 회로 영역의 게이트 양측의 반도체 기판에 고농도 접합부를 형성하는 단계;Forming insulating film spacers only on both sides of the gate of the peripheral circuit region, and forming a high concentration junction on the semiconductor substrate on both sides of the gate of the peripheral circuit region; 층간 절연막을 형성한 후, 셀 지역의 저농도 접합부가 노출되는 비트 라인 및 전하전장전극용 콘택홀을 각각 형성하는 단계; 및Forming an interlayer insulating film, and then forming bit line and contact hole for a charge-electrode electrode, each of which exposes a low concentration junction of a cell region; And 듀얼 틸트를 이용한 더블 이온 주입으로 콘택 플러그 이온 주입 공정 및 열처리를 실시하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 제조 방법.A method of manufacturing a semiconductor device comprising the step of performing a contact plug ion implantation process and heat treatment by double ion implantation using dual tilt. 제 1 항에 있어서,The method of claim 1, 상기 절연막 스페이서는 산화물, 언도프트 폴리실리콘 및 질화물 중 적어도 어느 하나를 증착하고, 스페이서 식각 공정을 통해 형성되는 것을 특징으로 하는 반도체 소자의 제조 방법.The insulating film spacer is a method of manufacturing a semiconductor device, characterized in that the deposition of at least one of oxide, undoped polysilicon and nitride, and through a spacer etching process. 제 1 항에 있어서,The method of claim 1, 상기 콘택 플러그 이온 주입 공정은 90 내지 200 KeV의 에너지로 틸트 범위를 0°내지 15°로 하고, 트위스트 범위를 0°내지 50°로 하여 1차 진행하고, 10 내지 50 KeV의 에너지로 틸트 범위를 0°내지 2°로 하고, 트위스트 범위를 0°내지 50°로 하여 2차 진행하는 것을 특징으로 하는 반도체 소자의 제조 방법.The contact plug ion implantation process proceeds first with a tilt range of 0 ° to 15 ° with an energy of 90 to 200 KeV, a twist range of 0 ° to 50 °, and a tilt range with an energy of 10 to 50 KeV. A method of manufacturing a semiconductor device, characterized by advancing second at 0 ° to 2 ° and setting the twist range to 0 ° to 50 °. 제 1 항 또는 제 3 항에 있어서,The method according to claim 1 or 3, 상기 콘택 플러그 이온 주입 공정은 2E12 내지 5E13 ions/cm2도우즈로 1차 진행하고, 2E12 내지 5E13 ions/cm2도우즈로 2차 진행하는 것을 특징으로 하는 반도체 소자의 제조 방법.The contact plug ion implantation process method of producing a semiconductor device, characterized in that to proceed with the primary 2E12 to about 5E13 ions / cm 2 dose, and proceeds to the second 2E12 to about 5E13 ions / cm 2 dose. 제 1 항에 있어서,The method of claim 1, 상기 열처리 공정은 750 내지 1050℃의 온도에서 5 내지 60초간 실시하는 것을 특징으로 하는 반도체 소자의 제조 방법.The heat treatment process is a method of manufacturing a semiconductor device, characterized in that performed for 5 to 60 seconds at a temperature of 750 to 1050 ℃.
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