KR100259092B1 - Circuit for data transmission - Google Patents

Abstract

The present invention relates to a data transmission circuit which reduces the number of transitions of data during data transmission. Particularly, a number of transitions for outputting the number of transitions of serial data input by counting the number of resultant '1' after exclusively arranging the serial data together. An output unit, a DC balancing logic unit for determining whether DC balancing is required, a controller for outputting control signals according to the number of transitions of the transition number output unit and the output value of the DC balancing logic unit, and a combination of control signals of the controller It consists of an encoder that outputs the even bits of the serial data as it is or is inverted and outputs to the DC balancing output, or the entire data is output as it is or inverted for DC balancing to the DC balancing output. Q [0: 9 including DC balancing ] To reduce the number of transitions up to four times, and if the number of transitions is small By transmission by reducing the average transition number, as can be transmitted stably even during high-speed transmission by the EMI noise and reduced as much as the data transport.

Description

Data transmission circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data transmission, and more particularly, to a data transmission circuit which reduces the number of transitions of data during data transmission.

As the transmission speed of data continues to increase, the transition rate of the data increases, which causes noise and electromagnetic interference (EMI) to increase.

Therefore, a method to solve this problem has been studied and one of them is shown in FIG.

1, the number of transitions is reduced by serial transmission of Q [0: 9] which adds two bits by encoding D [0: 7], which is 8-bit data, and performs a function of DC balancing. average) EMI is reduced.

That is, the encoder 11 outputs the least significant bit of the 8-bit data D [0: 7] as it is using seven exclusive ora gates, and performs the exclusive oaring with the least significant bit from the next bit. The output of E1 [0: 7] is output by exclusive ORing with the output of the OR gate. In addition, using the seven exclusive Noah gates, the least significant bit of the 8-bit data D [0: 7] is output as it is, and the least significant next bit is exclusively nominated with the least significant bit, and the next bit is the output of the previous exclusive Noah gate. Outputs E0 [0: 7] with an exclusive nooring. The output data E1 [0: 7] and E0 [0: 7] are inputted to the data adding unit 12, and the transition control bits 1 or 0 are added and outputted, and the output E [of the data adding unit 12 is output. 0: 8] is input to the DC balancing logic unit 15.

At this time, the counter 13 counts the number of 1 of the input serial data D [0: 7] and outputs the result to the control signal output unit 14, and the control signal output unit 14 has a number of '1's of 4. If less than the control signal CONT is output to the data adder 12 to add '0' as the transition control bit, and if the number of '1' is 4 or the least significant bit D [0] = 1, the transition control bit is' The control signal CONT is output to the data adding unit 12 to add 1 '. The DC balancing logic unit 15 adds one bit for data balancing to the output E [0: 8] of the data adding unit 12 again.

As can be seen in the operation example of FIG. 2, if D [0: 7] is serially transmitted as it is, up to seven transitions may occur. E [0: 7] encoded by exclusive or gated exclusive ora gates can have up to three transitions, and E [0: 8] with the addition of the transition control bit can have up to four transitions. In addition, since DC balancing is important in serial transmission, Q [0: 9], which adds bits to control this, therefore causes a maximum of five transitions.

By reducing the number of peak transitions by encoding and adding DC balancing, this reduces noise in data transmission and reduces EMI.

That is, as shown in (a) of FIG. 2, D [0: 7] has four transitions, but the encoding result of E [0: 7] has only two transitions, resulting in a decrease in the number of transitions. Looking at (b), D [0: 7] has two transitions, but the encoding result, E [0: 7], has only one transition, resulting in reduced transitions.

However, FIG. 1 described above always encodes the case where D [0: 7] originally had one or two transitions, as in the case of (c) or (d) of FIG. 2, and as a result, E [0: 8] is There are also cases where there are four transitions, and since Q [0: 9] after DC balancing transitions up to five times, the number of transitions increases, so that the average number of transitions does not decrease much.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a data transmission circuit that improves the safety of data transmission by reducing noise or EMI by encoding serial data so as to reduce the number of transitions of data. .

1 is a circuit diagram for a conventional data transmission

2A to 2D are diagrams showing examples of the number of transitions of an encoding result according to the number of transitions of data D [0: 7] input by FIG.

3 is a circuit diagram for data transmission according to the present invention.

4A to 4D are diagrams showing examples of the number of transitions of an encoding result according to the number of transitions of data D [0: 7] input in FIG.

Explanation of symbols for main parts of the drawings

31: encoder 32: DC balancing logic section

33: transition determination unit 34: counter

35: control unit

The data transmission circuit according to the present invention for achieving the above object, the output of the number of transitions to output the number of transitions of the serial data input by counting the number of the resulting '1' after the mutual data mutually exclusive And a DC balancing logic unit for determining whether DC balancing is required, a controller for outputting control signals according to the number of transitions of the transition number output unit and the output value of the DC balancing logic unit, and a combination of the control signals of the controller. It may include an encoding unit that outputs the even bits of the data as it is or inverted to the DC balancing output unit, and also outputs the entire data as it is or inverted for DC balancing output to the DC balancing output unit.

By using this data transmission method, the number of transitions of Q [0: 9] including DC balancing can be reduced to a maximum of four, while the small number of transitions can be transmitted as it is, thereby reducing the average transition times to further reduce noise or EMI.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a data transmission circuit according to the present invention. When 8-bit data D [0: 7] is input, even bits are inverted or inverted by a combination of an IEVEN signal and a BAL signal, or all bits are intact. Alternatively, the DC balancing logic unit 32 that receives the encoder 31, the IEVEN and the BAL signals, which are inverted, and the output E [0: 7] of the encoder 31, and adds and outputs bits for controlling the DC balancing, A transition discriminating unit 33 for outputting the transition state X [0: 6] of the input data D [0: 7] by exclusively ORing 8-bit data D [0: 7], respectively, and the transition discriminating unit 33 IEVEN that controls the encoding of the encoder 31 by using the counter 34 for outputting the number of transitions that count the number of '1' output from the output, the output of the DC balancing logic unit (DCBAL) and the output of the counter 34. And a control unit 35 for outputting a BAL signal.

The encoder 31 includes a plurality of inverters for inverting each bit of the input data, a plurality of first transfer gates for respectively controlling the output of the input data bits, and a plurality of inverters for respectively controlling the output of the data inverted by the inverter. Each bit of the 8-bit data D [0: 7] input by the second transmission gate is inputted to the first transmission gate as it is, is inverted through the inverter, and then input to the second transmission gate, and the IEVEN signal is even. The first or second transfer gate of bits is activated, and the result of the exclusive OR of the IEVEN signal and the BAL signal activates the first or second transfer gate of odd bits. For example, when the IEVEN and BAL signals are '11', the second transfer gate of the even bits and the first transfer gate of the odd bits are activated, and the even bits are inverted and output. If '10', the second transfer gate of even bits and the second transfer gate of odd bits are activated, and all bits of the input data are inverted and output. If '01', the first transfer gate of even bits and the second transfer gate of odd bits are activated to output even bits, and the odd bits are inverted and output. If '00', the second transfer gate of even bits and the first transfer gate of odd bits are activated to output all bits of the input data as they are.

The transition discriminating unit 33 is composed of seven exclusive oar gates, which exclusively rings the least significant bit and the next bit of the 8-bit data D [0: 7], and again the next bit and the exclusive oring from the least significant next bit. The process is performed up to the most significant bit, and the result is X [0: 6] indicating the transition state by exclusively ORing the most significant previous bit and the most significant bit. For example, if the input data D [0: 7] is '00110011', the output X [0: 6] of the transition determining unit 33 is '0101010'.

That is, the encoder 31 determines whether to invert even bits among the data D [0: 7] input by the 'IEVEN' signal generated by the control unit 35, and determining this is the transition determining unit 33. By counting the number of '1' of X [0: 6] produced by an exclusive OR gate between D [0: 7] bits in the counter 34.

Here, the number of '1' means the number of transitions of serial data. If the number exceeds 3 times, the even bits are inverted to make the number of transitions of E [0: 7] resulting from the encoding within 3 times.

For example, when D [0: 7] makes seven transitions, it is the case of '10101010' or '01010101'. At this time, inverting the even bits causes E [0: 7] to be equal to '00000000' or '11111111'. The transition count is 0. Likewise, if D [0: 7] is 6 times, E [0: 7] is 1 time, and if D [0: 7] is 5 times, E [0: 7] is 2 times If D [0: 7] is four times, E [0: 7] is three times.

In this case, if 'IEVEN' and 'BAL' having information inverted even bits are set to '1' and '1' and output to the DC balancing logic unit 32, the final data Q [0: 9] is maximum of 4 Only the meeting transition will take place.

If it is necessary to invert E [0: 7] as a whole by the DC balancing logic unit 32, if the even bits are already inverted, 'IEVEN' and 'BAL' are set to '0' and '1', If even bits are passed as it is, if 'IEVEN' and 'BAL' are set to '1' and '0', DC balancing can be easily implemented by integrating the even bits in order to reduce the number of transitions as shown in FIG. . This is because inversion of inversion is the original value.

As shown in (a) to (d) of FIG. 4 applied to the present invention as it is in the case of (a) to (d) of FIG. 2, Q [0] including the encoding bit and the DC balancing bit The number of transitions of: 9] is a maximum of four times, and the number of transitions of the original D [0: 7] is a maximum of seven times, which is much reduced, and is smaller than the maximum of five times in the case of FIG.

In addition, in the prior art of FIG. 1, the number of transitions of Q [0: 9] is increased up to 5 times by encoding, even when the number of transitions of D [0: 7] is 1, 2 times. The technology has the advantage that the average number of transitions is always reduced by transmitting as it is in this case.

For example, as shown in (a) of FIG. 4, the input data D [0: 7] has four transitions, but E [0: 8] having the transition control bits added to the encoding result has only three transitions. 4 (b), even when the input data D [0: 7] does not exceed two transitions, i.e., three transitions, E [0: 8] adding the transition control bit to the encoding result is only one transition. Is happening. Referring to FIG. 4C, the input data D [0: 7] does not exceed four times, that is, five times even if it does not exceed one transition, that is, three times. Similarly, in FIG. 4D, the input data D [0: 7] does not exceed two transitions, that is, three times, but E [0: 8] in which the transition control bit is added to the encoding result occurs only three transitions. have.

According to the data transmission circuit according to the present invention as described above, by outputting the even bits and odd bits of the data as it is or inverted by the control of the number of transition of the serial data input and the output value of the DC balancing logic unit, Reduces the number of transitions of Q [0: 9], including DC balancing, to up to four times. Also, if the number of transitions is small, the number of transitions is reduced and the average number of transitions is reduced. Data can be transmitted stably.

Claims (2)

A transition number output unit for outputting the number of transitions of the serial data input by counting the number of '1's resulting from mutually exclusive serial data; A DC balancing logic section for determining if DC balancing is needed, A controller for outputting control signals according to the number of transitions of the transition number output unit and the output value of the DC balancing logic unit; Combining the control signals of the control unit as it is or inverts the even bits of the serial data output to the DC balancing output unit, and for encoding or inverting the entire data as it is for DC balancing output to the DC balancing output unit A data transmission circuit. The method of claim 1, wherein the encoding unit A plurality of inverters for inverting respective bits of the input serial data, a plurality of first transfer gates for respectively controlling the output of the input data bit values, and a plurality of transfer gates for respectively controlling the output of the data inverted by the inverter And the IEVEN signal output from the controller activates the first or second transmission gate of even bits, and the result of the exclusive OR of the IEVEN signal and the BAL signal activates the first or second transmission gate of odd bits. A data transmission circuit, characterized in that.