KR100252502B1 - Apparatus for converting utopia level-1 to utopia level-2 in atm - Google Patents

Abstract

The present invention relates to an apparatus for converting a utopia level 1 interface into a utopia level 2 interface in an ATM communication device.

The present invention includes n byte-word converters 520a to 520d which receive byte data from a utopia Level 1 interface device and convert it into word units; N word FIFOs 530a to 530d for receiving and storing word units of data from the byte-word converter; A round robin address generator 560 for generating n identifiable addresses in a round robin manner; A multiplexer 540 for selecting and multiplexing one of the outputs of word FIFOs according to an address generated by the round robin address generator; A Utopia Level 1 Interface which receives a TxEnb * signal for Utopia Level 1 type handshake from a Utopia Level 1 interface device and provides a TxClav signal to the Utopia Level 1 interface device. Controller 510; And a utopia level 2 interface controller 550.

Therefore, in the present invention, when the physical layer is Utopia level 2, the ATM layer is Utopia level 1, or the physical layer is Utopia level 1, and the ATM layer is Utopia level 2, Utopia level 1 is converted to level 2 to convert devices of level 1 and level 2. It can be easily matched.

Description

An apparatus for converting UTOPIA level 1 to UTOPIA level 2 in ATM

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a utopia interface device for matching between an ATM layer and a physical layer in asynchronous transfer mode (ATM) communication, and more particularly, to an apparatus for converting a utopia level 1 interface into a utopia level 2 interface.

In recent years, with the rapid growth of the multimedia field, a communication network for transmitting a wideband signal in a digital manner such as a video signal has been required, resulting in the emergence of a Broadband-Integrated Services Digital Network (B-ISDN). With the advent of broadband ISDN, it is possible to meet various service needs of users, and in particular, it is possible to transmit moving images, which has become a foundation for realizing the dream of the future information society.

The B-ISDN requires an ATM exchange technology. The ATM transfers information using a fixed length (53 bytes) information block called a cell using the ATDM method. This ATM communication system forms a hierarchical structure as shown in Table 1 below and has standardized standards for each layer.

hierarchy Sublayer function Upper hierarchy - Higher layer function ATM Adaptation Layer Convergence (CS) sublayer Convergence function Cutting and recombination Cutting function and recombination function ATM layer - General Flow Control and Cell Header Processing Physical layer Transmission Convergence (TC) HEC signal generation and extraction function Physical medium Bit time information function

As shown in Table 1, the ATM communication method is divided into vertical structures such as a physical layer, an ATM layer, an ATM adaptation layer (AAL), and a higher protocol layer, and the AAL layer is a cut and recombination sublayer (SAR). The Segmentation And Reassembly sublayer (CS) and Convergence Sublayer (CS) sublayers are subdivided, and the physical layers are subdivided into Physical Media (PM) and Transmission Convergence (TC) sublayers.

In the ATM communication system, the service is classified into classes A to D according to the service of the user, that is, the characteristics of the source. Class A service is a real-time, constant bit rate, connectivity service, Class B service is a real-time, variable bit rate, connectivity service, Class C service is a non-real time, variable bit rate, non-connected service, Class D service Is a non-real time, variable bit rate, connectionless service. Representative examples of such services include identity rate video signals, variable rate video signals, connectivity data transmission, and connectionless data transmission.

Meanwhile, AAL protocols corresponding to the above services are classified into AAL1 to AAL5 as shown in Table 2 below.

AAL form Typical feature AAL-1 Support class A service of equal bit rate AAL-2 Support real-time, variable bit rate Class B service AAL-3 / 4 Support C and D class services with variable bit rate AAL-5 High speed service by simplifying AAL-3 / 4 function

As shown in Table 2, the AAL layer is divided horizontally as AAL1, AAL2, AAL3 / 4, AAL5 in order to efficiently process the service according to the type of service. In addition, each AAL layer transparently delivers a service data unit (U-SDU) from a service user, detects transmission errors, and performs information identification and buffer allocation. ) And the variable-length data received from the convergence sublayer (CS) to create an ATM cell, transfer it to the ATM layer, receive the ATM cell from the ATM layer, and reassemble it to converge the sublayer protocol data unit (CS-PDU: CS). Subdivided into break and recombination sublayers (SAR) to recover the Protocol Data Unit.

On the other hand, the ATM communication device sets a standard connection protocol between the ATM layer and the physical layer in order to provide flexibility for using various transmission media, and even if the physical layer is implemented in various forms, the ATM communication device is easily connected with the SAR layer. You can connect. In other words, "UTOPIA (the Universal Test & Operations PHY Interface for ATM)" is a standard interface method defined for connecting the ATM layer and the physical layer. The purpose of defining the utopia interface standard is first, common and standardization between the ATM layer and the physical layer. By specifying the interface, it is possible to expect cost savings, to enable the use of FIFO between ATM and physical layer devices with different speeds, and to use stream mode in ATM-physical devices that use the throttle interface rate. Fourth, to support the rate from 100Mbps to 155Mbps as a common interface of 8-bit data path.

However, Utopia Interface Standards are divided into Utopia Level 1 and Utopia Level 2 so that they can be selected according to the application. That is, Utopia Level 1 is based on 8-bit data transmission as a conventional Utopia method, and Utopia Level 2 is a new standard that is based on 16-bit data transmission.

Therefore, in order to access a device using Utopia Level 1 and a device using Utopia Level 2, a device for converting Utopia Level 1 to Utopia Level 2 is required.

Accordingly, an object of the present invention is to provide a utopia level converter for converting utopia level 1 to utopia level 2 so as to connect different levels of utopia interface devices. .

In order to achieve the above object, the present invention provides an ATM apparatus for matching a device providing n Utopia Level 1 interfaces with a device supporting one Utopia Level 2 interface, wherein the byte from the Utopia Level 1 interface device is used. N byte-word converters each receiving unit data and converting the data into word units; N word FIFOs for receiving and storing word units of data from the byte-word converter; A round robin address generator for generating n identifiable addresses in a round robin manner; A multiplexer for selecting and multiplexing one of the outputs of the word FIFOs according to an address generated by the round robin address generator; Utopia Level 1 which receives a TxEnb * signal for a Utopia Level 1 type handshake from the Utopia Level 1 interface device and provides a TxClav signal to the Utopia Level 1 interface device, respectively. An interface controller; It is connected to the utopia level 1 interface controller and receives a transmit cell enable signal (TxClav) and a transmit address (TxAddr) for a utopia level 2 type handshake from a utopia level 2 interface device, and receives the utopia level 2 interface device. And a Utopia Level 2 interface controller for providing a transmit enable (TxEnb *) signal and providing a control signal for enabling the multiplexer.

1 is a signal timing diagram during transmission of utopia level 1,

2 is a signal timing diagram upon reception of utopia level 1;

3 shows the structure of an ATM cell at utopia level 1,

4 is a diagram for describing utopia level 2;

5 is a block diagram illustrating an apparatus for converting utopia level 1 to utopia level 2 according to the present invention;

6 is a signal connection diagram of the Utopia level 2 interface and the multiplexer shown in FIG.

7 is an internal transmission timing diagram of utopia level 2. FIG.

* Explanation of symbols for main parts of the drawings

500: Utopia Level 2 Inverter

502a, 502b, 502c, 502d: Utopia Level 1 Interface Device

504: Utopia Level 2 Interface Device

510: Utopia Level 1 Interface Controller

520a, 520b, 520c, 520d: byte-to-word converter

530a, 530b, 530c, 530d: word FIFO

540: multiplexer 560: round-robin address generator

550: Utopia Level 2 Interface Controller

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a signal timing diagram at the transmission of Utopia Level 1, FIG. 2 is a signal timing diagram at the reception of Utopia Level 1, and FIG. 3 is a diagram illustrating the structure of an ATM cell at Utopia Level 1.

In the utopia interface, data flow from the ATM layer to the physical layer is called transmission, and data flow from the physical layer to the ATM layer is called reception. All interface control signals are active high, and active low is indicated by a '*' after the signal. In the utopia interface, transmission and synchronization are divided into transmission and synchronization at the octet level and transmission and synchronization at the cell level.

At the octet level, data transmission uses independent transmission synchronization clocks and reception synchronization clocks, respectively, and the physical layer device receives the transmission synchronization clock TxClk and the reception synchronization clock RxClk from the ATM layer device. Data transmission at the cell level establishes cell synchronization using a Start Of Cell (SOC) signal, which is asserted only at the first byte of an ATM cell. ')do.

Rate matching (rate matching) in the utopia level 1 is to solve the difference in the transmission rate between the physical layer and ATM layer, the physical layer device uses a first-in first-out buffer (FIFO) for rate matching. As such, a flow control signal is required to control the transmission rates of the ATM layer and the physical layer using the FIFO. For the flow control, the ATM layer asserts / deasserts the TxEnab signal while transmitting, and the physical layer asserts the TxFull * / TxClav signal. Assert / deassert. Upon reception, the physical layer asserts / deasserts the RxEmpty * / RxClav signal to control the data rate. At this time, the TxFull * signal and the RxEmpty * signal are flow control signals during octet level transmission, and the TxClav signal and RxClav signal are transmitted at cell level transmission. This is a flow control signal. At this time, the transmission pool (TxFull *) signal is asserted when the physical buffer overflows when 4 or more bytes are written. When the sellable signal is asserted, it indicates that there is sufficient space in the physical layer FIFO.

When the enable (Tx / Rx Enab) signal and the data flow are in the same direction (i.e., when transmitting), the data is transmitted in the same cycle as the enable signal, and when the enable signal and the data flow are in different directions, the data is the enable signal. Is transmitted in the next cycle.

The signals used for the transmission interface in the utopia level 1 interface are "TxData [7: 0]", "TxSoc", "TxEnb *", "TxFull * / TxClav", and "TxClk". "TxData [7: 0]" is 8 bits wide as the transmission data, and "TxSoc" is asserted in the first byte of the transmission cell by the ATM layer as the transmission cell start signal. "TxEnb *" is a transmit enable signal and is asserted upon cell data transmission in the ATM layer. "TxFull *" is asserted in the physical layer if only 4 bytes of data can be written in an octet-level transmission, and "TxClav" is asserted in the physical layer when it can accommodate a complete cell in a cell-level transmission. do. And "TxClk" is a transmission clock supplied from the ATM layer to the physical layer for data transmission and signal synchronization.

Timing in transmission by these signals is as shown in FIG.

1, the transmission interface is controlled by the ATM layer. The ATM layer supplies the transmit clock TxClk to the physical layer, thereby enabling the physical layer to use a rate matching buffer, i.e., a FIFO.

The data flow in the transmission interface is in the same direction as the transmit enable signal TxEnb *. The ATM layer transmission block generates and samples signals and data at the rising edge of the transmission clock TxClk. The physical layer informs the ATM layer that it is ready to receive a cell by asserting a TxFull * / TxClav signal, and the ATM layer asserts a transmit enable signal (TxEnb *) when the transmit cell available signal (TxClav) is high. That is, it is 'low' and at the same time drives the transmission data (TxData) on the data bus.

Looking at the handshake during octet-level transmission, we see the transmission window from when the TxFull * signal is asserted (i.e., low) until the TxFull * is deasserted (i.e., high) and then 4 bytes of data are written. do. The transmit enable signal TxEnb * can be asserted or deasserted only within this transmission window.

Looking at the handshake during cell level transmission, the physical layer must have the capacity to accommodate the transmission of a complete cell. In order to prevent the physical layer from overflowing, when the physical layer cannot accommodate the next cell, the physical layer should de-assert (ie, low) the transmit cell available signal TxClav 4 cycles before the current cell is finished.

Therefore, referring to FIG. 1, after TxClav is asserted high, TxEnb * is asserted low to start transmitting 53 bytes of ATM cells. At this time, when H1, the first byte of the cell, is transmitted, TxSoc becomes high, followed by H2, H3, H4, H5, P1, ..., P44, P45, P46, P47, and P48. When the physical layer cannot accept the next cell to be transmitted, TxClav goes low four clocks before the transmission of the current cell ends.

The signals used for the reception interface in the utopia interface are "RxData [7: 0]", "RxSoc", "RxEnb *", "RxEmpty * / RxClav", and "RxClk". "RxData [7: 0]" is 8 bits wide as received data, and "RxSoc" is asserted in the first byte of the receiving cell by the physical layer as the receiving cell start signal. "RxEnb *" is an enable signal and is asserted upon cell data transmission in the ATM layer. "RxEmpty *" is asserted by the physical layer when there is no data to transmit to the ATM layer in octet level transmissions, and "RxClav" is asserted by the physical layer when there is one complete cell to transmit in the cell level transmission. And "RxClk" is a reception clock supplied by the ATM layer to the physical layer in order to synchronize the physical layer to transmit data and sample a signal.

Timing upon reception by these signals is as shown in FIG. The receiving interface is controlled by the ATM layer. The ATM layer supplies the receive clock RxClk to the physical layer, thereby enabling the physical layer to use a rate matching buffer, i.e., a FIFO.

The flow of data in the receiving interface is in the opposite direction to the enable signal RxEnb. The ATM layer receiving block generates and samples signals and data at the rising edge of the reception clock RxClk. The physical layer informs the ATM layer that it is ready to send a cell by asserting an RxFull * / RxClav signal, and the ATM layer sets the receive enable signal RxEnb * to low when the receive cell available signal RxClav is high. The receive data (RxData) is read by asserting.

Looking at the handshake during octet level transmission, the physical layer informs the ATM layer that there is data to be sent to the ATM layer by deasserting the RxEmpty * signal, and the ATM layer accepts the data by asserting the RxEnb * signal. Send it.

Looking at the handshake during cell-level transmission, the physical layer asserts that there is one complete cell to transmit to the ATM layer by asserting the receive cell available signal (RxClav), and if there is no cell to transmit, the receive cell available signal (RxClav) Deassert. The ATM layer transmits information to accept data by asserting the receive enable signal RxEnb * when the receive cell available signal RxClav is asserted.

On the other hand, in the Utopia Level 1 interface, the ATM cell structure is divided into a 5-byte header (H: Header) section and a 48-byte user information section, as shown in FIG. 3, and the 5-byte header corresponds to the user network interface. It is divided into a header structure in the (UNI: User Network Interface) and a header structure in the network node interface (NNI: Network Node Interface), and the header structure in the user network interface (UNI) is a general flow of 4 bits in the first byte. It consists of Generic Flow Control (GFC) and 4-bit Virtual Path Identifier (VPI), and the second byte is 4-bit Virtual Path Identifier (VPI) and 4-bit Virtual Channel Identifier ( VCI (Virtual Channel Identifier), and the third byte is composed of 8 bits of virtual channel identification number (VCI), and the fourth byte is 4 bits of virtual channel identification number (VCI) and 3 bits of payload type ( PT: Payload Type) and 1-bit Cell Loss Priority (CLP) ), And the fifth byte consists of 8-bit header error control (HEC).

FIG. 4 is a diagram for describing a utopia level 2 interface. (A) shows that a plurality of physical layers can be connected to one ATM layer in utopia level 2. FIG. A diagram showing the structure of an ATM cell.

Utopia Level 2 interfaces basically follow the same conventions as Utopia Level 1 interfaces, but first, they can be speeded up from 33 MHz to 50 MHz, and second, they can scale to 16-bit parallel data paths when operating at 622 Mbps at 50 MHz. It is defined to enable multi-physical layer operations. That is, in the utopia level 2 interface, as shown in FIG. 4A, a plurality of physical layers 42a to 42n may be connected to one ATM layer 44.

"RxAdd [4: 0]" is added when receiving on this Utopia Level 2 interface, and "RxAdd [4: 0]" extracts VPI / VCI from RxData [15: 0] to determine the corresponding routing port. Create an address for the routing port. In transmission, "TxAdd [4: 0]" is added, and "TxAdd [4: 0]" generates an address of a port to be received in n transmission ports.

And the structure of the ATM cell in the Utopia Level 1 interface is composed of 8 bits x 53 as shown in FIG. 3, but in the Utopia Level 2 interface, the ATM cell is 16 bits x 27 as shown in (b) of FIG. It is composed. Referring to FIG. 4B, Header1 and Header2 are located in the first word of the cell, Heade3 and Header4 are located in the second word, and UDF1 and UDF2 are located in the third word. Subsequently, the payloads Payload 1 to 48 are located from the fourth word to the 27th word.

FIG. 5 is a block diagram showing an apparatus for converting utopia level 1 to utopia level 2 according to the present invention, FIG. 6 is a detailed signal connection diagram of the multiplexer shown in FIG. 5, and FIG. 7 is shown in FIG. Is a timing diagram of a utopia level 2 signal of a converted inverter. In FIG. 5, four Utopia Level 1 interface devices are connected to one Utopia Level 2 interface device. In an embodiment of the present invention, the Utopia Level 1 interface device is a SAR chipset including an ATM layer and the Utopia Level 2 interface device is a high-speed device. Physical layer chipsets. Therefore, FIG. 5 shows a configuration at the time of transmission, that is, transmission from the ATM layer to the physical layer.

The apparatus 500 for converting a utopia level 1 interface into a utopia level 2 interface according to the present invention provides a device 502a to 502d for providing a utopia level 1 interface, and a utopia level 2 interface, as shown in FIG. Located between the devices 504 to convert the utopia level 1 interface into a utopia level 2 interface.

Referring to FIG. 5, the utopia level converter 500 includes a utopia level 1 interface controller 510, a byte-to-word converter (520a to 520d), a word FIFO (530a to 530d), and a multiplexer (MUX). : 540, a utopia level 2 interface controller 550, and a round robin address generator 560. The multiplexer 540 and the utopia level 2 interface controller 550 are connected as shown in FIG. 6.

As described above, since the Utopia Level 1 interface carries data in bytes and the Utopia Level 2 interface carries data in words, four byte-word converters 520a through 520d provide four Utopia Level 1 devices 502a through. The byte unit data input from 502d) is converted into word units. The four word FIFOs 530a to 530d store the cell data output by the byte-word converters 520a to 520d, and output them to the multiplexer 540.

Utopia Level 1 interface controller 510 receives respective TxEnb * signals from four Utopia Level 1 interface devices 502a through 502d and provides respective TxClav signals. The first byte-to-word converter 520a receives the byte-by-byte transmission data TaD [7..0] from the first utopia level 1 interface device 502a and converts it into a word to convert the first word FIFO (FIFO1: 530a). ), And the first word FIFO 530a outputs the transmission data TaD [15..0] in word units to the multiplexer 540. Similarly, the second to fourth byte-word converters 520b to 520d may transmit the transmission data TbD [7..0], TcD [7..0], and TdD [7..0] to the second to fourth. It receives the input from the devices 502b to 502d and outputs it to the second to fourth word FIFOs 530b to 530d, and the second to fourth word FIFOs 530b to 530d are transmission data TbD [15..0 in word units. ], TcD [15..0], TdD [15..0]) are output to the multiplexer 540, respectively.

The utopia level 2 interface controller 550 provides one TxEnb * signal to the utopia level 2 interface device 504, receives one TxClav or TxFull * signal from the device 504, and receives a Utopia level 1 interface controller ( 510 is coupled to generate an appropriate control timing signal.

The round robin address generator 560 outputs four word FIFOs input to the multiplexer 540 (TaD [15..0], TbD [15..0], TcD [15..0], TdD [). 15..0]) select one of the transmission addresses (Txadd [2..0]) for multiplexing and provide the multiplexer 540, and the multiplexer 540 outputs the selected word FIFO. Is transmitted to the utopia level 2 interface device (504).

At this time, when the signals of the multiplexer 540 and the utopia level 2 interface controller 550 are examined in detail, as shown in FIG. 6, the utopia level 2 interface controller 550 transmits from the four word FIFOs 530a to 530d. Receives a cell enable signal (TaClav, TbClav, TcClav, TdClav) and provides a transmit enable signal (TxEnb *) to the Utopia Level 2 interface device, and transmits a TxClav signal from the Utopia Level 2 interface device. Input signal (TxAddr [2..0]) from the round robin address generator 560 and four read enable signals (TaRden, TbRden, TcRden, TdRden) to receive four word FIFOs (530a to 530d). To provide. The utopia level 1 interface controller 510 receives an Empty * signal from four word FIFOs, generates four transmit cell assignable signals, and provides them to the utopia level 1 interface device.

The multiplexer 540 according to the address Txadd [2..0] provided by the round robin address generator 560 by the same control signal as the transmit enable signal TxEnb * to the utopia Level 2 interface device. Output the selected transmission data to the Utopia Level 2 interface device. In the embodiment of the present invention, the transmission cell start signal TxSoc can be transmitted on the same path as the data bus.

As such, the utopia level 1 interface controller 510 provides control signals for interfacing with the four device ports and the byte-word converters 520a through 520d in the utopia level 1 direction, and the byte-word converters 520a through 520d At the upper ATM layer, it receives an 8-bit wide 53-byte ATM cell at level 1 and converts it into a 16-bit wide 27-word ATM cell. The word FIFOs 530a through 530d receive and store 27 words of 16-bit wide ATM cells in the byte-to-word converters 520a through 520d, and make it possible to wait for multiplexing.

The round robin address generator 560 repeatedly generates the addresses of the four input ports at the timing according to the Utopia Level 2 standard, and the multiplexer 540 receives the port addresses generated by the round robin address generator 560. The multiplexing port is multiplexed in the level 2 direction.

As shown in FIG. 1, the timing signal connected between the converter and the utopia level 2 device by converting the utopia level 1 to the utopia level 2 is a transmission clock TxClk, a transmission cell available signal TxClav, The transmit enable signal TxEnb *, the transmit data TxData, and the transmit cell start signal TxSOC.

Fig. 7 is a timing diagram of utopia level 2 transmission, which is applied to an internal signal of a utopia level 2 converter.

As described above, in the present invention, when the physical layer and the ATM layer support different levels of utopia interfaces, both levels may be converted to each other to easily interface with each other. That is, if the physical layer is Utopia level 2, the ATM layer is Utopia level 1, or the physical layer is Utopia level 1, and the ATM layer is Utopia level 2, Utopia level 1 is converted to level 2 to easily match the devices of level 1 and level 2. can do.

Claims (3)

An ATM apparatus for matching a device providing n Utopia Level 1 interfaces with a device supporting one Utopia Level 2 interface, N byte-to-word converters 520a to 520d which receive byte data from the utopia Level 1 interface device and convert them into word units; N word FIFOs 530a to 530d for receiving and storing word units of data from the byte-word converter; A round robin address generator 560 for generating n identifiable addresses in a round robin manner; A multiplexer (540) for selecting and multiplexing one of the outputs of the word FIFOs according to an address generated by the round robin address generator; Utopia Level 1 which receives a TxEnb * signal for a Utopia Level 1 type handshake from the Utopia Level 1 interface device and provides a TxClav signal to the Utopia Level 1 interface device, respectively. Interface controller 510; Receives a transmit cell enable (TxClav) signal for a utopia level 2 type handshake from a utopia level 2 interface device, receives a transmit address (TxAddr) from the round robin address generator 560, and receives the utopia level 2 interface. Utopia level 1 in an ATM communication method comprising a Utopia level 2 interface controller 550 for providing a transmit enable (TxEnb *) signal to a device and providing a control signal for enabling the multiplexer. Device that converts to Utopia Level 2. 2. The Utopia Level 1 interface device of claim 1, wherein the Utopia Level 1 interface device is implemented in a SAR layer chipset including an ATM layer, and the Utopia Level 2 interface device is implemented in a physical layer chipset, thus providing four 155 Mbps SAR layer devices in one 622 Mbps. An apparatus for converting utopia level 1 to utopia level 2 in an ATM communication method, which can be transmitted through a physical layer device. The apparatus for converting utopia level 1 to utopia level 2 according to claim 1, wherein the transmission cell start signal is transmitted through the same path as the data bus. Device.

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