KR100265839B1 - Metal wiring formation method of semiconductor device - Google Patents
Metal wiring formation method of semiconductor device Download PDFInfo
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- KR100265839B1 KR100265839B1 KR1019930020198A KR930020198A KR100265839B1 KR 100265839 B1 KR100265839 B1 KR 100265839B1 KR 1019930020198 A KR1019930020198 A KR 1019930020198A KR 930020198 A KR930020198 A KR 930020198A KR 100265839 B1 KR100265839 B1 KR 100265839B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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Abstract
Description
제 1 도는 종래 방법에 따른 금속배선 형성 후 스텝커버리지 상태를 보이는 단면도,1 is a cross-sectional view showing a step coverage after forming a metal wiring according to the conventional method,
제 2 도는 본 발명의 일실시예에 따른 금속배선 형성 공정 단면도.2 is a cross-sectional view of a metallization process according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 산화막1: silicon substrate 2: oxide film
3, 6 : 티타늄막 4 : 티타늄실리사이드막3, 6: titanium film 4: titanium silicide film
5 : 다결정실리콘막 7 : 티타늄나이트라이드막5: polycrystalline silicon film 7: titanium nitride film
8 : 배선용 금속막8: metal film for wiring
본 발명은 반도체 소자의 제조 공정 중 금속배선 형성 방법에 관한 것으로, 특히 티타늄-실리사이드 및 다결정실리콘을 이용하여 스텝커버리지 특성 및 배선의 특성을 향상시킬 수 있는 반도체 소자의 금속배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device manufacturing process, and more particularly, to a method for forming metal wirings for semiconductor devices capable of improving step coverage characteristics and wiring characteristics using titanium-silicide and polycrystalline silicon.
반도체 소자의 금속배선 형성을 위해 적용되는 금속막 증착 공정은 스퍼터링에 의한 방법이 일반적이다. 그러나 상기 스퍼터링에 의한 금속막 증착 방법은 여러 장점에도 불구하고 항상 따르는 문제가 스탭커버리지 특성 약화이다.The metal film deposition process applied for forming the metal wiring of the semiconductor device is generally a method by sputtering. However, in spite of various advantages of the metal film deposition method by sputtering, a problem that is always followed is a weakening of step coverage characteristics.
특히 소자가 고집적화되면서 디자인 룰의 감소로 금속배선층 콘택홀의 크기 감소는 필연적이고, 이에 따른 단차비(Aspect Ratio)의 증가는 금속배선층의 콘택홀 매립시 많은 어려움을 야기시키고, 또한 높은 단차비로 인한 금속배선층의 스텝커버리지(Step Coverage)의 열화는 반도체 소자의 신뢰도 저하 및 수율감소의 요인으로 작용하므로 고도의 공정 기술을 요한다.In particular, as the device is highly integrated, it is inevitable to reduce the size of the metallization layer contact hole due to the reduction of design rules. Accordingly, the increase of the aspect ratio causes many difficulties in filling the contact hole of the metallization layer, and also the metal due to the high leveling ratio. The deterioration of the step coverage of the wiring layer requires a high level of processing technology because it acts as a factor of lowering the reliability and yield of the semiconductor device.
종래의 금속배선 형성 방법은 다음과 같은 순서를 따른다.The conventional metal wiring forming method is as follows.
먼저 콘택홀을 형성한 다음 장벽금속막을 증착하고 열처리한 후 금속막을 증착하는 공정 수순을 따른다.First, a contact hole is formed, and then a barrier metal film is deposited and heat treated, followed by a process of depositing a metal film.
첨부된 도면 제1도는 상기 종래의 공정 방법에 따라 형성된 금속배선의 단면도로, 도면부호 1은 실리콘 기판, 2는 산화막, 8은 금속막을 각각 나타낸다.1 is a cross-sectional view of a metal wiring formed according to the conventional process method, wherein 1 is a silicon substrate, 2 is an oxide film, and 8 is a metal film, respectively.
도면에서 콘택홀 저면의 스텝커버리지 특성이 극도로 취약함을 알 수 있다.In the figure, it can be seen that the step coverage characteristic of the bottom of the contact hole is extremely weak.
상기와 같은 문제점을 해결하기 위한 본 발명은 미세한 패턴의 금속배선 형성시 배선의 스텝커버리지 특성을 향상시킬 수 있는 반도체 소자의 금속배선 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of improving step coverage characteristics of wiring when forming a fine pattern of metal wiring.
상기 목적을 달성하기 위한 본 발명은, 그 저면에 실리콘 기판을 노출시키는 콘택홀 형성이 완료된 구조 상에 제1 금속막을 증착하는 제1 단계; 열처리를 실시하여 상기 실리콘 기판과 접한 부분의 상기 제1 금속막을 실리사이드화하여 실리사이드막을 형성하는 제2 단계; 상기 실리사이드막으로 변하지 않고 잔류하는 상기 제1 금속막을 식각으로 제거하는 제3 단계; 상기 제3 단계가 완료된 전체 구조상에 다결정실리콘막을 증착하고 건식식각을 실시하여, 상기 콘택홀 저면의 모서리를 덮는 다결정실리콘막 스페이서를 형성하는 제4 단계; 상기 제4 단계가 완료된 전체 구조 상에 제2 금속막 및 장벽금속막을 차례로 증착하는 제5 단계; 열처리를 실시하여 상기 제2 금속막 및 상기 다결정실리콘막 스페이서를 반응시켜 실리사이드화하는 제6 단계; 및 상기 제6 단계가 완료된 전체 구조 상에 배선용 금속막을 형성하는 제7 단계를 포함하는 반도체 소자의 금속배선 형성 방법을 제공한다.The present invention for achieving the above object, the first step of depositing a first metal film on the structure of the contact hole formation is completed to expose the silicon substrate on the bottom surface; Performing a heat treatment to silicide the first metal film in a portion in contact with the silicon substrate to form a silicide film; A third step of etching the first metal film remaining unchanged into the silicide film; Depositing a polysilicon film over the entire structure of the third step and performing dry etching to form a polysilicon film spacer covering an edge of the bottom of the contact hole; A fifth step of sequentially depositing a second metal film and a barrier metal film on the entire structure of the fourth step; A sixth step of performing a heat treatment to react and silicide the second metal film and the polysilicon film spacer; And a seventh step of forming a wiring metal film on the entire structure in which the sixth step is completed.
본 발명은 스텝커버리지 특성이 취약한 콘택홀 저면 모서리 부분을 보강해주어 전반적으로 스텝커버리지 특성이 향상되도록 한 기술이다. 즉, 일반적으로 콘택홀 형성 후 뒤따르는 장벽금속막 증착전에, 티타늄-실리사이드막과 같은 실리사이드 형성공정과 다결정실리콘막 증착 및 식각공정을 추가하여 콘택홀 저면 모서리 부분의 경사를 완만하게 만들어 이후의 장벽금속막과 배선용 금속막 증착공정에서의 스텝커버리지 특성을 개선하는 기술이다.The present invention is to improve the overall step coverage characteristics by reinforcing the bottom edge of the contact hole that is weak in step coverage characteristics. That is, in general, a silicide forming process such as a titanium-silicide layer and a polysilicon film deposition and etching process are added before the deposition of the barrier metal film following the formation of the contact hole, thereby smoothing the slope of the bottom edge of the contact hole. It is a technique for improving the step coverage characteristics in the metal film and wiring metal film deposition process.
또한, 콘택홀 내의 다결정실리콘은 장벽금속층 희생금속막과 반응하여 태선 금속의 두께를 증가시키는 효과로도 스텝커버리지 개선에 기여하게 된다. 한편 다결정실리콘에 의해 완만하게 된 콘택홀 저면 모서리의 경사는 장벽금속막 증착시 확산장벽층인 금속막이 안정한 구조로 증착되게 하여 콘택 누설전류 특성의 개선도 아울러 꾀한 기술이다.In addition, the polysilicon in the contact hole contributes to the improvement of step coverage by the effect of increasing the thickness of the tie metal in response to the barrier metal layer sacrificial metal film. On the other hand, the slope of the bottom edge of the contact hole smoothed by polysilicon is designed to improve the contact leakage current characteristics by allowing the metal film, which is a diffusion barrier layer, to be deposited in a stable structure when the barrier metal film is deposited.
이하, 첨부된 도면 제2a도 내지 제2h도를 참조하여 본 발명을 상술한다.Hereinafter, the present invention will be described in detail with reference to the attached drawings 2A to 2H.
먼저 제2a도는 실리콘 기판(1) 상에 산화막(2)을 형성하고 마스크 공정을 거쳐 상기 산화막(2)을 소정부위 식각하여 콘택홀을 형성한 다음 전체구조 상부에 금속막의 예로서 제1 티타늄막(3)을 증착한 상태의 단면도이다.First, FIG. 2A shows an oxide film 2 formed on the silicon substrate 1 and a contact hole is formed by etching the oxide film 2 through a mask process to form a contact hole. It is sectional drawing of the state which deposited (3).
제2b도는 상기 제1 티타늄막(3)을 열처리하여 상기 실리콘 기판(1)과 접해있는 부분의 제1 티타늄막을 실리사이드화하여 제1 티타늄실리사이드막(4)으로 변화시킨 상태를 보이는 단면도이다.FIG. 2B is a cross-sectional view showing a state where the first titanium film 3 is heat-treated to silicide the first titanium film in contact with the silicon substrate 1 to change to the first titanium silicide film 4.
제2c도는 습식식각 공정으로 상기 열처리 공정시 실리사이드화되지 못한 제1 티타늄막(3)을 제거한 상태의 단면도이다.FIG. 2C is a cross-sectional view of the first titanium film 3 which is not silicided during the heat treatment process by the wet etching process.
제2d도는 전체 구조 상부에 스텝커버리지 특성이 우수한 다결정실리콘막(5)을 형성한 상태의 단면도이다. 이때, 증착되는 다결정실리콘막의 두께는 콘택홀의 모양과 크기에 따라 적절히 조절한다.FIG. 2D is a cross-sectional view of the polysilicon film 5 having excellent step coverage characteristics formed over the entire structure. At this time, the thickness of the polysilicon film deposited is appropriately adjusted according to the shape and size of the contact hole.
제2e도는 상기 다결정실리콘막(5)을 건식식각하여 상기 다결정실리콘막(5)을 콘택홀 저면의 모서리를 덮는 모서리를 덮는 스페이서 형태로 잔류시킨 것을 보이는 단면도이다. 이와 같이 콘택홀 저면의 모서리를 덮는 스페이서 형태로 잔류하는 다결정실리콘막(5)은 콘택홀 저면 모서리 부분의 경사를 완만하게 하여 이후의 스퍼터링시 스텝커버리지 특성 열화의 원인이 되는 그림자 효과(shadow effect)를 감소시켜 이후의 장벽금속막과 배선용 금속막 증착 공정에서 스텝커버리지 특성을 향상시키게 된다. 또한 다결정실리콘막(5)을 건식식각할 때 실리콘 기판(2)이 과도식각될 수 있는데, 실리콘 기판(1) 상에 이미 형성되어 있는 제1 티타늄실리사이드막(4)이 과도식각에 따른 실리콘 기판(1)의 손상을 방지한다.FIG. 2E is a cross-sectional view showing that the polysilicon film 5 is dry etched to leave the polysilicon film 5 in the form of a spacer covering an edge of the bottom of the contact hole. As such, the polysilicon film 5 remaining in the form of a spacer covering the edges of the bottom of the contact hole smoothes the slope of the bottom edge of the bottom of the contact hole, thereby causing a shadow effect that causes deterioration of step coverage characteristics during subsequent sputtering. The step coverage characteristics can be improved in the subsequent barrier metal film and wiring metal film deposition process. In addition, when the polysilicon film 5 is dry etched, the silicon substrate 2 may be over-etched. The first titanium silicide film 4 already formed on the silicon substrate 1 may be over-etched. (1) to prevent damage.
제2f도는 전체 구조 상부에 금속막의 예로서 제2 티타늄막(6)을 형성하고, 제2 티타늄막(6) 상에 장벽금속막인 티타늄나이트라이드막(7)을 차례로 형성한 상태의 단면도이다.FIG. 2F is a cross-sectional view of a state in which a second titanium film 6 is formed as an example of a metal film on the entire structure, and a titanium nitride film 7, which is a barrier metal film, is sequentially formed on the second titanium film 6. .
제2g도는 열처리 공정으로 상기 제2 티타늄막(6)과 다결정 실리콘막을 반응시켜 실리사이드화시킨 상태의 단면도이다. 이때 제2 티타늄막(6) 일부의 티타늄실리사이드화로 인하여 티타늄실리사이드막(4)의 두께는 두배로 증가하게 되는데, 이 또한 콘택홀 저면 모서리 부분의 스텝커버리지 특성 향상에 일조하게 된다.FIG. 2G is a cross-sectional view of a state in which the second titanium film 6 and the polycrystalline silicon film are silicided by a heat treatment process. At this time, the thickness of the titanium silicide layer 4 is doubled due to the titanium silicide of a part of the second titanium layer 6, which also helps to improve the step coverage characteristics of the bottom edge of the contact hole.
제2h도는 전체 구조 상부에 알루미늄 등과 같은 배선용 금속막(8)을 형성한 상태의 단면도이다.2H is a cross-sectional view of the wiring metal film 8 such as aluminum formed on the entire structure.
상기와 같이 이루어지는 본 발명은 금속배선 형성 공정에서 콘택홀 저면 모서리 부분에서의 스텝커버리지 특성 열화를 방지하고, 확산장벽인 티타늄나이트라이드막을 안정한 구조로 형성함으로써 콘택누설전류 특성을 개선하여 반도체 소자의 제조수율을 높이고, 소자의 신뢰성을 향상시키는 효과를 얻을 수 있다.The present invention made as described above prevents deterioration of step coverage characteristics at the bottom edge of the contact hole in the metallization forming process, and improves the contact leakage current characteristics by forming a titanium nitride film as a diffusion barrier to manufacture a semiconductor device. The effect which raises a yield and improves the reliability of an element can be acquired.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.
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| KR1019930020198A KR100265839B1 (en) | 1993-09-28 | 1993-09-28 | Metal wiring formation method of semiconductor device |
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| KR1019930020198A KR100265839B1 (en) | 1993-09-28 | 1993-09-28 | Metal wiring formation method of semiconductor device |
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| KR100265839B1 true KR100265839B1 (en) | 2000-09-15 |
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| KR20030050846A (en) * | 2001-12-19 | 2003-06-25 | 주식회사 하이닉스반도체 | Method for forming metal line of semiconductor |
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| KR100468694B1 (en) * | 1997-10-13 | 2005-03-16 | 삼성전자주식회사 | Method for forming contact for semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20030050846A (en) * | 2001-12-19 | 2003-06-25 | 주식회사 하이닉스반도체 | Method for forming metal line of semiconductor |
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