KR100298457B1 - Duty cycle correction circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generator. The present invention relates to a duty cycle correction circuit suitable for a duty cycle having a stable 50% duty ratio by feeding an output clock back to a correction unit to prevent a constant current flowing through an enable transistor. A correction voltage for generating first and second correction voltages (Vcp, Vcn) by receiving a first CMOS inverter, a second CMOS inverter for inverting the output clock of the first CMOS inverter, and an output clock of the second CMOS inverter. A first compensator for selectively correcting a duty ratio for an output clock of the first CMOS inverter by receiving a feedback signal and a first correction voltage of the second CMOS inverter as a gate signal, respectively, of the second CMOS inverter And a second correction unit configured to receive a feedback signal and a second correction voltage as a gate signal to selectively correct a duty ratio for an output clock of the first CMOS inverter. It is characterized by loosening.

Description

Duty cycle correction circuit {DUTY CYCLE CORRECTION CIRCUIT}

The present invention relates to a clock generation circuit, and more particularly, to a duty cycle correction circuit suitable for a duty cycle having a duty ratio of 50% to operate in a stable correction range.

In general, phase locked loops (PLLs) and delay locked loops (DLLs) are used to eliminate on-chip clock buffering delays and improve I / O timing margins. If this is unnecessary, it is used instead of PLL.

In addition, the DLL can be implemented in an analog or digital manner. The analog method generally has better jitter characteristics, has a lower layout area and power consumption, while the digital method is simpler and easier to design. There is a difference that can be low.

The digital clock signal is a sequential generation of a pulse having a voltage value between the power supply voltage (Vdd) and the ground voltage (Vss), and has a width (W) and a period (T) of a pulse, and a ratio W / T represents a duty ratio and a clock. The signal can have two cases of rising and falling transitions.

On the other hand, the duty cycle of the digital clock is generally expressed as a percentage, and a duty cycle with the same high and low potion, that is, 50% duty ratio, is required.

Hereinafter, a conventional duty cycle correction circuit will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a conventional digital DLL, including phase-splitter, first and second delay chains 11a and 11b, end of cycle deterctor, EOCD, and counter / State control logic and selection logic, dual first multiplexer and duty cycle correction circuit 12a, blender circuit, second multiplexer and duty cycle correction circuit 12b, filter, phase detector ), And a duty cycle error detection unit.

Here, the conventional digital DLL uses the first and second delay chains 11a and 11b made of CMOS inverters. The delay chains 11a and 11b have a duty cycle correction because the duty ratio varies as the clock signal passes through the inverter stage. Circuits 12a and 12b are needed.

2 is a circuit diagram showing a conventional duty cycle correction circuit, comprising: a first CMOS inverter 21 for inverting an input clock, a second CMOS inverter 22 for inverting the output of the first CMOS inverter 21, The first correction voltage Vcp is applied to the gate terminal, the power supply voltage Vdd is supplied to the source terminal, and the PMOS 23 connected to the output terminal of the first CMOS inverter 21 is connected to the drain terminal, and the second terminal is connected to the gate terminal. Input the NMOS 24 and the output clock of the second CMOS inverter 22, the correction voltage Vcn is applied, the ground terminal is connected to the source terminal, and the output terminal of the first CMOS inverter 21 is connected to the drain terminal. And a correction voltage generator 25 that generates the first and second correction voltages.

The operation of the conventional duty cycle correction circuit configured as described above will be described with reference to FIGS. 3A to 3C.

As shown in FIG. 3A, when the duty ratio of the input clock clk_in is 50%, the first correction voltage becomes a value reaching Vdd and the second correction voltage Vcn is approximated to Vss so that the NMOS 24 and the PMOS 23 are approximated. ), The output clock maintains 50% duty ratio.

As shown in FIG. 3B, when the duty ratio of the input clock is 50% or less, since the second correction voltage rises at Vss and the first correction voltage maintains a value close to Vdd, the PMOS 23 is blocked and the NMOS 24 is blocked. Is turned on.

Subsequently, when the input clock transitions from high to low, the first CMOS inverter 21 attempts to shift the output from low to high, but since the NMOS 24 keeps the node X low, the rising transition delay period 31 It will be longer.

On the other hand, when the duty ratio of the input clock is 50% or more, since the first correction voltage drops at Vdd and the second correction voltage is close to Vss, the NMOS 24 is blocked and the PMOS 23 is turned on.

Subsequently, when the input clock transitions from low to high, the first CMOS inverter 21 attempts to shift the output from high to low, but since the PMOS 23 keeps the node X high, the falling delay delay section 32 It will be longer.

That is, due to the transistors having the rising transition section 31 and the falling transition section 32 of the node X turned on, the delay ratio of the output clock is corrected to 50%.

In this case, a constant current flows from the power supply voltage to the ground terminal due to the transistor that is always turned on, and the voltage generated by the constant current decreases the amplitude by ΔV of the output clock.

However, the conventional duty cycle correction circuit as described above has a problem in that a constant current flows continuously through the transistor turned on for every half period of the cycle when the duty ratio is 50%.

In addition, if the difference between the 50% duty cycle of the input clock is significantly different, the first correction voltage or the second correction voltage fluctuates so that the level of the node X is not constant, so the output clock operates unstable and the duty cycle correction range is not short.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a duty cycle correction circuit suitable for generating a stable duty cycle having a duty ratio of 50% by feeding an output clock back to the correction unit to prevent a constant current flowing through the transistor turned on. Its purpose is to.

1 is a block diagram showing a general digital DLL

2 is a circuit diagram showing a conventional duty cycle correction circuit.

3A to 3C are waveform diagrams showing the operation of FIG.

4 is a circuit diagram showing a duty cycle correction circuit according to the present invention.

5A to 5C are waveform diagrams showing the operation of FIG.

6 is a diagram illustrating a correction voltage range of FIG. 4.

* Description of the symbols for the main parts of the drawings *

30: first CMOS inverter 40: second CMOS inverter

50: correction voltage generator 60: first correction unit

70: second correction unit

A duty cycle correction circuit according to the present invention for achieving the above object includes a first CMOS inverter for inverting the input clock, a second CMOS inverter for inverting the output clock of the first CMOS inverter, and the second CMOS inverter. A duty ratio for the output clock of the first CMOS inverter by receiving a correction voltage generator for generating a first correction voltage and a second correction voltage by an output clock, a feedback signal of the second CMOS inverter, and a first correction voltage. A first compensator for selectively correcting the voltage and a second compensator for selectively correcting a duty ratio of an output clock of the first CMOS inverter by receiving a feedback signal and a second correction voltage of the second CMOS inverter; Characterized in that configured.

Hereinafter, a duty cycle correction circuit according to the present invention will be described with reference to the accompanying drawings.

4 is a circuit diagram illustrating a duty cycle correction circuit according to the present invention, and FIGS. 5A to 5B are waveform diagrams illustrating the operation of FIG. 4, and FIG. 6 is a diagram illustrating a range of the correction voltage of FIG. 4.

First, the duty cycle correction circuit according to the present invention includes a first CMOS inverter 30 for inverting the input clock CLK_IN and a second CMOS inverter 40 for inverting the output signal Y of the first CMOS inverter 30. ), A correction voltage generator 50 for generating a first correction voltage Vcp and a second correction voltage Vcn by the output clock CLK_OUT of the second CMOS inverter 40, and the second CMOS. A first corrector 60 which receives a feedback signal Z of the output clock of the inverter 40 and a first correction voltage and selectively corrects the duty ratio of the output clock of the first CMOS inverter 30; A second corrector configured to receive a feedback signal Z of the output clock of the second CMOS inverter 40 and a second correction voltage to selectively correct the duty ratio of the output clock of the first CMOS inverter 30 ( 70).

The first compensator 60 includes a first PMOS 61 having a drain terminal connected to an output terminal Y of the first CMOS inverter 30 and a first correction voltage input to a gate terminal, It consists of a second PMOS 62 which is connected to the drain terminal of the PMOS 61, the Vdd is supplied to the source terminal, and the output clock Z of the second CMOS inverter 40 is fed back to the gate terminal. do.

The second compensator 70 includes a first NMOS 71 having a drain terminal connected to an output terminal Y of the first CMOS inverter 30 and a second correction voltage input to a gate terminal, and the first NMOS 71 being connected to the gate terminal. The drain terminal is connected to the source terminal of the NMOS 71 and the source terminal is connected to the ground terminal, and the output clock C of the second CMOS inverter 40 is fed back to the gate terminal to the second NMOS 72. It is composed.

The operation of the duty cycle correction circuit according to the present invention configured as described above will be described with reference to FIGS. 5A to 5C and 6.

As shown in FIG. 5A, when the duty ratio of the input clock CLK_IN is 50%, the first correction voltage reaches Vdd-Vtp and the second correction voltage has a value close to Vtn. 1 NMOS 71 remains blocked to maintain a 50% duty ratio for output clock CLK_OUT.

Where Vtp is the threshold voltage of the first PMOS 61, Vtn is the threshold voltage of the first NMOS 71, and Vdd is the power supply voltage supplied to the source terminal of the first PMOS 61.

As shown in FIG. 5B, when the duty ratio of the input clock is 50% or less, since the first correction voltage rises by the duty ratio difference up to Vdd, the first PMOS 61 is blocked and the second correction voltage rises at Vtn, so that the first NMOS 71 is turned on.

Subsequently, when the input clock transitions from high to low, the first CMOS inverter 31 attempts to shift the clock from low to high, but the first NMOS 71 and the second NMOS 72 keep the node Y low. As a result, the rising transition delay section 51 becomes long.

The second CMOS inverter 32 then transitions the clock corrected at the node Y from high to low and feeds the output clock back to the gate terminal of the second NMOS 72 to block the second NMOS 72. Since the current path to the ground terminal is shorted, no constant current flows through the turned-on first NMOS 71.

Here, since the rising transition delay node 51 in the node Y becomes large, the high period of the output clock of the second CMOS inverter 40 is increased to compensate for the duty ratio of 50%, and the node Y is Vdd by the feedback signal of the output clock. It rises quickly until it prevents the transition section of the output clock from slowing down.

As shown in FIG. 5C, when the duty ratio of the input clock is 50% or more, the first PMOS 61 is turned on because the first correction voltage is lowered by the duty ratio difference from Vdd-Vtp and the second correction voltage is lowered to Vss. The first NMOS 71 is cut off.

Subsequently, when the input clock transitions from low to high, the first CMOS inverter 30 attempts to shift the clock from high to low, but the first PMOS 61 and the second PMOS 62 keep node Y high. Since the descending stream delay section 52 is long.

Subsequently, the second CMOS inverter 40 shifts the clock corrected at the node Y from low to high and feeds the output clock of the second CMOS inverter 40 back to the gate terminal of the second PMOS 62 to supply the second PMOS. Since 62 is blocked, no constant current flows through the turned-on first PMOS 61.

In this case, since the descending stream of the node Y increases in the delay period 52, the high period of the output clock of the second CMOS inverter 40 is increased to be corrected to a duty ratio of 50%, and the node Y is driven by the feedback signal of the second CMOS inverter. Quickly descends to Vss, thus preventing the transition section from slowing down.

As shown in FIG. 6, the first correction voltage has a value approximating Vdd-Vtp when the duty ratio is 50% and rises from Vdd-Vtp to Vdd when 50% or less, and the duty at Vdd-Vtp when 50% or more. Descend by a non-difference.

In addition, the second correction voltage has a value approximating Vtn when the duty ratio is 50%, increases by the duty ratio difference from Vtn when 50% or less, and drops from Vtn to Vss when 50% or more.

As described above, the duty cycle correction circuit according to the present invention can operate stably by widening the duty ratio correction range when the duty ratio is significantly different from 50%, and also feeds the output clock back to the turned-on transistor. By cutting off the constant current path, power consumption can be reduced.

Claims (3)

A first CMOS inverter for inverting the input clock; A second CMOS inverter for inverting the output clock of the first CMOS inverter; A correction voltage generator which receives an output clock of the second CMOS inverter and selectively generates a first correction voltage and a second correction voltage; A first compensator for receiving a feedback signal of the second CMOS inverter and the first correction voltage as a gate signal, and selectively correcting a duty ratio of an output clock of the first CMOS inverter; And a second correction unit configured to receive a feedback signal of the second CMOS inverter and the second correction voltage as a gate signal, and selectively correct a duty ratio for an output clock of the first CMOS inverter. Cycle correction circuit. The method of claim 1, The first corrector may include a first PMOS having a drain terminal connected to an output terminal of the first CMOS inverter and a first correction voltage input to a gate terminal; A duty cycle correction comprising a second PMOS having a drain terminal connected to a source terminal of the first PMOS, an external power source applied to the source terminal, and an output clock of the second CMOS inverter input to a gate terminal as a feedback signal. Circuit. The method of claim 1, The second corrector may include a first NMOS having a drain terminal connected to an output terminal of the first CMOS inverter and a second correction voltage input to a gate terminal; A duty cycle correction comprising a second NMOS having a drain terminal connected to a source terminal of the first NMOS, a source terminal connected to a ground terminal, and an output clock of the second CMOS inverter input to a gate terminal as a feedback signal. Circuit.