KR100305205B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR100305205B1 KR100305205B1 KR1019950020974A KR19950020974A KR100305205B1 KR 100305205 B1 KR100305205 B1 KR 100305205B1 KR 1019950020974 A KR1019950020974 A KR 1019950020974A KR 19950020974 A KR19950020974 A KR 19950020974A KR 100305205 B1 KR100305205 B1 KR 100305205B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
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Abstract
Description
제1(a)도 내지 제(g)도는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도.1 (a) to (g) are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘기판 2 : N 웰1: silicon substrate 2: N well
3 : P 웰 4 : 베리어층3: P well 4: barrier layer
5A : 단결정실리콘층 5B : 제1다결정실리콘층5A: single crystal silicon layer 5B: first polycrystalline silicon layer
6 : 필드산화막 7 : 게이트산화막6: field oxide film 7: gate oxide film
8 : 제2다결정실리콘층 8A : 게이트전극8: second polysilicon layer 8A: gate electrode
9 : LDD 영역 10 : 산화막 스페이서9: LDD region 10: oxide film spacer
11 : 접합영역 12 : 절연막11 junction region 12 insulating film
12A : TEOS 12B : BPSG12A: TEOS 12B: BPSG
13 : 감광막 14 : 콘택홀13: photosensitive film 14: contact hole
15 : 금속배선15: metal wiring
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 접합영역의 하부에 베리어(Barrier)층을 형성하고, 상기 접합영역이 관통되도록 콘택홀을 형성하므로써 소자의 전기적특성이 향상될 수 있도록 한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a barrier layer is formed below a junction region and a contact hole is formed to penetrate the junction region, thereby improving the electrical characteristics of the device. It relates to a manufacturing method of.
일반적으로 반도체 소자가 고집적화됨에 따라 트랜지스터가 차지하는 단위면적도 감소된다. 이에 따라 접합영역의 깊이를 얕게 형성해야 하는데, 쇼트 채널 효과(Short Channe1 Effect)의 감소라는 측면에서 얕은 접합깊이의 구현은 필수적이다. 접합 깊이는 이온주입 에너지에 의해 결정된다. 그런데 종래의 방법으로는 접합영역에 불순물이온이 불균일하게 주입되기 때문에 전류가 흐를 수 있는 부분의 면적이 작아 소자의 전기적특성이 저하된다. 그리고 접합영역과 상부에 형성되는 금속층과의 접속을 위한 콘택홀 형성시 접합영역과 금속층의 완전한 접촉을 위해 접합영역의 표면을 과도식각(Over Etch)하기 때문에 실리콘기판의 표면이 손상되는 문제가 발생되며, 접합영역과 접촉되는 부분의 금속층에서 게이트전극과 근접하는 부분에 전류밀도가 집중되어 전류 집증 저항 성분이 존재하게 된다. 또한 접합영역에서 기생 정전용량(Parasitic Capacitance)이 발생되어 소자의 동작속도를 저하시킨다.In general, as semiconductor devices are highly integrated, the unit area occupied by transistors is also reduced. Accordingly, the depth of the junction region should be formed shallowly, and the implementation of the shallow junction depth is essential in terms of reducing the short channel effect (Short Channe1 Effect). The junction depth is determined by the ion implantation energy. However, in the conventional method, since the impurity ions are unevenly injected into the junction region, the area of the portion through which current can flow is reduced, and the electrical characteristics of the device are degraded. In addition, when forming the contact hole for connecting the junction region and the metal layer formed on the upper part, the surface of the silicon substrate is damaged due to over etching of the junction region for complete contact between the junction region and the metal layer. The current density is concentrated in a portion close to the gate electrode in the metal layer in contact with the junction region, and thus a current collecting resistance component is present. In addition, parasitic capacitance is generated in the junction region, which reduces the operation speed of the device.
따라서 본 발명은 접합영역의 하부에 베리어층을 형성하고, 상기 접합영역이 관통되도록 콘택홀을 형성하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 제조방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of solving the above-mentioned disadvantages by forming a barrier layer under the junction region and forming a contact hole to allow the junction region to penetrate.
상기한 목적을 달성하기 위한 본 발명은 실리콘기판상에 N웰 및 P웰을 형성한 후 전체 상부면에 베리어층을 형성하고 채널이 형성될 부분의 상기 실리콘기판이 노출되도록 상기 베리어층을 패터닝하는 단계와, 상기 단계로부터 상기 실리콘기판의 표면을 세정시킨 후 노출된 실리콘기판상에는 단결정 실리콘층이 형성되고, 상기 베리어층상에는 제 1 다결정 실리콘층이 형성되도록 에피택셜 성장을 실시하는 단계와, 상기 단계로부터 상기 N웰 및 P웰이 접하는 부분의 필드영역에 필드산화막을 형성하는 동시에 상기 N웰 및 P웰에 도핑된 불순물이온이 외부확산되어 상기 단결정 실리콘층에 채널 도핑이 이루어지도록 LOCOS 공정을 실시하는 단계와, 상기 단계로부터 전체 상부면에 게이트산화막 및 제 2 다결정 실리콘층을 순차적으로 형성한 후 게이트전극용 마스크를 이용한 사진 및 식각공정으로 상기 제 2다결정 실리콘층 및 게이트산화막을 순차적으로 페터닝하여 상기 단결정 실리콘층 상부에 게이트전극을 형성하는 단계와, 상기 단계로부터 노출된 상기 제 1 다결정 실리콘층에 저농도의 불순물이온을 주입하여 LDD영역을 형성하는 단계와, 상기 단계로부터 상기 게이트전극의 양측벽에 산화막 스페이서를 형성한 후 노출된 상기 제 1 다결정 실리콘층에 고농도의 불순물이온을 주입하여 접합영역을 형성하는 단계와, 상기 단계로부터 전체 상부면에 절연막 및 감광막을 순차적으로 형성한 후 콘택 마스크를 이용한 사진 및 식각공정으로 상기 감광막을 패터닝하는 단계와, 상기 단계로부터 상기 패터닝된 감광막을 마스크로 이용하여 상기 절연층을 소정 깊이 습식 식각한 후 나머지 두께의 절연층 및 제 1 다결정 실리콘층을 순차적으로 건식식각하여 상기 베리어층이 노출되도록 콘택홀을 형성하는 단계와, 상기 단계로부터 상기 콘택홀이 매립되도록 전체 상부면에 금속층을 형성한 후 금속배선용 마스크를 이용한 사진 및 식각공정으로 상기 금속층을 패터닝하여 금속배선을 형성하는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is to form a barrier layer on the entire upper surface after forming the N well and P well on the silicon substrate and to pattern the barrier layer so that the silicon substrate of the portion where the channel is to be exposed Performing a step of epitaxial growth such that a single crystal silicon layer is formed on the exposed silicon substrate and a first polycrystalline silicon layer is formed on the barrier layer after cleaning the surface of the silicon substrate from the step; LOCOS process is performed to form a field oxide film in the field region of the portion where the N well and the P well are in contact with each other and to simultaneously diffuse the dopant ions doped into the N well and the P well so that the single crystal silicon layer is channel doped. And sequentially forming a gate oxide film and a second polycrystalline silicon layer on the entire upper surface from the step; Sequentially patterning the second polycrystalline silicon layer and the gate oxide layer by a photolithography and etching process using a mask for forming a gate electrode on the single crystal silicon layer, and exposing the first polycrystalline silicon layer exposed from the step. Forming an LDD region by implanting low concentration of impurity ions; forming an oxide spacer on both sidewalls of the gate electrode; And forming an insulating film and a photoresist film on the entire upper surface sequentially from the step, and then patterning the photoresist film using a photomask and an etching process using a contact mask, and using the patterned photoresist film as a mask from the step. Wet etching the insulation layer a predetermined depth and then insulation layer of the remaining thickness Forming a contact hole to expose the barrier layer by sequentially dry etching the first polycrystalline silicon layer; forming a metal layer on the entire upper surface of the contact hole to be filled from the step; The metal layer is patterned by an etching process to form a metal wiring.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제1(a) 내지 제1(g)도는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도로서,1 (a) to 1 (g) are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device according to the present invention.
제1(a)도는 실리콘기판(1)상에 N웰(2) 및 P웰(3)을 형성한 후 전체 상부면에 베리어층(4)으로서 산화막을 형성하고 채널이 형성될 부분의 상기 실리콘기판(1)이 노출되도록 상기 베리어층(4)을 패터닝한 상태의 단면도인데, 이때 상기 N웰(2) 및 P웰(3)에 주입된 불순물이온의 외부확산에 의해 후속공정에서 채널 도핑(Doping)이 이루어지기 때문에 상기 N웰(2) 및 P웰(3)에 도핑되는 불순물이온의 농도를 적절하게 조절해야 하며, 접합 정전용량을 고려하여 상기 베리어층(4)의 두께를 결정해야 한다.After forming the N well 2 and the P well 3 on the silicon substrate 1 in FIG. 1 (a), an oxide film is formed as the barrier layer 4 on the entire upper surface, and the silicon in the portion where the channel is to be formed. The barrier layer 4 is patterned so that the substrate 1 is exposed. In this case, channel doping is performed in a subsequent process by external diffusion of impurity ions implanted into the N well 2 and the P well 3. Because doping is performed, the concentration of impurity ions doped in the N well 2 and the P well 3 should be properly adjusted, and the thickness of the barrier layer 4 should be determined in consideration of the junction capacitance. .
제1(b)도는 상기 실리콘기판(1)의 표면을 세정시킨 후 에피택셜 성장(Epi taxial Growth)을 실시한 상태의 단면도로서, 노출된 실리콘기판(1)상에는 단결정 실리콘층(5A)이 형성되고, 상기 베리어층(4)상에는 제 1 다결정 실리콘층(5B)이 형성된다. 이때 성장된 상기 단결정 실리콘층(5A) 및 제 1 다결정 실리콘층(5B)에는 불순물이온을 도핑시키지 않아야 한다.FIG. 1 (b) is a cross-sectional view of epitaxial growth after cleaning the surface of the silicon substrate 1, wherein a single crystal silicon layer 5A is formed on the exposed silicon substrate 1; The first polycrystalline silicon layer 5B is formed on the barrier layer 4. At this time, the grown single crystal silicon layer 5A and the first polycrystalline silicon layer 5B should not be doped with impurity ions.
제1(c)도는 LOCOS(Local 0xidation of Silicon )공정을 이용하여 상기 N웰(2) 및 P웰(3)이 접하는 부분의 필드영역에 필드산화막(6)을 형성한 상태의 단면도인데, 상기 필드산화막(6)이 형성되는 동안에 상기 N웰(2) 및 P웰(3)에 도핑된 불순물이온의 외부확산으로 인해 상기 단결정 실리콘층 (5A)에는 채널 도핑이 이루어진다.FIG. 1C is a cross-sectional view of the field oxide film 6 being formed in the field region of the portion where the N well 2 and the P well 3 are in contact by using a LOCOS (Local 0xidation of Silicon) process. While the field oxide film 6 is formed, channel doping is performed on the single crystal silicon layer 5A due to the external diffusion of the impurity ions doped into the N well 2 and the P well 3.
제1(d)도는 전체 상부면에 게이트산화막(7) 및 제 2 다결정 실리콘층(8)을 순차적으로 형성한 후 게이트전극용 마스크를 이용한 사진 및 식각공정으로 상기 제 2 다결정 실리콘층(8) 및 게이트산화막(7)을 순차적으로 패터닝하여 상기 단결정 실리콘층(5A) 상부에 게이트전극(8A)을 형성한다. 이후 노출된 상기 제 1 다결정 실리콘층(5B)에 저농도의 불순물이온을 주입하여 LDD영역(9)을 형성한 상태의 단면도이다.In FIG. 1 (d), the gate oxide film 7 and the second polycrystalline silicon layer 8 are sequentially formed on the entire upper surface, and the second polycrystalline silicon layer 8 is formed by a photolithography and etching process using a mask for a gate electrode. And the gate oxide film 7 is sequentially patterned to form a gate electrode 8A on the single crystal silicon layer 5A. Afterwards, the LDD region 9 is formed by implanting low concentrations of impurity ions into the exposed first polycrystalline silicon layer 5B.
제1(e)도는 상기 게이트전극(8A)의 양측벽에 산화막 스페이서(10)를 형성한 후 노출된 상기 제 1 다결정 실리콘층(5B)에 고농도의 불순물이온을 주입하여 접합영역(11)을 형성한 상태의 단면도로서, 이때 상기 제 1다결정 실리콘층(5B)의 하부에는 베리어층(4)이 형성되어 있으므로 불순물이온을 충분하게 주입하여 균일한 도핑을 이룬다.FIG. 1 (e) shows that the junction region 11 is formed by implanting a high concentration of impurity ions into the exposed first polycrystalline silicon layer 5B after forming oxide spacers 10 on both sidewalls of the gate electrode 8A. In this state, the barrier layer 4 is formed under the first polycrystalline silicon layer 5B. Thus, the impurity ions are sufficiently injected to form a uniform doping.
제1(f)도는 전체 상부면에 TEOS(12A) 및 BPSG(12B)를 순차적으로 증착하여 절연막(12)을 형성한 후 전체 상부면에 감광막(13)을 도포한다. 콘택 마스크를 이용한 사진 및 식각공정으로 상기 감광막(13)을 패터닝하고, 상기 패터닝된 감광막(13)을 마스크로 이용하여 상기 절연층(12)을 소정 깊이 습식 식각한다. 이후 나머지 두께의 절연층(12) 및 제 1 다결정 실리콘층(5B)을 순차적으로 건식 식각하여 상기 베리어층(4)이 노출되도록 콘택홀(14)을 형성한 상태의 단면도인데, 상기 콘택홀(14)은 상기 제 1 다결정 실리콘층(5B)에 형성된 접합영역(11)을 관통하도록 형성되며, 이때 상기 베리어층(4)은 식각 정지(Etch Stop)층 및 실리콘기판(1) 손상 방지층으로 이용된다.In FIG. 1 (f), TEOS 12A and BPSG 12B are sequentially deposited on the entire upper surface to form an insulating film 12, and then the photosensitive film 13 is coated on the entire upper surface. The photoresist layer 13 is patterned by a photolithography and an etching process using a contact mask, and the insulating layer 12 is wet-etched to a predetermined depth using the patterned photoresist 13 as a mask. Thereafter, the insulating layer 12 and the first polycrystalline silicon layer 5B having the remaining thickness are sequentially etched to form a contact hole 14 so that the barrier layer 4 is exposed. 14 is formed to penetrate the junction region 11 formed in the first polycrystalline silicon layer 5B, wherein the barrier layer 4 is used as an etch stop layer and a damage preventing layer of the silicon substrate 1. do.
제1(g)도는 상기 콘택홀(14)이 매립되도록 전체 상부면에 알루미늄 (A1)과 같은 금속(Metal)을 증착하여 금속층을 형성한 후 금속배선용 마스크를 이용한 사진 및 식각공정으로 상기 금속층을 패터닝하여 금속배선(15)을 형성한 상태의 단면도이다.In FIG. 1 (g), the metal layer is formed by depositing a metal, such as aluminum (A1), on the entire upper surface of the contact hole 14 to fill the metal layer. It is sectional drawing in the state which patterned and the metal wiring 15 was formed.
이와 같이 제조되는 반도체 소자는 첫째, 채널의 도핑 농도가 낮아 상기 베리어층(4)과 동일한 깊이까지 공핍영역(Depletion Region)이 형성되므로 쇼트 채널 효과에 대한 저항성이 증가되며, 핫 케리어(Hot Carrier)에 의해 발생되는 정공(Ho1e)으로 인한 스냅 백(Snap Back) 등의 문제점이 개선된다. 둘째, 상기 제 1 다결정 실리콘층(5B)의 두께 조절을 통해 접합 깊이를 정확히 조절할 수 있으며, 접합영역(11)이 균일하게 도핑되므로써 전류의 흐름이 효과적으로 극대화된다. 셋째, 상기 접합영역(11)과 채널이 상기 LDD영역(9)에 의해 완전히 분리되므로써 핫 케리어 또는 펀치 쓰루우(Punch through) 등의 문제점이 개선된다. 네째, 상기 콘택홀(14)을 상기 접합영역(11)을 관통하도록 형성하므로써 금속배선(15)과 접합영역(11)과의 접촉이 깊이 방향으로 완전하게 이루어져 전류의 흐름에 대한 기생 저항을 최대한 억제시킬 수 있다. 즉, 전류 집중 현상이 발생되지 않아 소자의 전류 구동능력이 향상된다. 다섯째, 접합영역(11)에서 기생 정전 용량이 발생되지 않도록 하여 소자의 동작속도가 향상된다.In the semiconductor device fabricated as described above, first, since the depletion region is formed to the same depth as the barrier layer 4 due to the low doping concentration of the channel, resistance to the short channel effect is increased, and a hot carrier Problems such as snap back due to holes Ho1e generated by the present invention are improved. Second, the junction depth can be precisely adjusted by controlling the thickness of the first polycrystalline silicon layer 5B, and the current flow is effectively maximized by uniformly doping the junction region 11. Third, since the junction region 11 and the channel are completely separated by the LDD region 9, problems such as hot carrier or punch through are improved. Fourth, since the contact hole 14 is formed to penetrate through the junction region 11, the contact between the metal wiring 15 and the junction region 11 is completely completed in the depth direction to maximize the parasitic resistance to the flow of current. Can be suppressed. That is, the current concentration phenomenon does not occur, thereby improving the current driving capability of the device. Fifth, the operating speed of the device is improved by preventing parasitic capacitance from occurring in the junction region 11.
상술한 바와 같이 본 발명에 의하면 접합영역의 하부에 베리어층을 형성하고 상기 접합영역이 관통되도록 콘택홀을 형성하므로써 소자의 전기적특성이 향상될 수 있는 탁월한 효과가 있다.As described above, according to the present invention, the barrier layer is formed below the junction region and the contact hole is formed to penetrate the junction region, thereby improving the electrical characteristics of the device.
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