KR100314800B1 - method of fabricating thin film transistor in semiconductor device - Google Patents
method of fabricating thin film transistor in semiconductor device Download PDFInfo
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- KR100314800B1 KR100314800B1 KR1019980024580A KR19980024580A KR100314800B1 KR 100314800 B1 KR100314800 B1 KR 100314800B1 KR 1019980024580 A KR1019980024580 A KR 1019980024580A KR 19980024580 A KR19980024580 A KR 19980024580A KR 100314800 B1 KR100314800 B1 KR 100314800B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
- H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
- H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
- H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
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Abstract
본 발명은 반도체 기술에 관한 것으로, 특히 SRAM(static random access memory) 등에 사용되는 반도체 소자의 박막 트랜지스터(thin film transistor, TFT) 제조방법에 관한 것이며, 강한 드레인 전계에 의한 오프 상태의 전류의 증가와, 게이트 에지의 기하학적 구조에 의한 전계 집중에 따른 게이트 산화막의 열화와, 채널용 전도막 식각시 게이트 측벽 부분에 레지듀가 잔류하는 현상을 방지하는 반도체 소자의 박막 트랜지스터 제조방법을 제공하는데 그 목적이 있다. 본 발명은 게이트 절연막 형성 전에 오프셋 영역을 덮는 절연막 패턴을 형성하여 강한 드레인 전계에 의한 오프 상태의 전류의 증가를 방지하고, 또한 상기 절연막 패턴 형성시 게이트 측벽에 스페이서를 형성하여 게이트 에지의 기하학적 구조에 의한 전계 집중에 따른 게이트 산화막의 열화와, 채널용 전도막 식각시 게이트 측벽 부분에 레지듀가 잔류하는 현상을 방지하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a method for manufacturing a thin film transistor (TFT) of a semiconductor device used for static random access memory (SRAM) and the like, and to increase the current in the off state by a strong drain electric field. To provide a method of manufacturing a thin film transistor of a semiconductor device to prevent the gate oxide film deterioration due to the concentration of the electric field due to the geometry of the gate edge and the residue remaining on the gate sidewall portion during the etching of the channel conductive film. have. The present invention forms an insulating film pattern covering the offset region prior to forming the gate insulating film to prevent an increase in the off-state current caused by a strong drain electric field, and also forms a spacer on the gate sidewall when forming the insulating film pattern to form a gate edge geometry. This is a technique for preventing the deterioration of the gate oxide film due to the concentration of the electric field and the phenomenon of residue remaining on the gate sidewall portion during the channel conductive film etching.
Description
본 발명은 반도체 기술에 관한 것으로, 특히 SRAM(static random access memory) 등에 사용되는 반도체 소자의 박막 트랜지스터(thin film transistor, TFT) 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a method of manufacturing a thin film transistor (TFT) of a semiconductor device used for static random access memory (SRAM).
종래의 바텀 게이트형 TFT를 사용하는 SRAM과 같은 소자에서는 TFT 게이트 폴리실리콘막을 정의하고, TFT 게이트 산화막을 형성한 다음, 노드 콘택에 접속되는 채널 폴리실리콘막을 정의하는 공정을 통해 제조해 왔다.In a device such as an SRAM using a conventional bottom gate type TFT, a TFT gate polysilicon film is defined, a TFT gate oxide film is formed, and a channel polysilicon film connected to a node contact is manufactured by a process.
이러한 공정을 통해 형성된 종래의 일반적인 바텀 게이트형 TFT는 게이트 산화막이 게이트 폴리실리콘막의 에지 부분을 지나가게 되는데, 보통 이 부분에 기하학적인 이유로 전계가 집중되어 TFT 게이트 산화막의 특성을 열화시키게 된다.In a conventional general bottom gate type TFT formed by such a process, a gate oxide film passes through an edge portion of a gate polysilicon film. In general, an electric field is concentrated in this portion to deteriorate the characteristics of the TFT gate oxide film.
또한, 바텀 게이트형 TFT에서 채널 폴리실리콘막이 TFT 게이트 폴리실리콘막의 측벽을 따라 형성되는데, 후속 채널 폴리실리콘막 식각시의 식각 타겟이 320Å 정도로 매우 작기 때문에 TFT 게이트 폴리실리콘막 측벽 부분에 형성된 채널 폴리실리콘막을 레지듀(residue) 없이 완전히 제거하는데 어려움이 있었다.In addition, in the bottom gate type TFT, a channel polysilicon film is formed along the sidewalls of the TFT gate polysilicon film, and the channel polysilicon formed on the sidewall portion of the TFT gate polysilicon film is very small because the etch target during the subsequent channel polysilicon film etching is about 320 kV. There was a difficulty in removing the membrane completely without the residue.
그리고, TFT의 특성을 위해 통상 200∼250Å 두께의 게이트 산화막을 사용하는데, 이러한 두께의 게이트 산화막에서는 TFT의 드레인에 걸리는 전계가 강해 오프 상태의 전류(off current)가 증가하는 문제점이 있었다.In addition, a gate oxide film having a thickness of 200 to 250 kHz is usually used for the characteristics of the TFT. In such a gate oxide film, an electric field applied to the drain of the TFT is strong, so that an off current increases.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 강한 드레인 전계에 의한 오프 상태의 전류의 증가와, 게이트 에지의 기하학적 구조에 의한 전계 집중에 따른 게이트 산화막의 열화와, 채널용 전도막 식각시 게이트 측벽 부분에 레지듀가 잔류하는 현상을 방지하는 반도체 소자의 박막 트랜지스터 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, the increase in the off-state current by the strong drain electric field, deterioration of the gate oxide film due to the electric field concentration due to the geometry of the gate edge, and for the channel SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a thin film transistor of a semiconductor device which prevents a residue from remaining on a gate sidewall portion during etching of a conductive film.
도 1a 내지 도 1f는 본 발명의 일 실시예에 따른 SRAM의 바텀 게이트형 박막 트랜지스터(TFT) 제조 공정도.1A to 1F illustrate a bottom gate type thin film transistor (TFT) fabrication process diagram of an SRAM according to an embodiment of the present invention.
도 2는 본 발명의 일 실시예에 따라 형성된 TFT의 레이아웃도.2 is a layout diagram of a TFT formed according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 실리콘 기판11 : 구동 트랜지스터의 게이트10 silicon substrate 11: gate of driving transistor
12 : 층간절연막13, 17 : 폴리실리콘막12: interlayer insulating film 13, 17: polysilicon film
13a : TFT 게이트13b : 노드 콘택13a: TFT gate 13b: node contact
14 : 산화막14a : 산화막 패턴14 oxide film 14a oxide film pattern
14b : 산화막 스페이서15, 18 : 포토레지스트 패턴14b: oxide spacer 15, 18: photoresist pattern
16 : 게이트 산화막16: gate oxide film
상기의 기술적 과제를 달성하기 위한 본 발명의 특징적인 반도체 소자의 박막 트랜지스터 제조방법은, 소정의 하부층이 형성된 기판 상에 게이트를 형성하는 단계; 상기 게이트가 형성된 전체 구조 상부에 절연막을 형성하는 단계; 상기 절연막을 선택 식각하여 드레인 오프셋 영역을 덮는 절연막 패턴을 형성하고, 상기 절연막 패턴이 형성되지 않는 상기 게이트 측벽에 절연막 스페이서를 형성하는 단계; 상기 게이트 표면에 게이트 절연막을 형성하는 단계; 및 소오스, 드레인 및 채널을 형성하는 단계를 포함하여 이루어진다.According to another aspect of the present invention, a method of manufacturing a thin film transistor of a semiconductor device includes: forming a gate on a substrate on which a predetermined lower layer is formed; Forming an insulating film on the entire structure where the gate is formed; Selectively etching the insulating film to form an insulating film pattern covering a drain offset region, and forming an insulating film spacer on the sidewall of the gate where the insulating film pattern is not formed; Forming a gate insulating film on the gate surface; And forming a source, a drain, and a channel.
즉, 본 발명은 게이트 절연막 형성 전에 오프셋 영역을 덮는 절연막 패턴을 형성하여 강한 드레인 전계에 의한 오프 상태의 전류의 증가를 방지하고, 또한 상기 절연막 패턴 형성시 게이트 측벽에 스페이서를 형성하여 게이트 에지의 기하학적 구조에 의한 전계 집중에 따른 게이트 산화막의 열화와, 채널용 전도막 식각시 게이트 측벽 부분에 레지듀가 잔류하는 현상을 방지하는 기술이다.That is, the present invention forms an insulating film pattern covering the offset region before forming the gate insulating film to prevent an increase in the off-state current due to a strong drain electric field, and also forms a spacer on the gate sidewall when forming the insulating film pattern to form a geometric shape of the gate edge. It is a technique for preventing the deterioration of the gate oxide film due to the concentration of the electric field due to the structure and the phenomenon of residue remaining on the gate sidewall portion during the channel conductive film etching.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 1a 내지 도 1f는 본 발명의 일 실시예에 따른 SRAM의 바텀 게이트형 TFT 제조 공정을 도시한 것으로, 이하 이를 참조하여 그 공정을 살펴본다.1A to 1F illustrate a process of manufacturing a bottom gate TFT of an SRAM according to an exemplary embodiment of the present invention. Hereinafter, the process will be described with reference to the accompanying drawings.
우선, 도 1a에 도시된 바와 같이 실리콘 기판(10) 상에 액세스 트랜지스터(도시되지 않음), 구동 트랜지스터 등의 벌크(bulk) 트랜지스터를 형성한 다음, 층간절연막(12)을 증착하고, 이를 선택 식각하여 노드 콘택홀을 형성한다. 이어서, 전체구조 상부에 TFT 게이트 형성을 위한 폴리실리콘막(13)을 형성한다. 미설명 도면 부호 '11'은 구동 트랜지스터의 게이트를 나타낸 것이다.First, as shown in FIG. 1A, a bulk transistor such as an access transistor (not shown), a driving transistor, or the like is formed on the silicon substrate 10, and then an interlayer insulating layer 12 is deposited, which is selectively etched. To form node contact holes. Subsequently, a polysilicon film 13 for forming a TFT gate is formed on the entire structure. Unexplained reference numeral 11 denotes a gate of the driving transistor.
다음으로, 도 1b에 도시된 바와 같이 폴리실리콘막(13)을 선택 식각하여 TFT 게이트(13a) 및 노드 콘택(13b)을 패터닝하고, 전체구조 상부에 산화막(14)을 증착한 다음, 산화막(14) 상에 포토레지스트 패턴(15)을 형성한다. 이때, 산화막(14)은 고온 산화막(hot temperature oxide, HTO)을 사용하며, 포토레지스트 패턴(15)은 후속 공정시 형성된 드레인 오프셋(offset) 영역을 덮도록 형성하는데, 포토레지스트 패턴(15)이 TFT 게이트(13a)의 드레인측 일부에 오버랩 되도록 한다. 물론 산화막(14)으로서 다른 종류의 절연막을 증착할 수도 있다.Next, as illustrated in FIG. 1B, the polysilicon film 13 is selectively etched to pattern the TFT gate 13a and the node contact 13b, and the oxide film 14 is deposited on the entire structure, and then the oxide film ( 14 is formed on the photoresist pattern 15. In this case, the oxide film 14 uses a hot temperature oxide (HTO), and the photoresist pattern 15 is formed to cover the drain offset region formed in a subsequent process, and the photoresist pattern 15 is A portion of the drain side of the TFT gate 13a is overlapped. Of course, another kind of insulating film may be deposited as the oxide film 14.
계속하여, 도 1c에 도시된 바와 같이 포토레지스트 패턴(15)을 식각 마스크로 사용하여 산화막(14)을 이방성 식각함으로써 드레인 오프셋 영역을 덮는 산화막 패턴(14a)과, TFT 게이트(13a)의 측벽에 산화막 스페이서(14b)를 형성한 다음, 포토레지스트 패턴(15)을 제거한다.Subsequently, as shown in FIG. 1C, the oxide film 14 is anisotropically etched using the photoresist pattern 15 as an etching mask, and the oxide film pattern 14a covering the drain offset region is formed on the sidewalls of the TFT gate 13a. After the oxide spacer 14b is formed, the photoresist pattern 15 is removed.
이어서, 도 1d에 도시된 바와 같이 TFT 게이트(13a) 및 노드 콘택(13b) 표면에 게이트 산화막(16)을 형성한 다음, 게이트 산화막(16)을 선택 식각하여 노드 콘택(13b)의 일부를 노출시키고, 전체구조 상부에 채널 형성을 위한 폴리실리콘막(17)을 증착한다.Subsequently, as shown in FIG. 1D, the gate oxide film 16 is formed on the surfaces of the TFT gate 13a and the node contact 13b, and then the gate oxide film 16 is selectively etched to expose a portion of the node contact 13b. Then, a polysilicon film 17 for forming a channel is deposited on the entire structure.
다음으로, 도 1e에 도시된 바와 같이 폴리실리콘막(17)에 이온주입을 실시하여 소오스, 드레인 및 채널 영역을 형성하고, 그 상부에 단위 TFT를 디파인하기 위한 포토레지스트 패턴(18)을 형성한다.Next, as illustrated in FIG. 1E, ion implantation is performed on the polysilicon film 17 to form a source, a drain, and a channel region, and a photoresist pattern 18 for defining the unit TFT is formed thereon. .
계속하여, 도 1f에 도시된 바와 같이 포토레지스트 패턴(18)을 식각 마스크로 사용하여 폴리실리콘막(17)을 선택 식각함으로써 TFT 형성을 완료한다. 이때, TFT의 소오스측에 Vss 라인을 함께 디파인한다.Subsequently, TFT formation is completed by selectively etching the polysilicon film 17 using the photoresist pattern 18 as an etching mask as shown in FIG. 1F. At this time, the Vss line is defined together on the source side of the TFT.
첨부된 도면 도 2는 전술한 본 발명의 일 실시예에 따라 형성된 TFT의 레이아웃을 도시한 것으로, 도면 부호 '20'은 TFT 게이트 영역, '21a'는 산화막 패턴에 의한 드레인 오프셋 영역, '21b'는 산화막 스페이서 영역, '22'는 노드 콘택 영역, '23'은 TFT와 노드 콘택의 콘택 영역, '24a'는 소오스 영역, '24b'는 드레인 영역, '24c'는 채널 영역, 24d는 Vss 라인 영역을 각각 나타낸 것이다.2 is a diagram illustrating a layout of a TFT formed according to an exemplary embodiment of the present invention described above, wherein reference numeral '20' denotes a TFT gate region, '21a' denotes a drain offset region due to an oxide film pattern, and '21b'. Is an oxide spacer region, '22' is a node contact region, '23' is a TFT and node contact region, '24a' is a source region, '24b' is a drain region, '24c' is a channel region, and 24d is a Vss line. Each area is shown.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
이상에서와 같이 본 발명은 오프셋 영역을 덮는 절연막 패턴을 형성하여 강한 드레인 전계에 의한 오프 상태의 전류의 증가를 방지하는 효과가 있으며, 또한 게이트 측벽에 스페이서를 형성하여 게이트 에지의 기하학적 구조에 의한 전계 집중에 따른 게이트 산화막의 열화와, 채널용 전도막 식각시 게이트 측벽 부분에 레지듀가 잔류하는 현상을 방지하는 효과가 있으며, 이로 인하여 소자의 신뢰도를 향상시키는 효과가 있다.As described above, the present invention has an effect of preventing the increase of the off-state current caused by the strong drain electric field by forming the insulating film pattern covering the offset region, and by forming a spacer on the gate sidewall, the electric field due to the geometry of the gate edge There is an effect of preventing the deterioration of the gate oxide film due to concentration and the residue of residue in the gate sidewall portion during the etching of the conductive film for the channel, thereby improving the reliability of the device.
Claims (5)
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