KR100316018B1 - Method for fabricating storage node - Google Patents
Method for fabricating storage node Download PDFInfo
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- KR100316018B1 KR100316018B1 KR1019980025233A KR19980025233A KR100316018B1 KR 100316018 B1 KR100316018 B1 KR 100316018B1 KR 1019980025233 A KR1019980025233 A KR 1019980025233A KR 19980025233 A KR19980025233 A KR 19980025233A KR 100316018 B1 KR100316018 B1 KR 100316018B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
- H10D1/712—Electrodes having non-planar surfaces, e.g. formed by texturisation being rough surfaces, e.g. using hemispherical grains
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02082—Cleaning product to be cleaned
- H01L21/02087—Cleaning of wafer edges
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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Abstract
본 발명은 웨이퍼상에 절연막, 전도막 및 감광막 패턴을 차례로 형성하는 단계; 상기 감광막을 마스크로 하여 상기 전도막을 식각하여 전하저장전극용 패턴을 형성하는 단계; 상기 전하저장전극패턴상에 상기 웨이퍼의 가장자리부분을 노출시키는 이온주입 마스크를 형성하는 단계; 상기 이온주입 마스크를 이용하여 상기 노출된 가장자리부분에 CxFy계 이온을 주입시키는 단계; 및 상기 이온주입 마스크를 제거한 후 상기 전하저장전극패턴상에 MPS막을 성장시키는 단계를 포함한다.The present invention comprises the steps of sequentially forming an insulating film, a conductive film and a photosensitive film pattern on the wafer; Etching the conductive layer using the photosensitive layer as a mask to form a pattern for a charge storage electrode; Forming an ion implantation mask on the charge storage electrode pattern to expose an edge portion of the wafer; Implanting CxFy-based ions into the exposed edge portion using the ion implantation mask; And removing the ion implantation mask and growing an MPS film on the charge storage electrode pattern.
본 발명은 전하저장전극 패턴 형성시 최외각 지역에 남아 있는 얇은 전도막 부위에 CxFy계 가스를 플라즈마를 이용해 전도막에 주입함으로써 MPS 증착을 방해하여 성장을 억제시키는 제조 방법으로서 전도막 위에 원하지 않는 필름의 증착을 선택적으로 억제함으로써 소자의 결함을 미연에 제거할 수 있다.The present invention is a manufacturing method of inhibiting growth by inhibiting MPS deposition by injecting CxFy-based gas into a conductive film using a plasma in a thin conductive film portion remaining in the outermost region when forming a charge storage electrode pattern. By selectively suppressing the deposition of, defects in the device can be removed beforehand.
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 브리지(bridge)를 가지지 않는 전하저장전극 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a charge storage electrode having no bridge.
일반적으로, 반도체 기억 소자의 전하저장전극 형성에 있어서 MPS(metalstable polysilicon)가 이용되고 있다, 이 MPS는 전하저정전극 패턴 위에 성장되어 상기 전하저장전극의 용량을 1.5∼2배 이상 증가시킴으로써 DRAM급 반도체 소자에서 널리 사용하고 있다.In general, a metalstable polysilicon (MPS) is used to form a charge storage electrode of a semiconductor memory device. The MPS is grown on a charge storage electrode pattern to increase the capacity of the charge storage electrode by 1.5 to 2 times or more. It is widely used in devices.
그러나 상기 공정은 소자의 집적도가 높아짐에 따라 전하저장전극의 패턴 두께가 얇아지면서 웨이퍼의 최외각 지역에서 떨어져 나온 MPS조각들이 클리닝 공정을 통해 웨이퍼 내부로 입사되어 전하저장전극 사이에 존재함으로써 브리지를 유발시킨다.However, as the integration of the device increases, the pattern thickness of the charge storage electrode becomes thinner, and MPS fragments separated from the outermost region of the wafer are incident into the wafer through the cleaning process and are present between the charge storage electrodes, causing a bridge. Let's do it.
첨부된 도면 도 1a 내지 도 1d를 참조하여 이러한 브리지를 현상을 자세히 설명하면 다음과 같다.Referring to the accompanying drawings, the phenomenon of the bridge in detail with reference to Figures 1a to 1d as follows.
먼저, 도 1a에 도시된 바와 같이, 절연막, 전도막 및 감광막(P/R)이 형성된 반도체 소자의 전하저장전극용 마스크 작업시, 감광막이 웨이퍼 최외각지역에서 뭉침현상이 발생하여 웨이퍼를 담는 카세트와 식각 장비의 전극을 오염시키는 원인이 되므로 신너를 통해 웨이퍼 최외각에서 1.5㎜ 정도까지 감광막을 완전히 제거한다. 그러나, 이때도 신너를 통해 제거하므로 그 끝부분이 노광한 것에 비해 경사를 심하게 가지게 된다.First, as shown in FIG. 1A, when a mask for charge storage electrodes of a semiconductor device having an insulating film, a conductive film, and a photoresist film (P / R) is formed, the photoresist agglomerates in the outermost region of the wafer, and thus a cassette containing the wafer. As it causes contamination of the electrodes of the etching equipment and the etching equipment, the photoresist is completely removed from the outermost surface of the wafer to about 1.5 mm through the thinner. However, even at this time, since the thinner is removed through the thinner, the tip portion has a slant more severe than that exposed.
이어서, 도 1b에 도시된 바와 같이, 상기 감광막의 경사도는 전하저장 전극 패턴 형성을 위한 건식식각시 전도막을 경사지게 한다.Subsequently, as shown in FIG. 1B, the inclination of the photosensitive film inclines the conductive film during dry etching for forming the charge storage electrode pattern.
도 1c는 상기 경사진 전도막의 상부에 MPS막을 성장시키면, 도 1d에 도시된 바와 같이, 이후 클리닝 공정(주로 QDR: Quick Dump Rinse)시 웨이퍼 최외각으로부터 안으로 밀려드는 습식 장비의 영향 때문에 경사져 취약해진 부분이 떨어져서 웨이퍼 내부로 입사된다.FIG. 1C shows that when the MPS film is grown on top of the inclined conductive film, as shown in FIG. 1D, it is inclined and vulnerable due to the influence of the wet equipment pushed in from the outermost wafer during the subsequent cleaning process (mainly QDR: Quick Dump Rinse). The part is separated and is incident into the wafer.
한편, 상기 종래 기술에 따른 전도막의 두께는 1000Å 이상으로 형성되어 상기 리프트 오프(lift off)를 최소화하였으나, 소자의 고집적화를 위해 전도막의 두께를 1000Å이하로 가져가만 된다, 이때는 상기 설명한 문제로 인하여 더욱더 브리지에 취약한 구조가 된다는 문제점을 안고 있었다.On the other hand, the thickness of the conductive film according to the prior art is formed to be 1000 Å or more to minimize the lift off (lift off), but only to bring the thickness of the conductive film below 1000 를 for high integration of the device, in this case due to the problem described above The problem was that the structure became more vulnerable to bridges.
따라서, 상기 문제점을 해결하기 위하여 안출된 본 발명은 고집적 반도체기억소자의 전하저장전극에서 유발되는 브리지를 효과적으로 제거함으로써 소자의 신뢰도 및 수율을 증가시킬 수 있는 반도체 소자의 전하저장전극 제조 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention devised to solve the above problems provides a method for manufacturing a charge storage electrode of a semiconductor device that can increase the reliability and yield of the device by effectively removing the bridge caused by the charge storage electrode of the highly integrated semiconductor memory device. The purpose is.
도 1a 내지 도 1d는 종래의 전하저장전극 형성 공정 단면도,1A to 1D are cross-sectional views of a conventional charge storage electrode forming process;
도 2a 내지 도 2c는 본 발명에 따라 브리지를 가지지 않는 전하저장전극 형성 공정 단면도.2A to 2C are cross-sectional views of a process for forming a charge storage electrode having no bridge according to the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
11: 감광막 12: 전도막11: photosensitive film 12: conductive film
13: 절연막 14: 이온주입마스크13: insulating film 14: ion implantation mask
15: MPS15: MPS
본 발명은 MPS 증착전 전하저장전극용 마스크 패턴을 이용하여 전하저장전극 패턴 형성이 완료된 셀 지역을 감광막으로 도포하여 보호하고 난 후, 도포되지 않은 부위에 CxFy 함유가스 플라즈마를 형성하여 CxFy계 이온을 폴리실리콘막에 주입한다. 상기 주입된 CxFy계 이온은 MPS막이 성장하는 것을 방해하여 원하지 않는 부위에 MPS가 자라는 것을 미연에 방지한다.The present invention uses a mask pattern for the charge storage electrode before MPS deposition to protect the cell region where the charge storage electrode pattern formation is completed by using a photosensitive film, and then forms a CxFy-containing gas plasma on the uncoated portion to form CxFy-based ions. Injected into the polysilicon film. The implanted CxFy-based ions prevent the growth of the MPS film and thus prevent the growth of the MPS at an unwanted site.
본 발명은 웨이퍼상에 절연막, 전도막 및 감광막 패턴을 차례로 형성하는 단계; 상기 감광막을 마스크로 하여 상기 전도막을 식각하여 전하저장전극용 패턴을형성하는 단계; 상기 전하저장전극패턴상에 상기 웨이퍼의 가장자리부분을 노출시키는 이온주입 마스크를 형성하는 단계; 상기 이온주입 마스크를 이용하여 상기 노출된 가장자리부분에 CxFy계 이온을 주입시키는 단계; 및 상기 이온주입 마스크를 제거한 후 상기 전하저장전극패턴상에 MPS막을 성장시키는 단계The present invention comprises the steps of sequentially forming an insulating film, a conductive film and a photosensitive film pattern on the wafer; Etching the conductive layer using the photosensitive layer as a mask to form a pattern for a charge storage electrode; Forming an ion implantation mask on the charge storage electrode pattern to expose an edge portion of the wafer; Implanting CxFy-based ions into the exposed edge portion using the ion implantation mask; And growing an MPS film on the charge storage electrode pattern after removing the ion implantation mask.
를 포함하여 이루어짐을 특징으로 한다.Characterized in that comprises a.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
먼저, 도 2a는 실리콘 기판 상에 절연막(13)을 증착한 후 그 상부에 전도막(12)을 증착하고, 상기 전도막(12) 상에 감광막(11) 패턴을 형성한 상태의 웨이퍼 최외각 지역의 단면도로서, 에지 비드 리무벌(edge bead removal) 공정이 완료된 후 감광막이 경사를 가지는 것을 알 수 있다. 상기 에지 비드 리무벌 공정 단계에서 웨이퍼 최외각 지역의 감광막을 0.5㎜∼5㎜ 까지 제거될 수도 있다.First, FIG. 2A illustrates an outermost wafer in a state in which an insulating film 13 is deposited on a silicon substrate, a conductive film 12 is deposited thereon, and a photosensitive film 11 pattern is formed on the conductive film 12. As a cross-sectional view of the area, it can be seen that the photoresist is inclined after the edge bead removal process is completed. In the edge bead removal process step, the photoresist of the outermost region of the wafer may be removed from 0.5 mm to 5 mm.
도 2b는 상기 감광막(11)을 마스크로 하여 전도막(12)을 식각하여 전하저장전극용 패턴을 형성하고 난 후에 전하저장전극 패턴이 형성된 지역만 다시 이온주입마스크(14) 작업을 한 웨이퍼 최외각 지역의 단면도로써, 전도막(12)의 경사가 감광막(11)의 경사를 그대로 따라가는 것을 알 수 있다. 상기 이온주입마스크(14) 작업이 완료된 후 CxFy 함유 가스로 플라즈마를 형성하여 드러난 웨이퍼의 모서리 부분에 CxFy계 이온을 주입시킨다. 상기 주입된 CxFy계 이온은 MPS의 성장을 방해하여 MPS를 성장하지 못하게 하는 역할을 한다.FIG. 2B illustrates a wafer having the ion implantation mask 14 reworked only in the region where the charge storage electrode pattern is formed after etching the conductive film 12 using the photosensitive film 11 as a mask to form the charge storage electrode pattern. As a cross-sectional view of the outer region, it can be seen that the inclination of the conductive film 12 follows the inclination of the photosensitive film 11 as it is. After the ion implantation mask 14 is completed, CxFy-based ions are implanted into the edge portion of the exposed wafer by forming plasma with a CxFy-containing gas. The implanted CxFy-based ions interfere with the growth of the MPS and prevent the growth of the MPS.
도 2c는 그 상부에 MPS막(15)을 성장시킨 후의 웨이퍼 최외각 지역의 단면으로써 마스크가 없었던 지역에는 MPS막(15)이 전혀 성장하지 않아 이후 클리닝 공정에서도 필름이 리프트 오프되는 현상이 발생하지 않는다.2C is a cross-sectional view of the outermost region of the wafer after growing the MPS film 15 thereon, and the MPS film 15 does not grow at all in the area where the mask was not present, and thus the film is not lifted off even in the subsequent cleaning process. Do not.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아니다. 또한, 본 발명의 기술분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above-described preferred embodiment, the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상기와 같이 이루어지는 본 발명은 하부 필름에 임의의 가스 플라즈마를 이용하여 주입시켜 성장을 목적으로 증착하는 상부 필름을 선택적으로 취할 수 있다. 이러한 방법을 통하여 소자의 동작에 치명적인 결함을 가져오는 브리지 문제를 완전 해소할 수 있으며 차세대 반도체 소자의 개발도 한 층 앞당길 수 있다. 아울러 반도체 소자의 신뢰성과 수율을 향상시킬 수 있고, 신규 장비 투자 없이 반도체 소자의 집적도를 높일 수 있다.The present invention made as described above may selectively take an upper film which is deposited for the purpose of growth by injecting the lower film using an arbitrary gas plasma. In this way, the bridge problem that causes fatal defects in the operation of the device can be completely solved and the development of the next-generation semiconductor device can be further advanced. In addition, the reliability and yield of semiconductor devices can be improved, and the integration of semiconductor devices can be increased without investing in new equipment.
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|---|---|---|---|
| KR1019980025233A KR100316018B1 (en) | 1998-06-30 | 1998-06-30 | Method for fabricating storage node |
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| KR1019980025233A KR100316018B1 (en) | 1998-06-30 | 1998-06-30 | Method for fabricating storage node |
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| KR20000003925A KR20000003925A (en) | 2000-01-25 |
| KR100316018B1 true KR100316018B1 (en) | 2002-06-20 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58143527A (en) * | 1982-02-22 | 1983-08-26 | Toshiba Corp | Manufacture of semiconductor device |
| JPH022638A (en) * | 1988-06-15 | 1990-01-08 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
-
1998
- 1998-06-30 KR KR1019980025233A patent/KR100316018B1/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58143527A (en) * | 1982-02-22 | 1983-08-26 | Toshiba Corp | Manufacture of semiconductor device |
| JPH022638A (en) * | 1988-06-15 | 1990-01-08 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
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