KR100319921B1 - A ferroelectric memory and a method for fabricating and operating the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory using a depletion capacitance, which allows a bound charge formed by polarization of a ferroelectric to be formed at a p-n junction of a source, a method of manufacturing the same, and a method of operating the same. In the ferroelectric memory using the depletion capacitance according to the present invention, the bound charge formed by the polarization of the ferroelectric is formed at the pn junction of the transistor drain, so that the structure is simple and is applied to each memory cell. Not only can the recorded information be read and written arbitrarily, but also the information of the memory cells can be read in particular non-destructively.

Description

A ferroelectric memory and a method for fabricating and operating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory using a depletion capacitance that allows a bound charge formed by polarization of a ferroelectric to be formed at a p-n junction of a drain, a method of manufacturing the same, and a method of operating the same.

1T-1C ferroelectric random access memory (FRAM) structure, where each conventional memory cell consists of a pair of transistors and one capacitor, recovers data because it reads in a destructive read out (DRO) mode instead of having a RAM function. access time loss due to the need for restoration, and nondestructive read out FRAM (NDRO FRAM) can be virtually RAM, similar to flash memory. The non-destructive read (NDRO) 1T-1C TFT-FRAM overcoming this problem is that TFT performance is still inferior to CMOS transistors, and NDRO 1T-1C CMOS FRAM has a complicated disadvantage of manufacturing CMOS transistors. have.

The present invention has been devised to solve the above problems, and by forming a bound charge due to polarization of the ferroelectric at the pn junction of the source, the information recorded in each memory cell is non-destructive. The purpose of the present invention is to provide a ferroelectric memory using a depletion capacity that can be arbitrarily read and written, and a method of manufacturing and operating the same.

1 is a vertical sectional view of a first embodiment of a ferroelectric memory using a depletion capacity according to the present invention;

2 is a vertical sectional view of a second embodiment of a ferroelectric memory using a depletion capacity according to the present invention;

3 is a vertical cross-sectional view of a third embodiment of a ferroelectric memory using the depletion capacity according to the present invention;

4A is a diagram for describing a write '1' operation of the first embodiment of FIG. 1;

4B is a view illustrating a normal state of a memory cell after a write '1' operation of the first embodiment of FIG. 4A;

FIG. 4C is a diagram for describing an operation of writing '0' in the first embodiment of FIG. 1; FIG.

4D is a view illustrating a normal state of a memory cell after a write '0' operation of the first embodiment of FIG. 4C;

5A is a view for explaining a read '1' operation of the first embodiment of FIG. 1;

5B is a diagram for describing a read '0' operation of the first embodiment of FIG. 1.

<Description of the symbols for the main parts of the drawings>

1. Bit line 2. Plate line

3. Ferroelectric capacitor upper electrode 3 '. Dielectric Capacitor Top Electrode

4. Ferroelectric 5. Bottom electrode of ferroelectric capacitor

5 '. Dielectric Capacitor Bottom Electrode 6. Contact Plug

7. Source 8. Word line (gate)

8'. Dielectric capacitor upper electrode of same material as gate material

9. Drain 10. High dielectric or high dielectric

10 '. Insulator, Dielectric, or High Dielectric

In order to achieve the above object, a ferroelectric memory using a depletion capacity according to the present invention includes a semiconductor substrate; CMOS transistors formed on the semiconductor substrate to correspond to each memory cell; Dielectric capacitors formed on the drains of the CMOS transistors; Ferroelectric capacitors formed on the source of the CMOS transistors; Word lines formed to connect gates of the CMOS transistors arranged on a stripe in one direction; Plate lines formed to connect upper electrodes of the ferroelectric capacitor arranged on a stripe in a direction crossing the word lines; And bit lines formed to connect upper electrodes of the dielectric capacitors arranged in a stripe in a direction parallel to the plate lines.

In the present invention, first contact plugs electrically connecting the dielectric capacitor and the drain between the dielectric capacitor and the drain and between the ferroelectric capacitor and the source, respectively; And second contact plugs electrically connecting the ferroelectric capacitor and the source, wherein the first contact plug, the second contact plug, the dielectric capacitor, and the ferroelectric capacitor are each formed in a twin structure having the same thickness. desirable.

In the present invention, the first contact plug and the second contact plug may be formed to have different thicknesses, and the dielectric capacitor and the ferroelectric capacitor may be formed in a step structure.

Further, in the present invention, a dielectric of the dielectric capacitor is formed directly above the drain so that the drain serves as an electrode below the dielectric capacitor, and electrically connects the ferroelectric capacitor and the source between the ferroelectric capacitor and the source. It is preferable that contact plugs are formed, and the dielectric is stacked to the same thickness using the same material as the gate axe below the gate, and the upper electrode of the dielectric capacitor is formed to the same thickness using the same material as the gate. .

In addition, to achieve the above object, a method of manufacturing a ferroelectric memory using a depletion capacity according to the present invention, (A) forming a contact plug on the source and drain of the CMOS transistor formed on the semiconductor substrate, respectively; (B) forming a dielectric capacitor bottom electrode and a ferroelectric capacitor bottom electrode on the contact plugs, respectively; (C) forming a dielectric on the lower electrode of the dielectric capacitor and forming a ferroelectric on the lower electrode of the ferroelectric capacitor; (D) forming upper electrodes on the dielectric and ferroelectric, respectively; (E) forming plate lines connecting the ferroelectric capacitor upper electrodes on a stripe in one direction; And (f) forming bit lines connecting the dielectric capacitor upper electrodes onto a stripe in one direction.

In the present invention, in the step (a), the contact plugs on the source and the contact plugs on the drain are simultaneously formed, and in the step (b), the electrode under the dielectric capacitor and the electrode under the ferroelectric capacitor are simultaneously formed. The (c) step may include: (c) a sub-step of simultaneously forming the ferroelectric on the dielectric capacitor lower electrodes and the ferroelectric capacitor lower electrodes; And (c-2) a sub-step of forming a dielectric by injecting a dopant into the ferroelectrics formed on the lower electrodes of the dielectric capacitor.

In the present invention, in the step (a), the thicknesses of the contact plugs on the source and the contact plugs on the drain are different from each other, and in the step (c), the thicknesses of the dielectric and the ferroelectric are equal to or different from each other. It is also desirable to form differently.

In the present invention, in step (a), only the contact plugs are formed on the source, and in step (b), only the electrode under the ferroelectric capacitor is formed on the contact plug on the source. (C-1) a sub-step of forming the dielectric directly over the drain of the CMOS transistor and simultaneously forming the gate insulating layer using a gate axide forming an insulating layer of the gate; And (c-2) a sub step of simultaneously forming the dielectric capacitor upper electrodes using the same material as the gate.

In addition, to achieve the above object, a method of operating a ferroelectric memory using a depletion capacity according to the present invention includes a semiconductor substrate; CMOS transistors formed on the semiconductor substrate to correspond to each memory cell; Dielectric capacitors formed on the drains of the CMOS transistors; Ferroelectric capacitors formed on the source of the CMOS transistors; Word lines formed to connect gates of the CMOS transistors arranged on a stripe in one direction; Plate lines formed to connect upper electrodes of the ferroelectric capacitor arranged on a stripe in a direction crossing the word lines; And bit lines formed to connect upper electrodes of the dielectric capacitors arranged in a stripe in a direction parallel to the plate lines, wherein the method comprises: (a) applying a voltage to the word line to address a memory cell; (B) writing information by applying a potential difference between the bit line and the plate line; And (c) reading information through a sense amplifier connected to the bit line.

Hereinafter, a ferroelectric memory using a depletion capacity according to the present invention, a manufacturing method thereof, and an operating method thereof will be described in detail with reference to the accompanying drawings.

In the ferroelectric memory using the depletion capacitance according to the present invention, the bound charge formed by the polarization of the ferroelectric is formed at the pn junction of the transistor drain, so that the structure is simple and is applied to each memory cell. In addition to being able to read and write the recorded information arbitrarily, there is a particular feature that the information of the memory cell can be read non-destructively. The specific structure of the embodiment of these ferroelectric memories is as shown in Figs.

First, FIGS. 1 to 3 are vertical cross-sectional views of ferroelectric memories using depletion capacities according to the present invention, and show vertical cross sections of each memory cell. As shown, in the ferroelectric memory using the depletion capacitance according to the present invention, the common dielectric capacitors 3 ', 10, 5' are connected to the drain 9 of the transistor and the ferroelectric capacitor is connected to the CMOS transistors 9, 8, and 7. (3, 4, 5) has a structure connected to the source 7 of the transistor. Herein, a general dielectric is referred to as a dielectric capacitor due to the characteristics of the material. In addition, a dielectric material or a high dielectric material may be used as a material for forming the dielectric capacitor. A high dielectric material is preferable. Such a structure can be seen as a COB (capacitor on bit line) structure. Each capacitor is connected to the drain 9 and the source 7 with a contact plug 6 between the contact plug 6 and the lower electrodes 5, 5 ′ or with a contact plug ( A barrier layer (not shown) may be inserted between the contact plug 6 and the drain 9 or between the contact plug 6 and the source 7. The two capacitors, the dielectric capacitor and the ferroelectric capacitor, may be manufactured in the same height and thickness in a twin structure as in the first embodiment of FIG. 1, or the second and third embodiments of FIG. 2 and FIG. 3. Similarly, stepped structures are fabricated one after the other at different heights. Also, as in the third embodiment of FIG. 3, the dielectric capacitor is formed such that the drain 9 is in contact with the ferroelectric layer 10 'so that the drain 9 is used as the lower electrode of the ferroelectric capacitor. Also, in the case of the dielectric capacitors 3 ', 10', and 5 ', the upper electrode 8' is gated as the dielectric 10 'if the same material is used at the same height as the word line 8. It is also possible to use the same insulating material as the gate oxide.

On the other hand, when fabricating the dielectric capacitor in the twin structure of FIG. 1 (first embodiment), the contact plug 6 and the lower electrodes 5 and 5 'are fabricated simultaneously, and the ferroelectric material is deposited at the same time to make the dielectric. The dopant is implanted into the ferroelectric in the capacitor region to make the dielectric constant. After that, the upper electrodes 3 and 3 'are also produced simultaneously. In the stepped structure of FIGS. 2 and 3, ferroelectric capacitors may be fabricated first and dielectric capacitors may be fabricated later, or dielectric capacitors may be fabricated and ferroelectric capacitors may be fabricated later. In particular, in the third embodiment of FIG. 3, when the word line 8 is fabricated, the upper electrode 8 'of the dielectric capacitor is also fabricated simultaneously using the same material as the word line 8. In this case, the dielectric or high dielectric material is first filled between the drain 9 and the upper electrode 8 '.

The operating method of the ferroelectric memory using the depletion capacity thus produced is shown in FIGS. 4A to 4D and FIGS. 5A and 5B. 4A to 4D are diagrams for describing a write operation of the first embodiment of FIG. 1, and FIGS. 5A and 5B are views for explaining a read operation of the first embodiment of FIG. 1.

First, as shown in FIG. 4A, a voltage Vw is applied to a word line 8 to address a memory cell to be written, and a voltage Vb is applied to a bit line 1. When applied to polarize the ferroelectric 4, it is recorded as '1'. As shown in FIG. 4C, when the voltage Vw is first applied to the word line 8 to address the memory cell, and the voltage Vp is applied to the plate line 2, the ferroelectric becomes' 0 'is recorded.

When it is written as' 1 ', the negative charge is bound to the ferroelectric capacitor upper electrode 3 and the positive charge is bound to the dielectric capacitor upper electrode 3' as shown in FIG. 4A. As the voltage is released, the bond charges of the dielectric capacitor are discharged as shown in FIG. 4B and the positive charge is bound to the lower electrode 5 of the ferroelectric capacitor. These positive charges are supplied from the substrate of the grounded CMOS transistor. This is called the normal stae of '1'.

When it is recorded as' 0 ', positive charge is bound to the ferroelectric capacitor upper electrode 3 and negative charge is bound to the dielectric capacitor upper electrode 3' as shown in FIG. 4C. As the applied voltage is released, as shown in FIG. 4D, the charges of the dielectric capacitor are discharged and the negative charge is bound to the pn junction of the drain below the ferroelectric capacitor, not the bottom electrode 5. As such, the reason why the negative charge is not bound to the lower electrode 3 of the ferroelectric capacitor and the pn junction of the drain is constrained is that even though the negative charge is supplied from the CMOS substrate, the pn junction between the transistor well and the source 7 is maintained. As the junction is formed, the negative charge stays depleted in the junction region between the well and the source 7 without reaching the ferroelectric capacitor lower electrode 5 through the source 7. The voltage applied to the junction region is determined by the magnitude of the capacitance of the depletion region and the amount of negative charge. This voltage acts as a back voltage, which may invert or depolarize the polarization of the ferroelectric 4, so a p-n junction should be made under such a condition that this phenomenon does not occur. The state where the depletion charge is formed is called a normal state of '0'.

Next, as shown in Figs. 5A and 5B, when reading these memory states, a sense amplifier connected to a word line 8 and a bit line 1 is shown. amplifer; S / A). That is, when the voltage Vw is applied to the word line 8 to address the channel of the transistor.

As shown in FIG. 5A, when the addressed memory cell is written as '1', since the positive charge is already bound to the lower electrode 5 of the ferroelectric capacitor, there is no charge transfer even if the channel of the transistor is opened. . That is, no current is detected in the sense amplifier. Therefore, we write 'off'.

As shown in FIG. 5B, when the addressed memory cell is written as '0', since the pn junction is connected to the dielectric capacitor through the channel, the depletion charge of the pn junction disappears, and instead, the upper electrode of the dielectric capacitor ( Negative charge is bound (induced) to 3 '). In other words, it may be called charging. Alternatively, the charge may be expressed as transferred. This charging current is detected by a sense amplifier S / A connected to the bit line 1. Sometimes referred to as 'on'.

In conclusion, this read operation can be regarded as non-destructive read (NDRO) because the read operation can be performed without causing polarization inversion of the ferroelectric 4. In the above, the FRAM structure is referred to as depletion FRAM (DFRAM).

As described above, the ferroelectric memory using the depletion capacity according to the present invention allows the bound charges formed by the polarization of the ferroelectric to be formed at the pn junction of the transistor source, thereby simplifying the structure of each memory. Not only can the information recorded in the cell be read and written arbitrarily, but also the information of the memory cell can be read non-destructively. Therefore, like 1T-1C FRAM, random memory cells can be accessed and read and written, and NVRAM can be read and read in NDRO type. The transistor manufacturing process is simple.

Claims (15)

Semiconductor substrates; CMOS transistors formed on the semiconductor substrate to correspond to each memory cell; Dielectric capacitors formed on the drains of the CMOS transistors; And Ferroelectric capacitors formed on the source of the CMOS transistors; Word lines formed to connect gates of the CMOS transistors arranged on a stripe in one direction; Plate lines formed to connect upper electrodes of the ferroelectric capacitor arranged on a stripe in a direction crossing the word lines; And Bit lines formed to connect upper electrodes of the dielectric capacitor arranged on the stripe in a direction parallel to the plate lines; Ferroelectric memory using a depletion capacity, characterized in that provided. The method of claim 1, First contact plugs electrically connecting the dielectric capacitor and the drain between the dielectric capacitor and the drain and between the ferroelectric capacitor and the source, respectively; And Second contact plugs electrically connecting the ferroelectric capacitor and a source; Ferroelectric memory using a depletion capacity, characterized in that provided. The method of claim 2, And the first contact plug, the second contact plug, the dielectric capacitor, and the ferroelectric capacitor are formed in twin structures having the same thickness, respectively. The method of claim 3, The dielectric of the dielectric capacitor is a ferroelectric memory using a depletion layer, characterized in that the dopant is doped with a ferroelectric material of the ferroelectric capacitor. The method of claim 2, The first contact plug and the second contact plug are formed to have different thicknesses, so that the dielectric capacitor and the ferroelectric capacitor have a stepped structure. The method of claim 1, A dielectric of the dielectric capacitor is formed directly above the drain such that the drain serves as an electrode below the dielectric capacitor, and contact plugs electrically connecting the ferroelectric capacitor and the source are formed between the ferroelectric capacitor and the source. Ferroelectric memory using depletion capacity. The method of claim 6, The dielectric is stacked with the same thickness using the same material as the gate axe below the gate, and the upper electrode of the dielectric capacitor is formed with the same thickness using the same material as the gate. Memory. The method of claim 1, The dielectric of the dielectric capacitor is a ferroelectric memory using a depletion layer, characterized in that consisting of a dielectric or high dielectric. (A) forming contact plugs on the source and the drain of the CMOS transistor formed on the semiconductor substrate, respectively; (B) forming a dielectric capacitor bottom electrode and a ferroelectric capacitor bottom electrode on the contact plugs, respectively; (C) forming a dielectric on the lower electrode of the dielectric capacitor and forming a ferroelectric on the lower electrode of the ferroelectric capacitor; (D) forming upper electrodes on the dielectric and ferroelectric, respectively; (E) forming plate lines connecting the ferroelectric capacitor upper electrodes on a stripe in one direction; And (F) forming bit lines connecting the dielectric capacitor upper electrodes onto a stripe in one direction; Method for producing a ferroelectric memory using a depletion capacity, characterized in that it comprises a. The method of claim 9, In the step (a), the contact plugs on the source and the contact plugs on the drain are simultaneously formed, and in the step (b), the electrode under the dielectric capacitor and the electrode under the ferroelectric capacitor are simultaneously formed. The (c) step, (C-1) the step of forming the ferroelectric on the dielectric capacitor lower electrodes and the ferroelectric capacitor lower electrodes at the same time; And (C-2) a sub-step of forming a dielectric by injecting a dopant into the ferroelectric formed on the lower electrodes of the dielectric capacitor; Method for producing a ferroelectric memory using a depletion capacity, characterized in that it comprises a. The method of claim 9, In the step (a), the thicknesses of the contact plugs on the drain and the contact plugs on the drain are different from each other, and in the step (c), the thicknesses of the dielectric and the ferroelectric are formed equal to or different from each other. Method of manufacturing ferroelectric memory using depletion capacity. The method of claim 9, In step (a), only the contact plugs are formed on the source, and in step (b), only the electrode under the ferroelectric capacitor is formed on the contact plug on the source. The (c) step, (C-1) a sub-step of forming the dielectric directly over the drain of the CMOS transistor and simultaneously forming the gate insulating layer using the gate axide forming the insulating layer of the gate; And (C-2) a sub-step of simultaneously forming the upper electrodes of the dielectric capacitor using the same material as the gate; Method for producing a ferroelectric memory using a depletion capacity, characterized in that it comprises a. The method of claim 9, And forming a common dielectric capacitor in the bit line, instead of directly forming the dielectric capacitor on the drain. Semiconductor substrates; CMOS transistors formed on the semiconductor substrate to correspond to each memory cell; Dielectric capacitors formed on the drains of the CMOS transistors; Ferroelectric capacitors formed on the source of the CMOS transistors; Word lines formed to connect gates of the CMOS transistors arranged on a stripe in one direction; Plate lines formed to connect upper electrodes of the ferroelectric capacitor arranged on a stripe in a direction crossing the word lines; And bit lines formed to connect upper electrodes of the dielectric capacitor arranged on the stripe in a direction parallel to the plate lines. (A) applying a voltage to the word line to address a memory cell; (B) writing information by applying a potential difference between the bit line and the plate line; And (C) reading information through a sense amplifier connected to the bit line; Method of operating a ferroelectric memory using a depletion capacity, characterized in that it comprises a. The method of claim 14, After reading '0', a re-lashing step of rewriting '0' to maintain the '0' memory state more securely. Method of operating a ferroelectric memory using a depletion capacity characterized in that it further comprises.