KR100311047B1 - Copper wiring layer using aluminium pillar in semiconductor device and formation method thereof - Google Patents

Abstract

The copper wiring layer of the semiconductor device of the present invention is a first interlayer insulating film formed on a base layer and having a first trench formed near the surface, a first copper wiring layer filling the first trench, and a first copper wiring layer sequentially It includes an etch stop pattern and aluminum pillar formed. In addition, a diffusion and anti-oxidation film formed on only the first copper wiring layer and not on both sidewalls of the aluminum pillar, and a second trench formed on the diffusion and anti-oxidation film and the aluminum pillar and exposing an upper portion of the aluminum pillar And a second interlayer insulating film formed thereon and a second copper wiring layer filling the second trench. The diffusion and anti-oxidation layer may be formed using high density plasma chemical vapor deposition (HDP CVD) in which deposition and etching are performed in situ. In the semiconductor device of the present invention, the diffusion and the anti-oxidation film do not remain between the aluminum pillars, thereby reducing the capacitance of the capacitor present between the aluminum pillars, thereby reducing the RC delay time.

Description

Copper wiring layer using aluminum pillar in semiconductor device and formation method

The present invention relates to a copper wiring layer of a semiconductor device and a method of forming the same, and more particularly, to a copper wiring layer of a semiconductor device employing an aluminum pillar and a method of forming the same.

In general, a method of using a copper metal as a wiring layer, which has a low specific resistance and can improve EM (electromigration) characteristics, focusing on a logic device requiring a high speed among semiconductor devices. However, when the wiring layer is formed using the copper metal, due to the difficulty of etching the copper metal due to the corrosion of the copper metal, a so-called 'dual damascene' process is used to simultaneously form a buried contact hole and a copper wiring layer. To form a copper wiring layer. However, in the dual damascene process, reactive ion etching for forming fine and large aspect ratio via holes, cleaning of via holes to reduce via resistance, and embedding of copper wiring layers in via holes having high aspect ratios reduce wiring width and via holes. It became very difficult along. Accordingly, it has been proposed to form a copper wiring layer using aluminum pillars.

1 to 4 are cross-sectional views illustrating a method for forming a copper wiring layer of a semiconductor device using a conventional aluminum pillar.

Referring to FIG. 1, after forming a first interlayer insulating layer 3 on a base layer 1, a first trench 4 is formed in the first interlayer insulating layer 3 using a photolithography process. Subsequently, a copper film is formed on the entire surface of the base layer 1 on which the first trench 4 is formed, followed by chemical mechanical polishing to form a first copper wiring layer 5 in the first trench 4.

Referring to FIG. 2, an etch stop film 7 and an aluminum layer 9 are formed on the entire surface of the base layer 1 on which the first copper wiring layer 5 is formed. The etch stop layer 7 is formed of a double layer of a tungsten film W and a tungsten nitride film WN _x . The etch stop layer 7 serves as an etch stop during etching of the aluminum layer in a subsequent process, and also serves as a diffusion barrier between the aluminum pillar and the first copper wiring layer 5 formed later. Next, a hard mask pattern 11 for patterning the aluminum layer 9 is formed on the aluminum layer 9. The hard mask pattern 11 is formed of a silicon nitride film using chemical vapor deposition.

Referring to FIG. 3, the aluminum layer 9 and the etch stop layer 7 are etched using the hard mask pattern 11 to form an aluminum pillar 9a and an etch stop pattern 7a. The etch stop pattern 7a remains only under the aluminum pillar 9a.

Subsequently, a diffusion and anti-oxidation layer 13 is formed on the entire surface of the resultant product on which the hard mask pattern 11, the aluminum pillar 9a, and the etch stop pattern 7a are formed. In this case, the diffusion and anti-oxidation layer 13 may be formed on the first interlayer insulating layer 3 and the first copper wiring layer 5 while surrounding the hard mask pattern 11, the aluminum pillar 9a, and the etch stop pattern 7a. Is formed. The diffusion and anti-oxidation film 13 is formed of a silicon nitride film to prevent the copper of the first copper wiring layer 5 from diffusing into the interlayer insulating film or the like and to prevent the oxidation of the first copper wiring layer 5.

Referring to FIG. 4, the second interlayer insulating layer 15 is formed to have a sufficient thickness on the entire surface of the resultant film on which the diffusion and antioxidant layer 13, the hard mask pattern 11, the aluminum pillar 9a, and the etch stop pattern 7a are formed. Form. Subsequently, a second trench 17 exposing an upper portion of the aluminum pillar 9a is formed. In this case, the diffusion and antioxidant layer 13 on the hard mask pattern 11 is etched to form the diffusion and antioxidant layer pattern 13a, and the hard mask pattern 11 is removed. As a result, the diffusion and anti-oxidation film pattern 13a remains on both side walls of the aluminum pillar 9a. Subsequently, a copper layer is formed on the entire surface of the resultant in which the second trenches 17 are formed, followed by chemical mechanical polishing to form a second copper interconnect layer 19 in the second trenches 17.

By the way, according to the conventional copper wiring layer formation method of the semiconductor element which employ | adopted the aluminum pillar 9a, the silicon nitride film which is the said diffusion and antioxidant film pattern 13a is not removed but remains between aluminum pillars 9a. When the silicon nitride film having a dielectric constant of about 7.5 is present between the aluminum pillars 9a, the effective dielectric constant of the entire interlayer insulating film is increased to greatly increase the RC delay time of the semiconductor device. In other words, as shown by reference numeral 18 of FIG. 4, the effective dielectric constant of the capacitor existing between the aluminum pillars 9a is increased to greatly increase the RC delay time of the semiconductor device. Moreover, this increase in RC delay time becomes more severe as semiconductor devices are integrated.

Therefore, the technical problem to be achieved by the present invention is to provide a copper wiring layer of a semiconductor device that can reduce the RC delay time by solving the above problems when employing an aluminum pillar.

Another object of the present invention is to provide a method for forming a copper wiring layer of the semiconductor device.

1 to 4 are cross-sectional views illustrating a method for forming a copper wiring layer of a semiconductor device using a conventional aluminum pillar.

5 is a cross-sectional view for explaining a copper wiring layer of a semiconductor device employing an aluminum pillar according to the present invention.

6 to 12 are cross-sectional views illustrating a method for forming a copper wiring layer of the semiconductor device of the present invention illustrated in FIG. 5.

In order to achieve the above technical problem, the copper wiring layer of the semiconductor device of the present invention is formed on the base layer and the first interlayer insulating film having a first trench formed in the vicinity of the surface, the first copper wiring layer to fill the first trench, An etching stop pattern and an aluminum pillar sequentially formed on the first copper wiring layer are included. In addition, a diffusion and anti-oxidation film formed on only the first copper wiring layer and not on both sidewalls of the aluminum pillar, and a second trench formed on the diffusion and anti-oxidation film and the aluminum pillar and exposing an upper portion of the aluminum pillar And a second interlayer insulating film formed thereon and a second copper wiring layer filling the second trench.

A first barrier metal pattern and a second barrier metal pattern may be further formed on the bottom and sidewalls of the first trench and the second trench, respectively. The aluminum pillar may further include a copper metal. The diffusion and anti-oxidation layer may be formed using high density plasma chemical vapor deposition (HDP CVD) in which deposition and etching are performed in situ.

In order to achieve the above another technical problem, the method for forming a copper wiring layer of the semiconductor device of the present invention is to form a first interlayer insulating film having a first trench on the underlying layer, and then to form a first copper wiring layer filling the first trench. Forming a step. Subsequently, an etch stop pattern and an aluminum pillar are sequentially formed on the first copper interconnection layer, and then a diffusion and anti-oxidation layer is formed on the upper surface of the aluminum pillar and the first copper interconnection layer except for both sidewalls of the aluminum pillar. After forming a second interlayer insulating film having a second trench exposing an upper portion of the aluminum pillar, a second copper wiring layer filling the second trench is formed.

The method may further include forming a first barrier metal pattern and a second barrier metal pattern on the bottom and sidewalls of the first trench and the second trench, respectively, before forming the first copper interconnection layer and the second copper interconnection layer. have. The aluminum pillar may further include a copper metal. The diffusion and anti-oxidation layer may be formed by high density plasma chemical vapor deposition (HDP CVD) in which deposition and etching are performed in situ.

In addition, a method for forming a copper wiring layer of a semiconductor device according to another example of the present invention includes forming a first interlayer insulating film having a first trench on a base layer. Subsequently, a first barrier metal pattern is formed on both sidewalls and the bottom of the first trench, and a first copper interconnection layer filling the first trench is formed. Next, an etch stop pattern and an aluminum pillar are sequentially formed on the first copper wiring layer. A diffusion and anti-oxidation film is formed on the upper surface of the aluminum pillar, the first copper wiring layer, and the first barrier metal pattern except for both sidewalls of the aluminum pillar. A second interlayer insulating film having a second trench exposing an upper portion of the aluminum pillar is formed. A second barrier metal pattern is formed on both sidewalls and the bottom of the second trench, and a second copper wiring layer is formed on the first barrier metal pattern to fill the second trench.

In the semiconductor device of the present invention described above, the diffusion and the anti-oxidation film do not remain between the aluminum pillars, thereby reducing the capacitance of the capacitor present between the aluminum pillars, thereby reducing the RC delay time.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a cross-sectional view for explaining a copper wiring layer of a semiconductor device employing an aluminum pillar according to the present invention.

Specifically, the first interlayer insulating film 23 is formed on the base layer 21, for example, a semiconductor substrate or a metal layer. The first trench 25 is formed near the surface of the first interlayer insulating film 23. First barrier metal patterns 27a are formed on both sidewalls and bottoms of the first trenches 25. The first barrier metal pattern 27a may be formed of a single film of Ta, Ti, WN, TiN, or TaN, or may be formed of a composite film of Ta and TiN, Ti and TiN, or Ta and TaN. A first copper wiring layer 29a is formed on the first barrier metal pattern 27a to fill the first trench 25.

An etch stop pattern 31a and an aluminum pillar 33a are sequentially formed on the first copper wiring layer 29a. The etch stop pattern 31a is formed of a WN, Ti, TiN, Ta, or TaN film. The etch stop pattern 31a also serves as an etch stop when the aluminum pillar 33a is formed and also serves as a diffusion barrier between the aluminum pillar 33a and the first copper wiring layer 29a. The aluminum pillar 33a may further include a copper metal as needed.

A diffusion and anti-oxidation film 37a is formed on the first copper wiring layer 29a, the first barrier metal pattern 27a, and the first interlayer insulating film 23. The diffusion and antioxidant film 37a is composed of a SiN, SiON, or SiC film. In particular, the diffusion and anti-oxidation film 37a is formed using high density plasma chemical vapor deposition (HDP CVD) in which deposition and etching proceed in situ. It is not formed on both sidewalls. Accordingly, since the capacitance value of the capacitor existing between the aluminum pillars 33a can be reduced, as compared with FIG. 4, the RC delay time of the semiconductor device can be reduced.

A second interlayer insulating film 38 is formed on the diffusion and anti-oxidation film 37a and the aluminum pillar 33a. A second trench 39 exposing an upper portion of the aluminum pillar 33a is formed in the second interlayer insulating layer 38. Second barrier metal patterns 41a are formed on both sidewalls and bottoms of the second trench 39. The second barrier metal pattern 41a may be formed of a single layer of Ta, Ti, WN, TiN, or TaN, or may be formed of a composite film of Ta and TiN, Ti and TiN, or Ta and TaN. A second copper wiring layer 43a is formed on the second barrier metal pattern 41a to fill the second trench 39.

6 to 12 are cross-sectional views illustrating a method for forming a copper wiring layer of the semiconductor device of the present invention illustrated in FIG. 5.

Referring to FIG. 6, a first interlayer insulating film 23, for example, an oxide film, a PSG film, a BPSG film, or the like is formed on a base layer 21, for example, a semiconductor substrate or a metal layer. Subsequently, a first trench 25 is formed in the first interlayer insulating layer 23 using a photolithography process.

Referring to FIG. 7, the first barrier metal film 27 is formed to a thickness of 50 to 800 에 on the entire surface of the base layer 21 on which the first trench 25 is formed. In this case, the first barrier metal layer 27 is formed to cover both sidewalls and the bottom of the first trench 25. The first barrier metal film 27 is formed of a single film of Ta, Ti, WN, TiN, or TaN, or a composite film of Ta and TiN, Ti and TiN, or Ta and TaN. The first barrier metal film 27 is formed to easily form a copper film formed later, and to prevent the copper of the copper wiring layer formed later from diffusing into the first interlayer insulating film 23. Next, the first copper film 29 is formed to have a thickness of 3000 to 20000 kPa, more preferably 5000 kPa or 12000 kPa so as to fill the first trench 25 on the first barrier metal film 27.

Referring to FIG. 8, the first interlayer insulating layer 23 is etched to stop the first copper layer 29 and the first barrier metal layer 27 by a chemical mechanical polishing (CMP) method to form a first trench ( A first copper wiring layer 29a and a first barrier metal pattern 27a filling the 25 are formed. The first barrier metal pattern 27a is formed on both side walls and the bottom of the first trench 25.

Referring to FIG. 9, an etch stop layer 31 is formed on the entire surface of the base layer 21 on which the first copper wiring layer 29a and the first barrier metal pattern 27a are formed. The etch stop layer 31 is formed of WN, Ti, TiN, Ta, or TaN. The etch stop layer 31 serves as an etch stop during etching of the aluminum film in a later process, and also serves as a diffusion barrier between the aluminum pillar and the first copper wiring layer 29a formed later.

Next, an aluminum film 33 is formed on the etch stop film 31. The aluminum film 33 may further include a copper metal as needed. Subsequently, a hard mask pattern 35 is formed on the aluminum layer 33 to correspond to the upper portion of the first copper wiring layer 29a by using a photolithography process. The hard mask pattern 35 uses a photoresist pattern and a film having a high etching selectivity such as SiN, SiC, and SiON. Of course, the photoresist pattern may be used without using the hard mask pattern 35.

Referring to FIG. 10, the aluminum pillar 33a is formed by etching the aluminum layer 33 using the hard mask pattern 35 as an etching mask. In this case, the etch stop layer 31 serves as an etch stop point. Subsequently, the etch stop layer 31 is etched using the hard mask pattern 35 and the aluminum pillar 33 a as an etch mask to form an etch stop pattern 31 a under the aluminum pillar 33 a.

Referring to FIG. 11, the hard mask pattern 35 used as an etching mask is removed in the above process. Next, on the aluminum pillar 33a, the first copper wiring layer 29a, the first barrier metal pattern 27a, and the first interlayer insulating film 23, a diffusion and anti-oxidation film 37 were formed to a thickness of 50 to 500 kPa. Form. The diffusion and prevention film 37 is formed to prevent the copper of the first copper wiring layer 29a from diffusing into the interlayer insulating film or the like and to prevent the oxidation of the first copper wiring layer 29a.

In particular, the diffusion and oxidation prevention film 37 of the present invention is formed using high density plasma chemical vapor deposition (HDP CVD) in which deposition and etching proceed in situ. In the case of using the high-density plasma chemical vapor deposition method, the diffusion and anti-oxidation film 37 is not formed on both side walls of the aluminum pillar 33a differently from the prior art, and the upper surface of the aluminum pillar 33a and the first interlayer insulating film 23 are used. And only the first copper wiring layer 29a and the first barrier metal pattern 27a. In this embodiment, the diffusion and anti-oxidation film 37 is formed of a silicon nitride film (SiN film) by using a mixed gas of SiH ₄ , NH ₃ (or N ₂ ), Ar (or He), a SiON or SiC film It can also be formed.

As described above, in the present invention, the diffusion and anti-oxidation film 37 is not formed on both side walls of the aluminum pillar 33a, thereby reducing the capacitor value generated in the insulating film between the aluminum pillars 33a shown at 45 in FIG. In this way, the RC delay time of the semiconductor device can be reduced.

Referring to FIG. 12, the second interlayer insulating layer 38 is formed to have a sufficient thickness on the entire surface of the resultant layer on which the diffusion and oxidation prevention layer 37, the aluminum pillar 33a, and the etch stop pattern 31a are formed. Subsequently, a second trench 39 exposing an upper portion of the aluminum pillar 33a is formed. At this time, the diffusion and antioxidant film 37 on the aluminum pillar 33a is removed. Subsequently, a second barrier metal film 41 and a second copper layer 43 are formed on the entire surface of the resultant product in which the second trench 39 is formed. The second barrier metal film 41 is formed to have a thickness of 50 to 800 kW using the same material as the first barrier metal film 27. The second copper layer 43 is formed to have a thickness of 3000 to 20000 kPa, more preferably 5000 kPa or 12000 kPa. Subsequently, the second barrier metal film 41 and the second copper layer 43 are chemically mechanically polished to form the second barrier metal pattern 41a and the second copper wiring layer 43a in the second trench 39 as shown in FIG. 5. ) To complete the present invention.

As described above, the semiconductor device of the present invention in which the copper wiring layer is formed without forming the diffusion and antioxidant film 37 on both side walls of the aluminum pillar 33a, and the diffusion and antioxidant film 13a as shown in FIG. Table 1 shows the capacitor values generated in the insulating film between the aluminum pillars 33a between the conventional semiconductor devices formed on both side walls of the N-type and the copper wiring layer.

Condition Capacitance value (pF) When both sides of aluminum pillar have diffusion and anti-oxidation film (conventional) 46 If both sides of the aluminum pillar do not have diffusion and anti-oxidation film (invention) 44

As shown in Table 1, the semiconductor device having the copper wiring layer of the present invention can reduce the RC delay time of the semiconductor device by reducing the capacitance value by about 5 compared with the device having the conventional copper wiring layer. In other words, in the present invention, since the silicon nitride film having an effective refractive index of about 7.5 does not remain between the aluminum pillars 33a, the effective dielectric constant of the insulating film between the aluminum pillars 33a is reduced. Accordingly, the present invention can reduce the capacitance value of the capacitor between the aluminum pillars, as shown by 45 in FIG. Moreover, the reduction of RC delay time according to the present invention becomes more important as semiconductor devices are integrated.

As mentioned above, although this invention was demonstrated concretely through the Example, this invention is not limited to this, A deformation | transformation and improvement are possible with the conventional knowledge in the art within the technical idea of this invention.

As described above, in the semiconductor device of the present invention employing the aluminum pillar and the copper wiring layer, a silicon nitride film, which is a diffusion and antioxidant film, does not remain between the aluminum pillars. Therefore, the semiconductor device of the present invention can reduce the effective dielectric constant of the insulating film between the aluminum pillars to reduce the capacitance value of the capacitor present between the aluminum pillars. As a result, the semiconductor device of the present invention can improve the properties of the product by reducing the RC delay time.

Claims (20)

A first interlayer insulating film formed on the underlying layer and having a first trench formed near the surface thereof; A first copper interconnection layer filling the first trench; An etch stop pattern and an aluminum pillar sequentially formed on the first copper interconnection layer; A diffusion and anti-oxidation film formed only on the first copper wiring layer and not on both sidewalls of the aluminum pillar; A second interlayer insulating layer formed on the diffusion and anti-oxidation layer and the aluminum pillar and having a second trench exposing an upper portion of the aluminum pillar; And And a second copper wiring layer filling the second trench. The copper wiring layer of claim 1, wherein a first barrier metal pattern and a second barrier metal pattern are formed on the bottom and side walls of the first trench and the second trench, respectively. The method of claim 2, wherein the first barrier metal pattern and the second barrier metal pattern are formed of a single film of Ta, Ti, WN, TiN, or TaN, or a composite film of Ta and TiN, Ti and TiN, or Ta and TaN. The copper wiring layer of a semiconductor element characterized by the above-mentioned. The copper wiring layer of a semiconductor device according to claim 1, wherein the aluminum pillar further contains a copper metal. The copper wiring layer of claim 1, wherein the diffusion and oxidation prevention layer is formed by using high density plasma chemical vapor deposition (HDP CVD) in which deposition and etching are performed in situ. The copper wiring layer of a semiconductor device according to claim 1, wherein the diffusion and oxidation prevention film is formed of a SiN, SiON, or SiC film. The copper interconnect layer of claim 1, wherein the etch stop pattern is formed of a WN, Ti, TiN, Ta, or TaN film. Forming a first interlayer insulating film having a first trench on the underlayer; Forming a first copper interconnection layer filling the first trench; Sequentially forming an etch stop pattern and an aluminum pillar on the first copper wiring layer; Forming a diffusion and anti-oxidation film on an upper surface of the aluminum pillar and the first copper interconnection layer except for both sidewalls of the aluminum pillar; Forming a second interlayer insulating film having a second trench that exposes an upper portion of the aluminum pillar; And And forming a second copper wiring layer filling the second trench. The method of claim 8, further comprising: forming a first barrier metal pattern and a second barrier metal pattern on the bottom and sidewalls of the first trench and the second trench, respectively, before forming the first copper wiring layer and the second copper wiring layer. The copper wiring layer forming method of a semiconductor device characterized by further comprising. The method of claim 9, wherein the first barrier metal pattern and the second barrier metal pattern are formed of a single film of Ta, Ti, WN, TiN, or TaN, or a composite film of Ta and TiN, Ti and TiN, or Ta and TaN. The copper wiring layer formation method of a semiconductor element characterized by the above-mentioned. The method for forming a copper wiring layer of a semiconductor device according to claim 8, wherein the aluminum pillar further includes a copper metal. The method of claim 8, wherein the forming of the etch stop pattern and the aluminum pillar comprises: sequentially forming an etch stop layer and an aluminum layer on the first copper interconnection layer, and forming a hard mask pattern on the aluminum layer; And patterning the aluminum layer and the etch stop layer using the hard mask pattern as an etch mask, and removing the hard mask pattern. The method of claim 12, wherein the etch stop layer is formed of a WN, Ti, TiN, Ta, or TaN film. The method for forming a copper wiring layer of a semiconductor device according to claim 12, wherein the hard mask pattern is formed of a SiN, SiON, or SiC film. The method of claim 8, wherein the diffusion and oxidation prevention layer is formed by high density plasma chemical vapor deposition (HDP CVD) in which deposition and etching are performed in situ. The method for forming a copper wiring layer of a semiconductor device according to claim 8, wherein the diffusion and oxidation prevention film is formed of a SiN, SiON, or SiC film. Forming a first interlayer insulating film having a first trench on the underlayer; Forming first barrier metal patterns on both sidewalls and bottoms of the first trenches, and forming a first copper interconnection layer filling the first trenches; Sequentially forming an etch stop pattern and an aluminum pillar on the first copper wiring layer; Forming a diffusion and anti-oxidation film on an upper surface of the aluminum pillar except for both sidewalls of the aluminum pillar, the first copper wiring layer, and the first barrier metal pattern; Forming a second interlayer insulating film having a second trench that exposes an upper portion of the aluminum pillar; And Forming a second barrier metal pattern on both sidewalls and bottoms of the second trench, and forming a second copper wiring layer on the first barrier metal pattern to fill the second trench. Copper wiring layer formation method of an element. The method of claim 17, wherein the first barrier metal pattern and the second barrier metal pattern are formed of a single layer of Ta, Ti, WN, TiN, or TaN, or a composite layer of Ta and TiN, Ti and TiN, or Ta and TaN. The copper wiring layer formation method of a semiconductor element characterized by the above-mentioned. 18. The method of claim 17, wherein the diffusion and anti-oxidation film is formed using high density plasma chemical vapor deposition (HDP CVD) in which deposition and etching proceed in situ. The method for forming a copper wiring layer of a semiconductor device according to claim 17, wherein the diffusion and oxidation prevention film is formed of a SiN, SiON, or SiC film.