KR100324817B1 - Semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, in which two linear device isolation layers are implemented in a cell unit in order to increase cell capacity in the same area, maintain a folded bit line structure, and share sense amplification. In order to maintain a sense amplified structure, one cell unit is alternately arranged, and one memory unit is used as a bit line and a bit line bar by one of each cell unit.

Description

Semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a memory device in which a cell unit is formed in two units having a straight cell shape to increase a cell area to increase cell capacity per same area, thereby manufacturing a highly integrated device. It is about.

In general, a memory device includes a volatile device that can be input and erased, such as a DRAM device, and the DRAM device has a structure in which one capacitor is connected to one transistor.

Such DRAM devices have a smaller area occupied by transistors and capacitors as semiconductor devices are highly integrated, but the capacitors must be able to store a predetermined capacity. Meanwhile, various layouts have been developed to improve the high integration of the DRAM.

In case of 64M DRAM, there is one cell unit using Z-cell.

As (Shrink) or higher integration, cell capacity decreases, and device characteristics deteriorate, and as the line width becomes finer, the operation speed may decrease.

In order to solve the above problems, the present invention implements two straight device isolation layers in a cell unit to increase cell capacity in the same area, maintains a folded bit line structure, and shares sense amplification (Shared). In order to maintain the structure (Sense Amplified), the purpose of the present invention is to provide a memory device in which one cell unit is arranged alternately and one bit line and one bit line are used in each cell unit.

1 is a view showing a layout of a memory device manufactured by the prior art.

2 is a layout view of a memory device in accordance with an embodiment of the present invention.

3 shows a circuit of a memory device provided by the present invention.

4 is a cross-sectional view taken along the line II of FIG. 2.

<Description of Symbols for Major Parts of Drawings>

1,11,12 active area 35 interlayer insulating film

2,13: Word line 3,14,36: Bit line

4,16,18 contact 15,37 bit line bar

31 semiconductor substrate 32 device isolation film

33: source / drain region 34: P-region

The present invention for achieving the above object is a memory device,

Word lines extending in a vertical direction and spaced apart at regular intervals,

A pair of active regions formed in a rectangular shape over the pair of word lines and spaced apart by a predetermined interval up and down;

A bit line and a bit line bar extending in a horizontal direction in spaced spaces between the pair of active regions;

In order to contact the bit line and the bit line bar to the source / drain common area of the active area, the contact areas of the bit line and the bit line bar protrude to the active area and overlap each other.

Gates of two transistors are connected to each of the word lines, a drain of the one transistor is connected to a bit line, and a drain of the other transistor is connected to a bit line bar.

Transistors having a symmetrical structure are formed in the active region, and the pair of active regions have a transistor having a vertically symmetrical structure.

A sense amplifier S / A is connected to the bit line and the bit line bar arranged one space apart from the bit line.

According to the present invention as described above, the cell capacity is reduced toward higher integration to prevent device characteristics from deteriorating, and as the line width becomes finer, the operation speed can be solved.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a view illustrating a layout of a memory device manufactured according to the prior art, in which a word line 2 provided at a predetermined interval in the vertical direction and a bit line 3 provided at a predetermined interval in the horizontal direction are provided. It is provided so that the contact region overlaps the active region 1 so as to contact the cathode / drain common region 4 of the active region 1 which is provided but is spaced apart at regular intervals in the longitudinal and transverse directions in the form of a rectangle. . However, this structure has a limitation in increasing cell capacity as the cell area decreases as the device is highly integrated.

2 is a layout view of a memory device according to an exemplary embodiment of the present invention, wherein the word lines 13 are spaced apart at regular intervals in a vertical direction and a pair of spaced apart at regular intervals in a vertical direction in a rectangular shape. A pair of bit lines 14 and a bit line bar 15 provided in a horizontal direction between the active regions 11 and 12 and the pair of active regions 11 and 12 are disposed, and the bit lines 14 are disposed. And the contact areas of the bit line 14 and the bit line bar 15 are connected to the active area 11, in order to contact the bit line bar 15 with the source / drain common areas of the active 11 and 12. 12) is provided so as to overlap and protrude.

That is, the present invention is arranged so that a pair of active regions are arranged adjacent to each other, and the bit lines and the bit line bars are contacted to the active regions, respectively.

3 shows a circuit of a memory device according to the present invention, in which word lines ML0, WL1..., Bit lines, and bit line bars are repeatedly arranged in a horizontal direction, and a pair of transistors are provided in word line ML0. Gates of Q1 and Q2 are connected, drains of the pair of transistors Q1 and Q2 are respectively connected to bit lines and bit line bars, and a pair of transistors Q3 and Q4 are respectively connected to word lines ML1. A gate is connected and drains of the pair of transistors Q3 and Q4 are connected to the bit line and the bit line bar, respectively.

A sense amplifier S / A is connected to the bit line and the bit line bar arranged one space apart from the bit line, and another sense amplifier S / A is connected to a bit line spaced one space apart from the bit line bar adjacent to the bit line. ) Is connected.

4 is a cross-sectional view taken along the line I-I of FIG. 2, showing the structure of a memory device manufactured by the present invention on a semiconductor substrate. In other words, the device isolation layer 32 is manufactured in the region excluding the active region of the P-type semiconductor substrate 31, and then N-type impurities are implanted into the active region to form the N + source / drain region 33. For reference, the P-impurity region 34 may be formed at the edge of the source / drain region 33 to improve device isolation.

After forming the interlayer insulating film 35 as a whole, the bit line 36 and the bit line bar 37 are formed thereon.

According to the present invention, two linear device isolation layers are implemented in the cell unit in order to increase cell capacity in the same area, and maintain a folded bit line structure and a shared sense amplified structure. In order to maintain, the cell capacity per same area is increased by using bit line and bit line one by one in each cell unit, and the characteristics of the device shrink and highly integrated device are increased. Can be improved.

Although the present invention described above is not shown in the above embodiments, various modifications are possible within the claims of the present invention, and such changes are considered to be included in the scope of the present invention.

Claims (5)

In the memory device, Word lines extending in a vertical direction and spaced apart at regular intervals, A pair is formed in a rectangular shape over the pair of the word line, spaced up and down spaced apart by a predetermined interval, the impurity region for reducing the electric field at the boundary with the device isolation film by ion implantation of the same type of impurities Active area, A bit line and a bit line bar extending in a horizontal direction in spaced spaces between the pair of active regions; And a contact region of the bit line and the bit line bar protrudes into the active region and overlaps the bit line and the bit line bar to contact the source / drain common region of the active region. The method of claim 1, A gate of two transistors is connected to each of the word lines, a drain of the one transistor is connected to a bit line, and a drain of the other transistor is connected to a bit line bar. The method of claim 1, And the transistor having a symmetrical structure is formed in the one active region. The method of claim 1, And wherein the pair of active regions have a vertically symmetrical transistor structure. The method of claim 1, And a sense amplifier (S / A) is connected to the bit line and the bit line bar arranged every other space with the bit line.