KR100323238B1 - Method of measuring overlapping length and overlapping capacity in MOSFET and apparatus for measuring the same - Google Patents

Abstract

The overlapping length is defined as the length of the overlapping region measured in the longitudinal direction of the gate, and the overlapping region is defined as the region overlapping with the diffusion region where the gate becomes the source or drain, and the device for accurately measuring the overlapping length of the MOSFET The apparatus of claim 1, wherein the apparatus is configured to electrically measure the current flowing between the gate and the source / drain of each MOSFET having a different gate length and the voltage applied between the gate and the source / drain, A plurality of Cgc-Vg characteristics are determined based on the measurement result, and a gate voltage Vx whose gate voltage depends on the gate length Lg is determined based on the Cgc-Vg characteristics, and at the gate voltage Vx The Cgc-Lg characteristic is determined by determining the capacitance (Cx) between the gate and the source / drain, and the fringe is based on the intercept of the Cgc axis of the Cgc-Lg characteristic. And a data processor 5 for determining the capacitance Cf and for determining the overlapping length DELTA L based on the fact that Cgc becomes equal to Cx in the Cgc-Lg characteristic.

Description

Method of measuring overlapping length and overlapping capacity in MOSFET and apparatus for measuring the same}

The present invention relates to a method for measuring overlapping length and overlapping capacity, an apparatus for performing the same, and a recording medium readable by a computer and storing a program therein so that the computer performs the method or functions as the device. Here, the overlapping length is defined as the length of the overlapping region measured in the longitudinal direction of the gate of the MOSFET, and the overlapping capacitance is defined as the capacitance formed in the overlapping region between the gate and the diffusion region serving as the source or drain region of the MOSFET. The overlapping region is defined as the region where the gate overlaps with the diffusion region.

The overlapping length and overlapping capacity are important device parameters in performing circuit simulation of the MOSFET.

One method of measuring the overlapping length of a MOSFET is disclosed in IEEE 1995, International Conference on Microelectronic Test Structure, Vol / 8 March 1995, pp. 151-155.

First, as shown in Figs. 1A and 1B, two devices having the same total gate area are provided.

1A shows a MOSFET 50 having a p-type substrate 51, a plurality of gates 52a, 52b, 52c formed on the p-type substrate 51, and a diffusion region 53 serving as a source or a drain, respectively. Indicates. The terminal 100 is electrically connected to all the gates 52a, 52b, 52c, and the terminal 102 is electrically connected to the substrate 51.

1B shows a MOS capacitor 60 having a p-type substrate 61 and a single gate 62 formed on the p-type substrate 61. The terminal 200 is electrically connected to the gate 62, and the terminal 202 is electrically connected to the substrate 61.

The capacitance Cgb between the gates 52a, 52b, 52c and the substrate 51 is measured by changing the gate voltage Vg applied between the terminals 100, 102 of the MOSFET 50 shown in FIG. 1A. Similarly, the capacitance Cp between the gate 62 and the substrate 61 is measured by changing the gate voltage Vg applied between the terminals 200 and 202 of the MOS capacitor 60.

This measurement result is shown in FIG.

Next, the capacitance Cgb formed between the gates 52a, 52b, 52c of the MOSFET 50 and the substrate 51 and the capacitance Cp formed between the gate 62 and the substrate 61 of the MOSFET 60 are next formed. The difference Cdiff is calculated. (Cdiff = Cgb-Cp) Next, at the point where the peak occurs in the (Cgb-Cp) curve, the capacitance Cdiff is determined.

Next, the overlapping length Δ of the MOSFET 50 is calculated according to Equations 1 and 2 below based on the determined capacitance Cdiff. Here, the overlapping length is defined as the length of the overlapping region measured in the longitudinal direction of the gate 52a (or 52b, 52c) in the MOSFET 50, and the overlapping region is each gate overlapping the diffusion region 53. It is defined as an area of (52a, 52b, 52c).

ΔL = Cdiff × Lp / (Cp × Nf)

Lp = Nf / L

In Equations 1 and 2, Lp represents the gate length of the MOS capacitor 60, Nf represents the gate number of the MOSFET 50, and L represents the gate length of the MOSFET 50.

However, in the aforementioned overlapping length measuring method of the MOSFET, there is a problem that the total gate pattern areas of the devices shown in Figs. 1A and 1B are not always the same with respect to each other depending on the lithography conditions in the lithography step. That is, an error may occur between the entire areas of the devices. As a result, when the peak does not occur in the above-mentioned (Cgb-Cp) curve, the overlapping length ΔL cannot be determined. This is due to quantum effects or gate depletion due to poor precision resulting from extracting the overlapping capacity based on the shape difference of the devices and calculating the overlapping length ΔL according to the extracted overlapping capacity (Cgb-Cp). This is because the peak may not appear in the curve.

In view of the above-mentioned problems in the prior art, an object of the present invention is to provide a method for accurately measuring the overlapping length and overlapping capacity of a MOSFET, an apparatus capable of performing the same, and a program readable by a computer therein. A storage medium is provided that allows a computer to perform this method or act as a device.

1A is a cross-sectional view of an apparatus used when the overlapping length is measured according to a conventional overlapping length measuring method.

1B is a cross-sectional view of another apparatus used when the overlapping length is measured according to a conventional overlapping length measuring method.

FIG. 2 is a graph showing the relationship between the capacitance and the gate voltage formed between the gate and the substrate in each of the devices shown in FIGS. 1A and 1B.

3 is a block diagram of an apparatus for measuring overlapping length and overlapping capacity of a MOSFET according to a first embodiment of the present invention.

4 is a circuit diagram of the apparatus shown in FIG. 3.

FIG. 5 is a flowchart of steps performed by a data processor that is part of the apparatus shown in FIG. 3.

FIG. 6 is a graph showing a relationship between a capacitor Cgc and a gate voltage Vg formed between a gate and a source / drain obtained by performing MOSFET measurements with the apparatus shown in FIG. 3.

FIG. 7 is a graph showing a relationship between a gate voltage Vg and a capacitance Cgc formed across a gate and a source / drain obtained by performing a MOSFET measurement with the apparatus shown in FIG. 3.

FIG. 8 is a graph showing the difference between the capacitor Cgc and the gate voltage Vg shown in FIG. 7.

9 is a graph showing the relationship between dCgc / dVg and gate voltage Vg obtained based on the Cgc-Vg characteristic.

FIG. 10 is a graph illustrating a relationship between δCgc / δVg and the gate voltage Vg shown in FIG. 7.

Fig. 11 is a graph showing the relationship between the gate length Lg of the MOSFET and the capacitance formed between the gate and the source / drain.

FIG. 12 is a graph showing a relationship between a gate length Lg of a MOSFET obtained in consideration of the Cgc-Vg characteristic shown in FIG. 7 and a capacitance formed between a gate and a source / drain.

13 is a flowchart of steps performed by a data processor that is part of an apparatus for measuring the overlapping length and overlapping capacity of a MOSFET, according to a second embodiment of the present invention.

FIG. 14 is a graph showing the relationship between the capacitance Cgc and the gate voltage Vg formed between the gate and the source / drain obtained by measuring the MOSFET with the device according to the second embodiment of the present invention.

FIG. 15 is a graph showing a relationship between δ (δCgc / δVg) / δLg and the gate voltage Vg obtained in consideration of the dCgc / dVg-Vg characteristic shown in FIG. 9.

FIG. 16 is a graph showing the relationship between δ (δCgc / δVg) / δLg and the gate voltage Vg obtained in consideration of the Cgc / Vg characteristic shown in FIG. 14.

FIG. 17 is a graph showing the relationship between the MOSFET characteristic having the largest gate length and the MOSFET characteristic having the smallest gate length among the δ (δCgc / δVg) / δLg-Vg characteristics shown in FIG.

18 is a graph showing the relationship between the capacitance Cgc and the gate length Lg formed between the gate and the source / drain of the MOSFET.

FIG. 19 is a graph showing a relationship between a gate length Lg and a capacitance formed between a gate and a source / drain of a MOSFET obtained based on the Cgc-Vg characteristic shown in FIG.

20 is a circuit diagram of an apparatus for measuring the overlapping length of a MOSFET, according to a third embodiment of the present invention.

Fig. 21A is a sectional view of a MOS capacitor.

Fig. 21B is a sectional view of the MOS capacitor formed on the diffusion layer.

FIG. 22 is a flowchart of steps performed by a data processor that is part of an apparatus for measuring the overlapping length of a MOSFET in accordance with a third embodiment of the present invention.

Fig. 23 is a graph showing the C-V characteristics of a MOS capacitor.

24 is a graph obtained by plotting the capacitance C _GSUB formed between the gate and the substrate of the MOSFET measured by the overlapping length measuring apparatus with respect to (Vbi-V _SUB ) ^1/2 according to the third embodiment of the present invention.

Fig. 25 is a plan view illustrating a depletion layer formed between a source / drain of a MOSFET and a substrate when the overlapping length is measured by the apparatus according to the third embodiment of the present invention.

FIG. 26 is a flowchart of steps performed by a data processor that is part of an apparatus for measuring the overlapping length of a MOSFET, in accordance with a fourth embodiment of the present invention.

FIG. 27 is a graph obtained by plotting the capacitance C _GSUB formed between the gate and the substrate of the MOSFET measured by the overlapping length measuring apparatus with respect to (Vbi-V _SUB ) ^1/2 according to the fourth embodiment of the present invention. .

Fig. 28 is a plan view illustrating a depletion layer formed between a source / drain of a MOSFET and a substrate when the overlapping length is measured by the apparatus according to the fourth embodiment of the present invention.

※ Explanation of symbols for main parts of drawing

1: MOSFET 2: Measuring device

3: input device 4: recording medium

5: Data Processor 6: Memory

7: output device 21, 21a: element mounting

22,22a: Measuring part 40,41: MOS capacitor

221: variable DC bias voltage source 222: AC voltage source

223 voltmeter 224 ammeter

According to one aspect of the invention, the overlapping length is defined as the length of the overlapping region measured in the longitudinal direction of the gate, and the overlapping capacitance is defined as the capacitance formed in the overlapping region between the gate and the diffusion region which becomes the source or drain region. The overlapping region is defined as a region in which the gate overlaps with the diffusion region, wherein the overlapping length of the MOSFET and the overlapping capacitance measuring method include: (a) gates and sources of a plurality of MOSFETs having different gate lengths; Applying a DC bias voltage (Vg) and an AC voltage between the drains, and varying the DC bias voltage (Vg) as a gate voltage to measure the current flowing between the gate and the source or drain, and the result of the current measurement Based on the capacitance C formed between the gate and the source or drain, respectively. determining a plurality of Cgc-Vg characteristics representing a relationship between gc) and a gate voltage Vg; and (b) among the gate voltages Vg, for the gate length Lg in the Cgc-Vg characteristics. Determine the gate voltage Vx in which the dependence of the gate voltage Vg appears, and determine the same capacitance Cx as the capacitance Cgc associated with the gate voltage Vx based on the Cgc-Vg characteristics. And (c) determining the capacitance Cgc associated with the gate length Lg at the gate voltage Vg at which the capacitance Cgc is saturated based on the Cgc-Vg characteristics, and determining the determined capacity. Plotting the capacity Cgc to determine the Cgc-Lg characteristic, (d) determining the fringe capacity Cf based on the intercept on the Cgc axis of the Cgc-Lg characteristic, and (e) the fringe Based on the capacitance Cf, the overlap of the MOSFET having the step of determining the overlapping length ΔL and the overlapping capacitance Cov The length and the overlap capacitance measuring method is provided.

In the above method, the capacitance Cx in the capacitance Cgc formed between the gate and the source / drain is based on the branching point where the dependency of the capacitance Cgc on the gate length Lg in the plurality of Cgc-Vg characteristics is shown. Is determined. Therefore, it is possible to accurately determine the overlapping length DELTA L even in a short channel MOSFET. In addition, it is possible to obtain the overlapping capacity Cov and the fringe capacity.

In the method, step (b) calculates a difference between two capacitances Cgc associated with two gate lengths Lm, Ln (m ≠ n) in the Cgc-Vg characteristics, and calculates the Cgc- The gate voltage Vx in which the dependence of the gate voltage on the gate length Lg in the Vg characteristics is defined as the gate voltage Vg in which the difference maximizes a constant ratio, and is based on the Cgc-Vg characteristics. Therefore, the method may be replaced by determining the same capacitance Cx as the capacitance Cgc associated with the gate voltage Vx.

In the above method, step (b) comprises: (b1) determining a plurality of [(δCgc / δVg) -Vg] characteristics representing a relationship between (δCgc / δVg) and a gate voltage (Vg), Branch points are determined in the [(δCgc / δVg) -Vg] characteristic as the respective gate voltages Vx in which the dependence of the gate voltage on the gate length Lg in the Cgc-Vg characteristics is shown, and the Cgc-Vg Based on the characteristics, it may be replaced by the step (b2) of determining the capacitance Cx equal to the capacitance Cgc associated with the gate voltage Vx.

In the above method, step (b) provides a plurality of [δ (δCgc / δVg) / δLg-Vg] characteristics indicating a relationship between (δ (δCgc / δVg) / δLg) and gate voltage Vg, respectively. The step (b1) of determining and as the respective gate voltages Vx exhibiting the dependence of the gate voltage on the gate length Lg in the Cgc-Vg characteristics [δ (δCgc / δVg) / δLg-Vg]. The branching points may be determined in the characteristic, and based on the Cgc-Vg characteristics, the method may be replaced by the step (b2) of determining the same capacitance Cx as the capacitance Cgc associated with the gate voltage Vx.

In the above method, step (b) provides a plurality of [δ (δCgc / δVg) / δLg-Vg] characteristics indicating a relationship between (δ (δCgc / δVg) / δLg) and gate voltage Vg, respectively. In the step (b1) of determining and in the Cgc-Vg characteristics, a peak is generated in each of the [δ (δCgc / δVg) / δLg-Vg] characteristics of the equation [Vx = Vp−k × Vw]. The gate voltage is shown, and Vw represents the half value width in each of the above [δ (δCgc / δVg) / δLg-Vg] characteristics, and k is the gate length according to a constant (1.0 <k <1.5) in the range of 1.0 to 1.5. Calculate a gate voltage Vx in which the dependence of the gate voltage on Lg appears, and based on the Cgc-Vg characteristics, the capacitance Cx equal to the capacitance Cgc associated with the gate voltage Vx. It may be replaced by step (b2) to determine.

In the above alternatives, the capacitance Cx in the capacitance Cgc formed between the gate and the source / drain is based on the branching point where the dependence of the capacitance Cgc on the gate length Lg in the plurality of Cgc-Vg characteristics is shown. This is determined. Therefore, it is possible to accurately determine the overlapping length DELTA L even in a short channel MOSFET. In addition, it is possible to obtain the overlapping capacity Cov and the fringe capacity.

In addition, the overlapping length is defined as the length of the overlapping region measured in the longitudinal direction of the gate, and the overlapping region is defined as an overlapping region with the diffusion region in which the gate becomes a source or a drain. (A) CV characteristic which shows the relationship between DC bias voltage Vg and capacitance C applied between the gate electrode which has a MOS capacitor pattern, and a board | substrate is determined, and based on the CV characteristic, the DC bias voltage is determined. Determining a flat band capacitance C _FB per unit area of the gate electrode at a point where Vg becomes equal to the flat band voltage V _FB , and (b) the same overlapping length L _SD and the same gate. Applying a DC bias voltage (V _SUB ) to a substrate of a plurality of MOSFETs having a width (W) and different gate lengths (Lg), the DC bias voltage between the gate and the source or drain. (Vg), DC bias voltage (V _SUB ), and AC voltage is applied to vary the DC bias voltage (V _SUB ) while the gate voltage (Vg) is at V _SUB + V _FB to the gate and the substrate. Measuring the formed capacitance C _GSUB , (c) determining the built-in potential Vbi between the substrate and the source or drain, and (d) for (Vbi-V _SUB ) ^1/2 Determining the overlapping length L _SD based on the C _FB × (Lg-2L _SD ) intercept on the C _GSUB axis in the regression line obtained by plotting the capacitance C _GSUB . An overlapping length measuring method is provided.

According to the method described above, the DC bias voltage V _SUB applied to the substrate is measured in the forward direction until the source or drain is forward biased. As a result, the capacitance can be measured without being affected by the depletion layer formed between the source / drain and the substrate, and therefore, the PN junction position located between the substrate and the source / drain can be evaluated with high accuracy.

In addition, since the bias voltage is determined (Vg = V _SUB + V _FB ) so that the energy band of the region where the MOSFET capacitance is measured is flat, the depletion layer formed between the source / drain and the substrate is distributed in parallel to the PN junction. As a result, disturbance to the positioning of the PN junction is reduced. Thus, it is possible to determine the overlapping length close to the metallurgical overlapping length.

In addition, since the bias voltage is determined (Vg = V _SUB + V _FB ) so that the energy band of the region where the MOSFET capacitance is measured is flat, the depletion layer formed between the source / drain and the substrate is distributed in parallel to the PN junction. As a result, disturbance to the positioning of the PN junction is reduced. Thus, it is possible to determine the overlapping length close to the metallurgical overlapping length.

In addition, the overlapping length is defined as the length of the overlapping region measured in the longitudinal direction of the gate, and the overlapping region is defined as an overlapping region with the diffusion region in which the gate becomes a source or a drain. (A) determining a CV characteristic showing a relationship between a DC bias voltage Vg and a capacitor C applied between a gate electrode formed on the diffusion layer having the diffusion layer and a MOS capacitor pattern, and based on the CV characteristic. Determining the flat band capacitance C _FB per unit area of the gate electrode at a point where the DC bias voltage Vg becomes equal to the flat band voltage V _FB , and (b) the same overlapping length ( L _SD), the same gate width (W), and another DC bias voltage (Vg in each of the gate and the source or drain of the MOSFET having a plurality of different gate length (Lg)) Applying an AC voltage and varying the DC bias voltage (Vg) as a gate voltage, measuring the current flowing between the gate and the source or drain, and based on the current measurement results, respectively, the gate and the source or Determining a plurality of Cgc-Vg characteristics representing a relationship between the capacitance Cgc and the gate voltage Vg formed between the drains, and (c) in the Cgc-Vg characteristics, the capacitance Cgc is saturated. Determining a capacitance (Cgc) associated with the gate length (Lg) at a gate voltage (Vg), and plotting the determined capacitance (Cgc) to determine a Cgc-Lg characteristic, and (d) the Cgc-Lg characteristic Determining a gate fringe capacitance (C _FL ) based on the intercept on the Cgc axis of (e) and (e) varying the DC bias voltage (V _SUB ) applied to the substrates of the respective MOSFETs. The capacity (Cgc) measured at zero (Vg = 0) And determining a capacitance (C _GSD) are respectively defined, (f) determining a built-in potential (Vbi) between the substrate and the source or the drain, and (g) the capacitor (C _GSD) (Vbi- V _SUB) to about ^1/2 the floating _{(C GSD - (Vbi-V} SUB) 1/2) determine the characteristics, and the capacity (at least the said (C _GSD of _{C GSD) - (Vbi-V} SUB) 1 ^{/ 2} ) determining the overlapping length (L _SD ) based on (C _FB × L _SD × W + 2C _FL ) in the characteristic is provided.

According to the method, the DC bias voltage V _SUB applied to the substrate is measured in the forward direction until the MOSFET is turned on. As a result, the capacitance can be measured without being affected by the depletion layer formed between the source / drain and the substrate, and the PN junction position located between the substrate and the source / drain can be evaluated with high accuracy.

In addition, since the bias voltage is determined (Vg = 0V) so that the energy band of the region where the MOSFET capacitance is measured is flat (Vg = 0V), the depletion layer formed between the source / drain and the substrate is distributed in parallel to the PN junction, and as a result, Disturbance to the positioning of the PN junction is reduced. Thus, it is possible to determine the overlapping length close to the metallurgical overlapping length.

According to another aspect of the invention, the overlapping length is defined as the length of the overlapping region measured in the longitudinal direction of the gate, and the overlapping capacitance is a capacitance formed in the overlapping region between the gate and the diffusion region which becomes the source or drain region. Wherein the overlapping region is defined as a region in which the gate overlaps with the diffusion region, wherein the overlapping length of the MOSFET and the overlapping capacitance measuring device are (a) gates of a plurality of MOSFETs having different gate lengths; A measuring device for applying a DC bias voltage (Vg) and an AC voltage between the source or the drain, and varying the DC bias voltage (Vg) as a gate voltage to measure a current flowing between the gate and the source or drain, and (b1) the gate and the source, respectively, based on the result of the current measurement; Or determining a plurality of Cgc-Vg characteristics representing a relationship between the capacitor Cgc and the gate voltage Vg formed between the drains, and (b2) among the Cgc-Vg characteristics among the gate voltages Vg. Determine a gate voltage Vx in which the dependence of the gate voltage Vg on the gate length Lg appears, and based on the Cgc-Vg characteristics, the capacitance Cgc associated with the gate voltage Vx is determined. A function Cgc associated with the gate length Lg at a gate voltage Vg at which the capacitor Cgc is saturated based on the function of determining the same capacitance Cx and (b3) the Cgc-Vg characteristics. ), And determining the Cgc-Lg characteristics by plotting the determined dose (Cgc), (b4) determining the fringe dose (Cf) based on the intercept on the Cgc axis of the Cgc-Lg characteristics and And (b5) determining the overlapping length ΔL and the overlapping capacity Cov based on the fringe capacity Cf. Provided is a device for measuring overlapping length and overlapping capacity of a MOSFET having a function (b) with a processor.

According to the apparatus, the processor is based on the branching point where the dependence of the capacitance (Cgc) on the gate length (Lg) in the plurality of Cgc-Vg characteristics, the capacitance (Cgc) formed between the gate and the source / drain (Cgc) Cx) is designed to be determined. Therefore, it is possible to accurately determine the overlapping length DELTA L even in a short channel MOSFET. In addition, it is possible to obtain the overlapping capacity Cov and the fringe capacity.

In the apparatus, the processor calculates a difference between two capacitances Cgc associated with two gate lengths Lm and Ln (m ≠ n) in the Cgc-Vg characteristics, instead of the function (b2). The gate voltage Vx in which the dependence of the gate voltage on the gate length Lg in the Cgc-Vg characteristics is defined as a gate voltage Vg in which the difference maximizes a constant ratio. Based on the Vg characteristics, it may be designed to have a function of determining the same capacitance Cx as the capacitance Cgc associated with the gate voltage Vx.

In the above apparatus, instead of the function (b2), the processor determines a plurality of [(δCgc / δVg) -Vg] characteristics representing the relationship between (δCgc / δVg) and the gate voltage Vg, respectively ( b21) determine the branch points in the [(δCgc / δVg) -Vg] characteristic as the respective gate voltage Vx in which the function and the dependence of the gate voltage on the gate length Lg in the Cgc-Vg characteristics are shown. On the basis of the Cgc-Vg characteristics, it may be designed to have a function (b22) for determining a capacitance Cx equal to the capacitance Cgc associated with the gate voltage Vx.

In the above apparatus, the processor is configured to provide a plurality of [δ (δCgc / δVg) / δLg representing the relationship between (δ (δCgc / δVg) / δLg) and gate voltage Vg, respectively, instead of the function (b2). (B21) function for determining the -Vg] characteristic, and [δ (δCgc / δVg) as the respective gate voltage Vx in which the dependence of the gate voltage on the gate length Lg in the Cgc-Vg characteristics is shown. / δLg-Vg] characteristic to determine the branch points, and based on the Cgc-Vg characteristics, to have a function (b22) to determine the capacitance (Cx) equal to the capacitance (Cgc) associated with the gate voltage (Vx). Can be designed.

In the above apparatus, the processor may include a plurality of [δ (δCgc / δVg) / δLg representing the relationship between (δ (δCgc / δVg) / δLg) and gate voltage Vg, respectively, instead of the function (b2). (B21) function for determining the -Vg] characteristic, and in the Cgc-Vg characteristics, the formula [Vx = Vp-k × Vw] (Vp is the [δ (δCgc / δVg) / δLg-Vg] characteristics Indicates a gate voltage at which a peak is generated, Vw represents a half value width in each of the above [δ (δCgc / δVg) / δLg-Vg] characteristics, and k is a constant (1.0 <k <1.5) in the range of 1.0 to 1.5. And calculates the gate voltage Vx in which the dependence of the gate voltage on the gate length Lg appears, and based on the Cgc-Vg characteristics, the capacitance Cgc associated with the gate voltage Vx It can be designed to have a function (b22) to determine the same capacitance (Cx).

According to the apparatus, the processor is based on the branching point where the dependence of the capacitance (Cgc) on the gate length (Lg) in the plurality of Cgc-Vg characteristics, the capacitance (Cgc) formed between the gate and the source / drain Cx) is designed to be determined. Therefore, it is possible to accurately determine the overlapping length DELTA L even in a short channel MOSFET. In addition, it is possible to obtain the overlapping capacity Cov and the fringe capacity.

In addition, the overlapping length is defined as the length of the overlapping region measured in the longitudinal direction of the gate, and the overlapping region is defined as the overlapping region with the diffusion region in which the gate becomes a source or a drain. (A1) When the CV characteristic of the MOS capacitor pattern is measured, an AC voltage and a DC bias voltage (Vg) are applied between the gate electrode and the substrate having the MOS capacitor pattern, and the current flowing between the gate electrode and the substrate Measuring a voltage applied between the gate electrode and the substrate; (a2) When the capacitance C _GSUB between each gate and the substrate of the plurality of MOSFETs having different gate lengths is measured, a DC bias voltage V _SUB is applied to the substrate, and between the gate and the source or the drain. By applying a DC bias voltage (Vg), a DC bias voltage (V _SUB ), and an AC voltage to measure the current flowing between the gates and the substrates of the plurality of MOSFETs while varying the DC bias voltage (V _SUB ) ( a) determining the CV characteristic representing the relationship between the DC bias voltage Vg and the capacitance C, based on the measurement apparatus and (b1) the measurement result performed by the measuring apparatus; Based on the function of determining the flat band capacitance C _FB per unit area of the gate electrode at the point where the DC bias voltage Vg becomes equal to the flat band voltage V _FB , and (b2) the same overlapping. Length (L _SD ), same gate width (W) and the DC bias voltage V _SUB is applied to the substrates of the plurality of MOSFETs having different gate lengths Lg, and the DC bias voltage Vg and the DC bias voltage V between the gate and the source or drain. _SUB ), and an AC voltage is applied to vary the DC bias voltage V _SUB while measuring a capacitance C _GSUB formed at the gate and the substrate at a gate voltage Vg of V _SUB + V _FB . Function, (b3) determining the built-in potential (Vbi) between the substrate and the source or drain, and (b4) obtained by plotting the capacitance (C _GSUB ) with respect to (Vbi-V _SUB ) ^1/2 . An apparatus for measuring overlapping length of a MOSFET having a processor (b) having a function of determining the overlapping length (L _SD ) based on a C _FB × (Lg-2L _SD ) intercept on a C _GSUB axis in a regression line. do.

According to the device, the measuring device and the processor, according to the method, are designed such that the DC bias voltage V _SUB applied to the substrate is measured in the forward direction until the source or drain is forward biased. As a result, the capacitance can be measured without being affected by the depletion layer formed between the source / drain and the substrate, and the PN junction position located between the substrate and the source / drain can be evaluated with high accuracy.

In addition, since the bias voltage is determined (Vg = V _SUB + V _FB ) so that the energy band of the region where the MOSFET capacitance is measured is flat, the depletion layer formed between the source / drain and the substrate is distributed in parallel to the PN junction. As a result, disturbance to the positioning of the PN junction is reduced. Thus, it is possible to determine the overlapping length close to the metallurgical overlapping length.

In addition, the overlapping length is defined as the length of the overlapping region measured in the longitudinal direction of the gate, and the overlapping region is defined as the overlapping region with the diffusion region in which the gate becomes a source or a drain. (A1) When the CV characteristic of the MOS capacitor pattern is measured, an AC voltage and a DC bias voltage (Vg) are applied between the gate electrode formed on the diffusion layer having the MOS capacitor pattern and the substrate, and the gate electrode and the Measuring a current flowing between the diffusion layer and a voltage applied between the gate electrode and the diffusion layer; (a2) When the capacitance Cgc between each gate and source or drain of a plurality of MOSFETs having different gate lengths is measured, a DC bias voltage V _SUB is applied to the substrate, and the gate and the drain or A current flowing between the gate and the source or drain while varying the DC bias voltage Vg or the DC bias voltage V _SUB applied to the substrate by applying a DC bias voltage Vg and an AC voltage between the sources. And (b1) determine the CV characteristic representing the relationship between the DC bias voltage (Vg) and the capacitance (C) based on the measurement results performed by the measuring device and (a) the measuring device. A function of determining the flat band capacitance C _FB per unit area of the gate electrode at the point at which the DC bias voltage Vg becomes equal to the flat band voltage V _FB , based on the CV characteristic; b2) same The overlapping length (L _SD), and applying the same gate width (W), and with each other, each of the gate and the source or a DC bias voltage (Vg) and the AC voltage to the drain of the plurality of MOSFET having a different gate length (Lg), By measuring the DC bias voltage (Vg) as a gate voltage while measuring the current flowing between the gate and the source or drain, and based on the current measurement results, respectively the capacitance (Cgc) between the gate and the source or drain and A function of determining a plurality of Cgc-Vg characteristics representing a relationship between gate voltages Vg, and (b3) the gate voltage Vg at which the capacitance Cgc is saturated based on the Cgc-Vg characteristics. Determine the capacitance (Cgc) associated with the gate length (Lg), and plot the determined capacitance (Cgc) to determine the Cgc-Lg characteristics, and (b4) based on the intercept on the Cgc axis of the Cgc-Lg characteristics the gate fringe capacitance (C _F The ability to determine _L) and, (b5) a measured dose time while varying the DC bias voltage (V _SUB) to be applied to each substrate of the MOSFET, the gate voltage (Vg) becomes zero (Vg = 0) A function of determining the capacitance C _GSD defined as (Cgc), (b6) a function of determining the built-in potential Vbi between the substrate and the source or drain, and (b7) (Vbi-V _SUB ) About ^one-half the capacity (C _GSD) by the float _{(C GSD - (Vbi-V} SUB) 1/2) is the minimum of the capacitance (C _GSD) determine the characteristic, and (C _GSD - (Vbi- V _SUB ) ^1/2 ) overlapping length of MOSFET with processor (b) having the function of determining the overlapping length (L _SD ) based on (C _FB × L _SD × W + 2C _FL ) A measuring device is provided.

According to the device, the measuring device and the processor, according to the method, are designed such that the DC bias voltage V _SUB applied to the substrate is measured in the forward direction until the MOSFET is turned on. As a result, the capacitance can be measured without being affected by the depletion layer formed between the source / drain and the substrate, and the PN junction position located between the substrate and the source / drain can be evaluated with high accuracy.

In addition, since the bias voltage is determined (Vg = 0V) so that the energy band of the region where the MOSFET capacitance is measured is flat (Vg = 0V), the depletion layer formed between the source / drain and the substrate is distributed in parallel to the PN junction, and as a result, Disturbance to the positioning of the PN junction is reduced. Thus, it is possible to determine the overlapping length close to the metallurgical overlapping length.

According to still another aspect of the present invention, there is provided a computer-readable recording medium storing a program for causing the computer to execute the above-described overlapping length and overlapping capacity measuring method of the MOSFET or the above-mentioned overlapping length measuring method.

The recording medium provides the same advantages as those provided by the methods described above.

In addition, there is provided a computer-readable recording medium storing a program for a computer to act as the above-described overlapping length and overlapping capacity measuring method of the MOSFET or the above-mentioned overlapping length measuring device.

The recording medium provides the same advantages as those provided by the above-described devices.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

First embodiment

3 shows the structure of an apparatus for measuring the overlapping length and overlapping capacity of a MOSFET according to the first embodiment.

As shown in Fig. 3, the device comprises a measuring device 2 for electrically measuring the capacitance Cgc formed between the gate and the source / drain of the MOSFET 1, and an input device 3 such as a keyboard and a mouse. ), A recording medium 4 storing a program therein, a data processor 5 operating according to a program stored in the recording medium 4, a memory 6 temporarily storing therein stored data and calculated data therein, And an output device 7 such as a display and a printer.

4 shows the structure of the measuring device 2. As shown in Fig. 4, the measuring device 2 comprises a device mounting portion 21 on which the MOSFET 1 is mounted, and a gate and a source / drain at each MOSFET 1 under the control of the data processor 5; The measuring unit 22 measures a current flowing through the human body and a voltage applied thereto.

The element mounting portion 21 has respective terminals electrically connected to the gate 1g, the source 1s, the drain 1d, and the semiconductor substrate 1b.

The measuring unit 22 includes a variable DC bias voltage source 221 for applying a DC bias voltage to the gate 1g, an AC voltage source 222 electrically connected in series to the variable DC bias voltage source 221, and a gate 1g. And a voltmeter 223 for measuring the voltage applied between the source 1s or the drain 1d, and an ammeter 224 for measuring the current flowing between the gate 1g and the source 1s or drain 1d. .

One end of the variable DC bias voltage source 221 is electrically connected to the AC voltage source 222, and the other end is grounded. The AC voltage source 222 is electrically connected to the gate terminal formed in the element mounting portion 21. The gate terminal is grounded through a voltmeter 223 and an ammeter 224. The source terminal and the drain terminal are electrically connected to each other and grounded through an ammeter 224. The substrate terminal formed on the element mounting portion 21 is grounded. Therefore, each MOSFET 1 is electrically connected to the measuring section 22 via the element mounting section 21.

Hereinafter, the operation of the data processor 5 will be described with reference to FIG. 5.

First, a plurality of NMOS transistors are mounted on the element mounting portion 21 as the MOSFET 1. Each NMOS transistor 1 is mounted on the element mounting portion 21 by connecting the gate 1g, the source 1s, the drain 1d and the semiconductor substrate 1b to the mounting terminal. These NMOS transistors 1 are manufactured in the same process, but have different gate lengths L1, L2, and L3.

Next, the DC bias voltage and the AC voltage are applied between the gate and the source / drain of each NMOS transistor 1 by the variable DC bias voltage source 221 and the AC voltage source 222, respectively. While varying the DC bias voltage Vg as the gate voltage, the current flowing between the gate and the source / drain and the voltage applied thereto are measured by the ammeter 224 and the voltmeter 223, respectively. In step 300, according to the measurement result, a plurality of Cgc-Vg characteristics respectively representing the relationship between the capacitance Cgc formed between the gate and the source / drain and the gate voltage Vg are determined.

The Cgc-Vg characteristic thus obtained is shown in FIG. An example of the Cgc-Vg characteristic measurement is shown in FIG. In Fig. 7, curves P1, P2, P3, and P4 have gate lengths (Lg) of 1.0 μm, 0.5 μm, 0.36 μm, and 0.24 μm, respectively, and have a gate width W of 1.0 mm in common. Cgc-Vg characteristics are shown.

Next, in step 302, the gate voltage Vx in which the dependence of the gate voltage Vg on the gate length Lg among the plurality of Cgc-Vg characteristics is determined is determined.

The gate voltage Vx can be determined in the following two ways.

In the first method, the difference between the capacitances Cgc formed between the gate and the source / drain is first calculated at any two gate lengths Lm and Ln (m ≠ n) among the plurality of Cgc-Vg characteristics. The gate voltage Vg at a constant ratio of the calculated difference to the maximum difference is determined as the gate voltage Vx.

8 shows an example in which a difference in Cgc-Vg characteristics is measured. In Fig. 8, curve P10 shows the difference in Cgc-Vg characteristics between two MOSFETs having gate lengths Lg of 1.0 mu m and 0.5 mu m, respectively, and curve P11 shows a gate of 0.5 mu m and 0.36 mu m, respectively. The difference in Cgc-Vg characteristics between two MOSFETs having a length Lg is shown, and the curve P12 shows the difference in Cgc-Vg characteristics between two MOSFETs having a gate length Lg of 0.36 µm and 0.24 µm, respectively. Indicates.

In the second method, first, a plurality of δCgc / δVg-Vg characteristics representing the relationship between δCgc / δVg and the gate voltage Vg obtained by differentiating the capacitance Cgc by the gate voltage Vg are calculated first. Next, the granularity or branch point of each delta Cgc / delta Vg-Vg characteristic is determined. The granularity or branch point is defined as the gate voltage Vx where the dependence of the gate voltage Vg on the gate length Lg appears.

FIG. 9 is a curve showing δCgc / δVg-Vg obtained from the Cgc-Vg characteristic shown in FIG. 6.

Fig. 10 shows a measurement example of the? Cgc /? Vg-Vg characteristic. In Fig. 10, curves Q1, Q2, Q3, and Q4 have gate lengths (Lg) of 1.0 mu m, 0.5 mu m, 0.36 mu m, and 0.24 mu m, respectively, and have a gate width W of 1.0 mm in common. ? Cgc /? Vg-Vg characteristics are shown. It can be seen from FIG. 10 that the gate voltage Vx is -0.4V.

After determining the gate voltage Vx according to the first and second methods described above, in step 304, the capacitance Cx associated with the gate voltage value Vx is determined in consideration of the Cgc-Vg characteristic.

Next, in step 306, the capacitance Cgc associated with the gate length Lg at the gate voltage Vg at which the capacitance Cgc is saturated in the Cgc-Vg characteristic is determined. Next, the capacitance Cgc thus determined is plotted against the gate length Lg to obtain Cgc-Lg characteristics as shown in FIG.

Next, in step 308, the fringe capacitance Cf is calculated based on the intercept of the Cgc axis in the Cgc-Lg characteristic determined in step 306.

Next, in step 310, the overlapping length ΔL and the overlapping capacity Cov are determined based on the fringe capacity Cf in that the capacity Cgc becomes equal to the capacity Cx in this Cgc-Lg characteristic. do. Here, the overlapping length ΔL is defined as the length of the overlapping region measured in the gate length Lg direction in the MOSFET, and the overlapping capacity Cov is formed in the overlapping region between the gate and the diffusion or drain region of the MOSFET. It is defined as a dose. The overlapping region is defined as the region where the gate overlaps with the diffusion region.

12 shows a measurement example of Cgc-Lg characteristics. 12 shows the Cgc-Lg characteristic when the gate voltage Vg is set to 2.0V. As is apparent from Fig. 12, the fringe capacitance Cf is 0.08 GPa, the overlapping capacitance Cov is 0.13 pF, and the overlapping length DELTA L is 56 nm.

According to the first embodiment described above, the capacitance in the capacitance Cgc formed between the gate and the source / drain is based on the branching point where the dependence of the capacitance Cgc on the gate length Lg in the plurality of Cgc-Vg characteristics is shown. (Cx) is determined. Therefore, it is possible to accurately determine the overlapping length DELTA L even in a short channel MOSFET. In addition, it is possible to obtain the overlapping capacity Cov and the fringe capacity Cf.

Second embodiment

Hereinafter, the overlapping length and overlapping capacity measuring apparatus of the MOSFET according to the second embodiment will be described. The apparatus according to the second embodiment has the same structure as that of the apparatus according to the first embodiment except for the operation of the data processor 5. Therefore, only the differences between these devices are described.

13 is a flowchart showing the steps performed by the data processor 5 in the apparatus according to the second embodiment.

First, similarly to the first embodiment, a plurality of NMOS transistors are mounted as the MOSFET 1 on the element mounting portion 21. Each NMOS transistor 1 is mounted on the element mounting portion 21 by connecting the gate 1g, the source 1s, the drain 1d and the semiconductor substrate 1b to the mounting terminal. These NMOS transistors 1 are manufactured in the same process, but have different gate lengths L1, L2, and L3.

Next, the DC bias voltage and the AC voltage are applied between the gate and the source / drain of each NMOS transistor 1 by the variable DC bias voltage source 221 and the AC voltage source 222, respectively. While varying the DC bias voltage Vg as the gate voltage, the current flowing between the gate and the source / drain and the voltage applied thereto are measured by the ammeter 224 and the voltmeter 223, respectively. In step 400, according to the measurement result, a plurality of Cgc-Vg characteristics respectively representing the relationship between the capacitance Cgc formed between the gate and the source / drain and the gate voltage Vg are determined.

The Cgc-Vg characteristic thus obtained is shown in FIG. An example of the Cgc-Vg characteristic measurement is shown in FIG. In Fig. 14, curves P21, P22, P23, and P24 each have a gate length Lg of 1.0 mu m, 0.5 mu m, 0.36 mu m, and 0.24 mu m, and have a gate width W of 1.0 mm in common. Cgc-Vg characteristics are shown.

Next, in step 402, the capacitance Cgc is differentiated by the gate voltage Vg in the Cgc-Vg characteristic obtained in step 400, and this differential capacitance δCgc / δVg is further differentiated by the gate length Lg, A plurality of δ (δCgc / δVg) / δLg-Vg characteristics indicating the relationship between (δCgc / δVg) / δLg and the gate voltage Vg are determined.

15 is a curve showing δ (δCgc / δVg) / δLg-Vg characteristics. Fig. 16 shows measurement examples of δ (δCgc / δVg) / δLg-Vg characteristics. In Fig. 16, curve R1 represents the difference of δ (δCgc / δVg) / δLg-Vg characteristics between two MOSFETs having a gate length Lg of 0.5 μm and 0.36 μm, and curve R2 is 0.36, respectively. Differences in the characteristics of δ (δCgc / δVg) / δLg-Vg between two MOSFETs having a gate length Lg of 0.2 μm and 0.24 μm, and curve R3 are 1.0 μm and 0.5 μm, respectively, The difference of δ (δCgc / δVg) / δLg-Vg characteristics between two MOSFETs having?

Next, in step 404, on the basis of the δ (δCgc / δVg) / δLg-Vg characteristic determined in step 402, the gate whose dependence of the gate voltage Vg on the gate length Lg among the plurality of Cgc-Vg characteristics is shown. Determine the voltage Vx. The gate voltage Vx is determined as the gate voltage Vg at the standing point of the δ (δCgc / δVg) / δLg-Vg characteristics shown in FIG. It can be seen from FIG. 15 that the gate voltage Vx is -0.4V.

The gate voltage Vx may be determined by the following method.

In the Cgc-Vg characteristic, the capacitance Cgc is differentiated into the gate voltage Vg, and the differential capacitance δCgc / δVg is further differentiated back to the gate length Lg, so that δ (δCgc / δVg) / δLg and gate voltage ( Δ (δCgc / δVg) / δLg-Vg characteristics indicating a relationship with Vg) are determined. Next, the gate voltage Vx is calculated according to the equation (3).

Vx = Vp-k × Vw

In Equation 3, Vp represents a gate voltage at which a peak is generated at each [δ (δCgc / δVg) / δLg-Vg] characteristic, and Vw is a half value width at each [δ (δCgc / δVg) / δLg-Vg] characteristic. K is a constant (1.0 <k <1.5) in the range of 1.0-1.5.

Fig. 17 shows an example of measuring the gate voltage Vx based on the half-value width in the [? (? Cgc /? Vg) /? Lg-Vg] characteristic. In FIG. 17, the vertical axis represents the ratio of δ (δCgc / δVg) / δLg to the maximum [δ (δCgc / δVg) / δLg] max. In Fig. 17, the gate voltage Vp is set equal to 0.5V, the half value width Vw is set equal to 0.8V, and the constant k is set to 1.1. The gate length Lg is set in the range of 1.0 µm to 0.5 µm. According to these parameters, the gate voltage Vx is calculated as follows.

Vx = Vp-k × Vw = 0.5-1.1 × 0.8 = -0.38 V

Steps 406 to 412 where subsequent steps are performed are the same as steps 304 to 310 described with reference to FIG. 5.

In step 406, the capacitance Cx associated with the gate voltage value Vx is determined in consideration of the Cgc-Vg characteristic.

Next, in step 408, the capacitance Cgc associated with the gate length Lg at the gate voltage Vg at which the capacitance Cgc is saturated in the Cgc-Vg characteristic is determined. The capacitance Cgc thus determined is then plotted against the gate length Lg to obtain Cgc-Lg characteristics as shown in FIG.

Next, in step 410, the fringe capacity Cf is calculated based on the intercept of the Cgc axis in the Cgc-Lg characteristic determined in step 408.

Next, in step 412, the overlapping length ΔL and the overlapping capacity Cov are determined based on the fringe capacity Cf in that the capacity Cgc becomes the same as the capacity Cx in this Cgc-Lg characteristic. do.

19 shows a measurement example of Cgc-Lg characteristics. 19 shows Cgc-Lg characteristics obtained when the gate voltage Vg is set to 2.0V. As is apparent from Fig. 19, the fringe capacitance Cf is 0.08 GPa, the overlapping capacitance Cov is 0.13 pF, and the overlapping length DELTA L is 56 nm.

According to the second embodiment described above, the capacitance in the capacitance Cgc formed between the gate and the source / drain is based on the branching point where the dependency of the capacitance Cgc on the gate length Lg in the plurality of Cgc-Vg characteristics is shown. (Cx) is determined. Therefore, it is possible to accurately determine the overlapping length DELTA L even in a short channel MOSFET. In addition, it is possible to obtain the overlapping capacity Cov and the fringe capacity Cf.

Third embodiment

Hereinafter, the overlapping length measuring apparatus according to the third exemplary embodiment will be described with reference to FIGS. 20 through 25. According to this apparatus, the overlapping length is measured by applying a DC bias voltage (V _SUB ) to the semiconductor substrate of the MOSFET until the source / drain and semiconductor substrate junctions are forward biased.

The device according to the third embodiment has the same structure as that of the device according to the first embodiment except for the operation of the measuring unit 22 and the data processor 5 of the measuring device 2. Therefore, only the differences between these devices are described below.

20 shows the structure of a measuring device in the device according to the third embodiment of the present invention. The measuring device 2 measures the current flowing between the gate and the substrate in each MOSFET 1 and the voltage applied thereto under the control of the element mounting portion 21a on which the MOSFET 1 is mounted and the data processor 5. The measuring part 22a is provided.

The element mounting portion 21a includes terminals connected to the gate 1g, the source 1s, the drain 1d, and the semiconductor substrate 1b in the MOSFET 1, and the MOS capacitor 40 shown in Fig. 21A. Terminals connected to the gate 40g and the semiconductor substrate 40b are provided.

The measuring unit 22a includes a variable DC bias voltage source 221 and 225 for applying a DC bias voltage to the gate 1g, an AC voltage source 222 and a gate 1g electrically connected in series with the variable DC bias voltage source 221. A voltmeter 223 that measures the voltage applied between the gate 40g and the semiconductor substrate 1b (semiconductor substrate 40b), and the gate 1g (gate 40g) and the semiconductor substrate 1b (semiconductor). The ammeter 224 which measures the electric current which flows between the board | substrates 40b) is provided.

The variable DC bias voltage source 225 applies a DC bias voltage to the semiconductor substrate 1 of the MOSFET 1.

The variable DC bias voltage sources 221 and 225 are electrically connected in series to the AC voltage source 222. The other end of the variable DC bias voltage source 225 is grounded. The gate terminal of the element mounting portion 21a is electrically connected to the substrate terminal via the voltmeter 223. The substrate terminal of the element mounting portion 21a is electrically connected via the ammeter 224 at the node P where the variable DC bias voltage sources 221 and 225 are electrically connected to each other. The source and drain terminals of the element mounting portion 21a are electrically connected to each other and grounded.

Hereinafter, the operation of the data processor 5 will be described with reference to FIG.

First, the gate 40g and the semiconductor substrate 40b of the MOS capacitor 40 shown in FIG. 21A are connected to the mounting terminal of the element mounting portion 21a.

Next, the DC bias voltage Vg and the AC voltage are applied between the gate of the MOS capacitor (or MOS capacitor pattern) 40 and the semiconductor substrate by the variable DC bias voltage source 221 and the AC voltage source 222, respectively. The variable DC bias voltage source 225 is set to apply 0V. The ammeter 224 and the voltmeter 223 measure the current flowing between the gate and the semiconductor substrate of the MOS capacitor 40 and the voltage applied thereto while varying the DC bias voltage Vg as the gate voltage. According to the measurement result, in step 500, the C-Vg characteristic indicating the relationship between the capacitance C of the MOS capacitor 40 and the gate voltage Vg is determined.

The C-Vg characteristic thus obtained is shown in FIG. In Fig. 23, the horizontal axis represents the gate voltage Vg, and the vertical axis represents C / C0. Here, C represents the capacitance of the MOS capacitor 40 when the gate voltage Vg is applied, and C0 represents the capacitance of the MOS capacitor 40 when the gate voltage Vg is zero (Vg = 0). Indicates.

In Fig. 23, the solid line X1 represents the ideal C-Vg characteristic, and the dotted line X2 represents the C-Vg characteristic actually obtained. In the ideal C-Vg characteristic indicated by the solid line X1, the capacitance of the MOS capacitor 40 when the gate voltage Vg is zero is referred to as flat band capacitance C _FB .

The actual obtained C-Vg characteristic indicated by the dotted line X2 is due to the surface potential generated on the MOS capacitor 40 due to the difference in the work function of the gate electrode and the semiconductor substrate, the charge present in the oxide film, and the like. It is deflected in the transverse direction by about (V _FB ). Here, the flat band voltage V _FB is defined as the voltage required to flatten the energy band on the surface of the semiconductor substrate of the MOS capacitor 40 by compensating the surface potential.

In step 502, the unit of the gate electrode of the MOS capacitor 40 at the point where the gate voltage or the DC bias voltage Vg becomes equal to the flat band voltage V _FB based on the C-Vg characteristic obtained in step 500. Determine the flat band capacity (C _FB ) per area.

Next, a plurality of NMOS transistors are mounted as the MOSFET 1 on the element mounting portion 21a. As shown in Fig. 20, each NMOS transistor 1 is mounted on the element mounting portion 21a by connecting the gate 1g, the source 1s, the drain 1d and the semiconductor substrate 1b to the mounting terminal. These NMOS transistors 1 are manufactured in the same process. These NMOS transistors 1 have different gate lengths L1, L2, and L3.

Next, in step 504, the DC bias voltage V _SUB is applied to the substrate, and at the same time, the DC bias voltage Vg, the DC bias voltage V _SUB , and the AC voltage are applied to the gate and source of each NMOS transistor 1. Applied between / drain. While varying the DC bias voltage (V _SUB ), measure the capacitance (C _GSUB ) formed between the gate and the substrate where the gate voltage (Vg) is equal to the sum of V _SUB and V _FB (Vg = V _SUB + V _FB ). do. That is, the bias voltage is determined (Vg = V _SUB + V _FB ) so that the energy band of the region where the capacitance of the MOSFET is measured becomes flat. The DC bias voltage V _SUB varies from 0.7V to approximately -1.0V with respect to the source / drain voltage.

In step 506, the built-in potential Vbi between the substrate and the source / drain is determined by simulation.

Next, in step 508, the capacitance C _GSUB formed between the gate and the substrate is plotted against (Vbi-V _SUB ) ^1/2 to obtain a regression line as shown in FIG.

Capacity C _GSUB is calculated according to Equations 4 and 5 below.

D _SUB (V _SUB ) = k (Vbi-V _SUB ) ^1/2

C _GSUB = C _FB × (Lg-2L _SD -2D _SUB (V _SUB )) × W + 2C _SW (V _SUB )

In Equations 4 and 5, D _SUB is the distance between the substrate-side end of the depletion layer formed between the substrate and the source / drain and the PN junction formed between the substrate and the source / drain, as shown in FIG. D _SUB (V1) indicates when V _SUB is equal to V1 (V _SUB = V1), and D _SUB (V2) indicates when V _SUB is equal to V2 (V _SUB = V2) (V1> V2) . L _SD is an overlapping length defined as the length in the gate length direction in the overlapping region with the diffusion region where the gate becomes the source / drain. C _SW represents the side capacitance between the gate and the substrate. C _SW becomes smaller as D _SUB becomes smaller, and becomes zero when D _SUB becomes zero. W is the gate width.

As shown in FIG. 25, as the voltage forward biased to the PN junction formed between the source / drain and the substrate increases, the thickness of the depletion layer formed between the substrate and the source / drain decreases.

In step 510, the overlapping length L _SD is calculated based on the C _FB × (Lg-2L _SD ) intercept on the C _GSUB axis in the regression line determined in step 508.

According to the third embodiment described above, the DC bias voltage V _SUB applied to the substrate is measured in the forward direction until the source / drain is forward biased. As a result, the capacitance can be measured without being affected by the depletion layer formed between the source / drain and the substrate, and the PN junction position located between the source / drain and the substrate can be evaluated with high accuracy.

In addition, since the bias voltage is determined (Vg = V _SUB + V _FB ) so that the energy band of the region where the MOSFET capacitance is measured is flat, the depletion layer formed between the source / drain and the substrate is distributed in parallel to the PN junction. As a result, disturbance to the positioning of the PN junction is reduced. Thus, it is possible to determine the overlapping length close to the metallurgical overlapping length.

Fourth embodiment

Hereinafter, the overlapping length measuring apparatus according to the fourth embodiment will be described with reference to FIGS. 26 to 28. According to this apparatus, the overlapping length is measured by applying a DC bias voltage V _SUB to the substrate of the MOSFET in the forward direction until just before the MOSFET is turned on.

The apparatus according to the fourth embodiment has the same structure as that of the apparatus according to the third embodiment except for the operation of the data processor 5. Therefore, only the differences between these devices are described.

26 is a flowchart of the steps performed by the data processor 5 in the apparatus according to the fourth embodiment. Hereinafter, the operation of the data processor 5 will be described with reference to FIG. 26.

First, the gate 41g and the electrode 41a of the diffusion layer of the MOS capacitor 41 shown in FIG. 21B are connected to the mounting terminal of the element mounting portion 21 shown in FIG. The semiconductor substrate 40b is grounded.

Referring to FIG. 26, a DC bias voltage (Vg) and an AC voltage are generated between the gate of the MOS capacitor (or MOS capacitor pattern) 41 and the semiconductor substrate by the variable DC bias voltage source 221 and the AC voltage source 222, respectively. Is approved. The ammeter 224 and the voltmeter 223 measure the current flowing between the gate and the semiconductor substrate of the MOS capacitor 41 and the voltage applied thereto while varying the DC bias voltage Vg as the gate voltage. According to the measurement result, in step 600, the C-Vg characteristic indicating the relationship between the capacitance C of the MOS capacitor 41 and the gate voltage Vg is determined. The C-Vg characteristic thus obtained is shown in FIG.

In step 602, the unit of the gate electrode of the MOS capacitor 41 at the point that the gate voltage or the DC bias voltage Vg becomes equal to the flat band voltage V _FB based on the C-Vg characteristic obtained in step 600. Determine the flat band capacity (C _FB ) per area.

Next, a plurality of NMOS transistors are mounted as the MOSFET 1 on the element mounting portion 21a. Each NMOS transistor 1 is mounted on the element mounting portion 21a by connecting the gate 1g, the source 1s, the drain 1d, and the semiconductor substrate 1b to the mounting terminal of the element mounting portion 21a. These NMOS transistors 1 are manufactured in the same process and have gates formed in one of the wells formed on the surface of the semiconductor substrate or the surface of the semiconductor substrate. These NMOS transistors 1 have different gate lengths L1, L2, and L3.

Next, in step 604, the capacitance Cgc formed between the gate and the source / drain in the strong inversion region of each NMOS transistor 1 is measured in the same manner as in steps 300 to 306 described with reference to FIG. Therefore, the Cgc-Lg characteristic is determined.

In particular, the DC bias voltage Vg and the AC voltage are respectively applied between the gate and the source / drain of each NMOS transistor 1 by the variable DC bias voltage source 221 and the AC voltage source 222. The ammeter 224 and the voltmeter 223 measure the current flowing between the gate and the source / drain and the voltage applied thereto while varying the DC bias voltage Vg as the gate voltage. According to the measurement result, a plurality of Cgc-Vg characteristics indicating the relationship between the capacitor Cgc and the gate voltage Vg are determined, respectively. The Cgc-Vg characteristic thus obtained is shown in FIG.

Next, the capacitance Cgc associated with the gate length Lg at the gate voltage Vg at which the capacitance Cgc is saturated in the Cgc-Vg characteristic is determined. Next, the capacitance Cgc thus determined is plotted against the gate length Lg to obtain Cgc-Lg characteristics as shown in FIG.

Next, in step 606, the gate fringe capacitance 2C _FL is calculated based on the intercept of the Cgc axis in the Cgc-Lg characteristic.

Next, in step 608, the capacitance C _GSD is measured where the gate voltage Vg becomes zero while varying the DC bias voltage V _SUB applied to the substrate of the MOSFET. That is, the bias voltage is determined (Vg = 0) so that the energy band of the region where the capacitance of the MOSFET is measured becomes flat. The DC bias voltage V _SUB varies from 0.7V to approximately -1.0V with respect to the source / drain voltage.

In step 610, the built-in potential Vbi between the substrate and the source / drain is determined by simulation.

Next, in step 612, the capacitance C _GSD formed between the gate and the source / drain is plotted against (Vbi-V _SUB ) ^1/2 so that C _GSD − (Vbi-V _SUB ) as shown in FIG. 27. ^1/2 characteristic is obtained.

Here, the capacitance C _GSD formed between the gate and the source / drain is determined according to Equations 6 and 7 below.

D _SUB (V _SUB ) = k ₁ (Vbi-V _SUB ) ^1/2

C _GSD = 2C _FB1 × (L _SD -D _SD (V _SUB )) × W + 2C _SW1 (V _SUB ) + 2C _FL

In Equations 6 and 7, D _SD is a distance between the source / drain side end of the depletion layer formed between the substrate and the source / drain and the PN junction formed between the substrate and the source / drain, as shown in FIG. . D _SD (V1) indicates when V _SUB is equal to V1 (V _SUB = V1), and D _SD (V2) indicates when V _SUB is equal to V2 (V _SUB = V2) (V1> V2) . L _SD is an overlapping length defined as the length in the gate length direction in the overlapping region with the diffusion region where the gate becomes the source / drain. C _SW1 represents the lateral capacitance between the gate and the source / drain. C _SW1 becomes smaller as D _SD becomes smaller, and becomes zero when D _SD becomes zero. W represents the gate width.

As shown in FIG. 28, as the voltage forward biased to the PN junction formed between the source / drain and the substrate increases, the thickness of the depletion layer formed between the substrate and the source / drain decreases.

In step 614, C _GSD determined in step 612 - the basis of the minimum capacity (C _GSD) from (Vbi-V _SUB) ^1/2 characteristics, the overlapping length (L _SD) are calculated.

According to the fourth embodiment described above, the DC bias voltage V _SUB applied to the substrate is measured in the forward direction until the MOSFET is turned on. As a result, the capacitance can be measured without being affected by the depletion layer formed between the source / drain and the substrate, and the PN junction position located between the substrate and the source / drain can be evaluated with high accuracy.

In addition, since the bias voltage is determined (Vg = 0V) so that the energy band of the region where the MOSFET capacitance is measured is flat (Vg = 0V), the depletion layer formed between the source / drain and the substrate is distributed in parallel to the PN junction, and as a result, Disturbance to the positioning of the PN junction is reduced. Thus, it is possible to determine the overlapping length close to the metallurgical overlapping length.

An example of a recording medium storing therein a program for implementing the above-described apparatus for measuring the overlapping length and overlapping capacity of a MOSFET or measuring the overlapping length of a MOSFET will be described below.

The recording medium which stores the program for forming the above-mentioned device may be programmed by a computer in a readable programming language or recorded on CD-ROM, floppy disk, magnetic tape, and other suitable program storage means. This can be done by recording the program on the medium.

As a recording medium, a hard disk mounted on the server may be used. It is also possible to form the recording medium according to the present invention by storing the above-described computer program in the above-described recording medium and the like and reading the computer program through another network.

According to the present invention described above, the capacitance Cx in the capacitance Cgc formed between the gate and the source / drain based on the branching point where the dependence of the capacitance Cgc on the gate length Lg in the plurality of Cgc-Vg characteristics appears. ) Is determined. Therefore, it is possible to accurately determine the overlapping length DELTA L even in a short channel MOSFET. In addition, it is possible to obtain the overlapping capacity Cov and the fringe capacity.

In addition, the DC bias voltage V _SUB applied to the substrate is measured in the forward direction until the source or drain is forward biased. As a result, the capacitance can be measured without being affected by the depletion layer formed between the source / drain and the substrate, and therefore, the PN junction position located between the substrate and the source / drain can be evaluated with high accuracy.

In addition, since the bias voltage is determined so that the energy band of the region where the MOSFET capacitance is measured is flat, the depletion layer formed between the source / drain and the substrate is distributed in parallel to the PN junction, and as a result, the positioning of the PN junction is performed. Disturbance to is reduced. Thus, it is possible to determine the overlapping length close to the metallurgical overlapping length.

Claims (16)

The overlapping length is defined as the length of the overlapping region measured in the longitudinal direction of the gate, and the overlapping capacitance is defined as the capacitance formed in the overlapping region between the gate and the diffusion region which becomes the source or drain region, and the overlapping region is the gate In the method of measuring the overlapping length and the overlapping capacity of a MOSFET, wherein is defined as a region overlapping with the diffusion region: (a) Applying a DC bias voltage (Vg) and an AC voltage between gates and sources or drains of a plurality of MOSFETs having different gate lengths, and varying the DC bias voltage (Vg) as a gate voltage so that the gate and the A plurality of Cgc- which represent the relationship between the capacitance Cgc and the gate voltage Vg formed between the gate and the source or drain, respectively, by measuring the current flowing between the source or the drain, and based on the result of the current measurement Determining a Vg characteristic; (b) determining the gate voltage Vx in which the dependence of the gate voltage Vg on the gate length Lg in the Cgc-Vg characteristics among the gate voltage Vg is determined, and the Cgc-Vg characteristics Determining a capacitance Cx equal to the capacitance Cgc associated with the gate voltage Vx based on the capacitance; (c) The capacitor Cgc associated with the gate length Lg is determined at the gate voltage Vg at which the capacitor Cgc is saturated based on the Cgc-Vg characteristics, and the determined capacitance Cgc is determined. Plotting the Cgc-Lg characteristic; (d) determining a fringe dose (Cf) based on the section on the Cgc axis of the Cgc-Lg characteristic; And (e) determining the overlapping length (ΔL) and the overlapping capacity (Cov) based on the fringe capacitance (Cf). The method of claim 1, wherein step (b) calculates a difference between two capacitances Cgc associated with two gate lengths Lm and Ln (m ≠ n) in the Cgc-Vg characteristics, and calculates Cgc. The gate voltage Vx in which the dependence of the gate voltage on the gate length Lg in the -Vg characteristics is defined as the gate voltage Vg in which the difference maximizes a constant ratio, and the Cgc-Vg characteristics And the step (b1) of determining a capacitance Cx equal to the capacitance Cgc associated with the gate voltage Vx is based on the overlapping length and overlapping capacitance measuring method of the MMOSFET. The method of claim 1, wherein step (b) comprises: (b2) determining a plurality of [(δCgc / δVg) -Vg] characteristics representing a relationship between (δCgc / δVg) and a gate voltage Vg, respectively; Branch points are determined in the [(δCgc / δVg) -Vg] characteristic as the respective gate voltages Vx in which the dependence of the gate voltage on the gate length Lg in the Cgc-Vg characteristics is shown. The overlapping length and overlapping capacity measuring method of the MMOSFET, characterized in that the step is replaced by step (b3) of determining the same capacity (Cx) and the capacitance (Cgc) associated with the gate voltage (Vx) based on the Vg characteristics. The method of claim 1, wherein the step (b) comprises a plurality of [δ (δCgc / δVg) / δLg-Vg] characteristics each indicating a relationship between (δ (δCgc / δVg) / δLg) and the gate voltage Vg. (B4), and [δ (δCgc / δVg) / δLg-Vg as the respective gate voltages Vx in which the dependence of the gate voltage on the gate length Lg in the Cgc-Vg characteristics is shown. The branch points are determined in the characteristic; and (b5) is determined based on the Cgc-Vg characteristics to determine the same capacitance Cx as the capacitance Cgc associated with the gate voltage Vx. Method of measuring overlapping length and overlapping capacity of MMOSFET The method of claim 1, wherein the step (b) comprises a plurality of [δ (δCgc / δVg) / δLg-Vg] characteristics each indicating a relationship between (δ (δCgc / δVg) / δLg) and the gate voltage Vg. (B4) and the Cgc-Vg characteristics, wherein the peak occurs in the [δ (δCgc / δVg) / δLg-Vg] characteristic. The gate voltage, and Vw represents the half value width in each of the above [δ (δCgc / δVg) / δLg-Vg] characteristics, and k is a gate according to a constant (1.0 <k <1.5) in the range of 1.0 to 1.5. Calculate the gate voltage Vx in which the dependence of the gate voltage on the length Lg appears, and based on the Cgc-Vg characteristics, the capacitance Cx equal to the capacitance Cgc associated with the gate voltage Vx. The overlapping length and overlapping capacity measuring method of MMOSFET, characterized in that is replaced by step (b6). In the overlapping length measuring method of a MOSFET, the overlapping length is defined as the length of the overlapping region measured in the longitudinal direction of the gate, and the overlapping region is defined as a region overlapping with the diffusion region in which the gate becomes a source or a drain. (a) A CV characteristic representing the relationship between the DC bias voltage Vg and the capacitor C applied between the gate electrode having the MOS capacitor pattern and the substrate is determined, and the DC bias voltage Vg is determined based on the CV characteristic. Determining a flat band capacitance (C _FB ) per unit area of the gate electrode at a point where?) _Becomes equal to the flat band voltage (V _FB ); (b) Applying a DC bias voltage (V _SUB ) to the substrates of a plurality of MOSFETs having the same overlapping length (L _SD ), the same gate width (W), and different gate lengths (Lg), the gate and source or drain Applying a DC bias voltage (Vg), a DC bias voltage (V _SUB ), and an AC voltage to a human, while varying the DC bias voltage (V _SUB ), the gate voltage (Vg) at V _SUB + V _FB , the Measuring a capacitance C _GSUB formed on a gate and the substrate; (c) determining a built-in potential (Vbi) between the substrate and the source or drain; And (d) The overlapping length L based on the C _FB × (Lg-2L _SD ) intercept on the C _GSUB axis in the regression line obtained by plotting the capacity C _GSUB with respect to (Vbi-V _SUB ) ^1/2 . _SD ) determining the overlapping length of the MOSFET comprising the step of determining. In the overlapping length measuring method of a MOSFET, the overlapping length is defined as the length of the overlapping region measured in the longitudinal direction of the gate, and the overlapping region is defined as a region overlapping with the diffusion region in which the gate becomes a source or a drain. (a) determining a CV characteristic indicating a relationship between a DC bias voltage Vg and a capacitor C applied between the diffusion layer and the gate electrode formed on the diffusion layer and having a MOS capacitor pattern, and based on the CV characteristic, Determining a flat band capacitance (C _FB ) per unit area of the gate electrode at the point where the DC bias voltage (Vg) becomes equal to the flat band voltage (V _FB ); (b) DC bias voltage (Vg) and AC voltage between each gate and source or drain of a plurality of MOSFETs having the same overlapping length (L _SD ), the same gate width (W), and different gate lengths (Lg). Applying a current, and varying the DC bias voltage (Vg) as a gate voltage, and measuring the current flowing between the gate and the source or drain, and based on the current measurement result, between the gate and the source or drain, respectively. Determining a plurality of Cgc-Vg characteristics representing a relationship between the formed capacitance Cgc and the gate voltage Vg; (c) In the Cgc-Vg characteristics, at the gate voltage Vg at which the capacitance Cgc is saturated, the capacitance Cgc associated with the gate length Lg is determined, and the determined capacitance Cgc is plotted. Determining the Cgc-Lg characteristics; (d) determining a gate fringe capacitance (C _FL ) based on the intercept on the Cgc axis of the Cgc-Lg characteristic; (e) The capacitance defined as the capacitance Cgc respectively measured when the gate voltage Vg becomes zero (Vg = 0) while varying the DC bias voltage V _SUB applied to the substrates of the respective MOSFETs. C _GSD ); (f) determining a built-in potential (Vbi) between the substrate and the source or drain; And minimal _{- ((Vbi-V SUB)} 1/2 C GSD) determining a property, and the capacitance (C _GSD) (g) said capacitance (C _GSD) to (Vbi-V _SUB) to about ^1/2 the floating wherein the _{(C GSD - (Vbi-V} SUB) 1/2) basis as in the (C _{FB SD} × L × W + 2C _FL) characteristics by overlapping length measurement comprising the step of determining the overlapping length (L _SD) Way. The overlapping length is defined as the length of the overlapping region measured in the longitudinal direction of the gate, and the overlapping capacitance is defined as the capacitance formed in the overlapping region between the gate and the diffusion region which becomes the source or drain region, and the overlapping region is the gate In the overlapping length and the overlapping capacity measuring apparatus of a MOSFET, wherein is defined as a region overlapping with the diffusion region: (a) Applying a DC bias voltage (Vg) and an AC voltage between gates and sources or drains of a plurality of MOSFETs having different gate lengths, and varying the DC bias voltage (Vg) as a gate voltage so that the gate and the A measuring device for measuring a current flowing between the source or the drain; And (b1) a function of determining a plurality of Cgc-Vg characteristics representing a relationship between a capacitor Cgc and a gate voltage Vg formed between the gate and the source or drain, respectively, based on the result of the current measurement; (b2) In the gate voltage Vg, the gate voltage Vx in which the dependence of the gate voltage Vg on the gate length Lg in the Cgc-Vg characteristics is determined, and the Cgc-Vg characteristics are determined. A function of determining a capacitance Cx equal to the capacitance Cgc associated with the gate voltage Vx; (b3) Based on the Cgc-Vg characteristics, the capacitance Cgc associated with the gate length Lg is determined at the gate voltage Vg at which the capacitance Cgc is saturated, and the determined capacitance Cgc is determined. Plotting the Cgc-Lg characteristics to determine the characteristics; (b4) determining a fringe dose (Cf) based on the section on the Cgc axis of the Cgc-Lg characteristic; And (b5) having a function of determining the overlapping length ΔL and the overlapping capacity Cov based on the fringe dose Cf; (b) Overlap length and overlapping capacity measuring apparatus for MOSFETs with a processor. The method of claim 8, wherein the processor is configured to determine a difference between two capacitances Cgc associated with two gate lengths Lm and Ln (m ≠ n) in the Cgc-Vg characteristics instead of the function (b2). Calculate a gate voltage Vx in which the dependence of the gate voltage on the gate length Lg in the Cgc-Vg characteristics is defined as a gate voltage Vg in which the difference maximizes a constant ratio, and the Cgc The overlapping length and overlapping capacitance measuring device of a MOSFET having a function of determining a capacitance Cx equal to the capacitance Cgc associated with the gate voltage Vx based on the Vg characteristics. The processor according to claim 8, wherein the processor determines, instead of the function (b2), a plurality of [(δCgc / δVg) -Vg] characteristics each representing a relationship between (δCgc / δVg) and a gate voltage Vg. (B2) determines the branch points in the [(δCgc / δVg) -Vg] characteristic as the respective gate voltages Vx in which the function and the dependence of the gate voltage on the gate length Lg in the Cgc-Vg characteristics are shown. And overlapping length and overlapping of the MOSFET with a function of determining (B3) the same capacitance Cx as the capacitance Cgc associated with the gate voltage Vx based on the Cgc-Vg characteristics. Capacity measuring device. The method according to claim 8, wherein the processor is configured to provide a plurality of (δ (δCgc / δVg) / indicating the relationship between (δ (δCgc / δVg) / δLg) and the gate voltage Vg, respectively, instead of the function (b2). (B4) a function of determining the [Delta] Lg-Vg] characteristic, and the respective [Delta] Cgc / δVg as the respective gate voltages Vx in which the dependence of the gate voltage on the gate length Lg in the Cgc-Vg characteristics is shown. (B5) function of determining branch points in the () / δLg-Vg] characteristic and determining a capacitance (Cx) equal to the capacitance (Cgc) associated with the gate voltage (Vx) based on the Cgc-Vg characteristics. Device for measuring overlapping length and overlapping capacity of MOSFET, characterized in that it has. The method according to claim 8, wherein the processor is configured to provide a plurality of [δ (δCgc / δVg) / representing the relationship between (δ (δCgc / δVg) / δLg) and gate voltage Vg, respectively, instead of the function (b2). (B4) function for determining the δLg-Vg] characteristic, and in the Cgc-Vg characteristics, the formula [Vx = Vp−k × Vw] (Vp is the [δ (δCgc / δVg) / δLg-Vg] The gate voltage at which the peak is generated in the characteristic is shown, and Vw represents the half value width in each of the [δ (δCgc / δVg) / δLg-Vg] characteristics, and k is a constant (1.0 <k <1.5) in the range of 1.0 to 1.5. Calculates the gate voltage Vx in which the dependence of the gate voltage on the gate length Lg appears, and based on the Cgc-Vg characteristics, the capacitance Cgc associated with the gate voltage Vx. The overlapping length and overlapping capacity measuring device of a MOSFET, characterized in that it has a function (B6) to determine the same capacity (Cx). In the overlapping length measuring apparatus of a MOSFET, an overlapping length is defined as a length of an overlapping region measured in the longitudinal direction of a gate, and the overlapping region is defined as an overlapping region with a diffusion region in which the gate becomes a source or a drain. (a1) When the CV characteristic of the MOS capacitor pattern is measured, an AC voltage and a DC bias voltage (Vg) are applied between the gate electrode and the substrate having the MOS capacitor pattern, and the current flowing between the gate electrode and the substrate and the gate Measuring a voltage applied between an electrode and the substrate; (a2) When the capacitance C _GSUB between each gate and the substrate of the plurality of MOSFETs having different gate lengths is measured, a DC bias voltage V _SUB is applied to the substrate, and between the gate and the source or the drain. By applying a DC bias voltage (Vg), a DC bias voltage (V _SUB ), and an AC voltage to measure the current flowing between the gates and the substrates of the plurality of MOSFETs while varying the DC bias voltage (V _SUB ) ( a) measuring device; And (b1) Based on the measurement result performed by the measuring device, the CV characteristic indicating the relationship between the DC bias voltage Vg and the capacitance C is determined, and the DC bias is determined based on the CV characteristic. Determining a flat band capacitance (C _FB ) per unit area of the gate electrode at the point where the voltage (Vg) becomes equal to the flat band voltage (V _FB ); (b2) Applying a DC bias voltage (V _SUB ) to a plurality of MOSFET substrates having the same overlapping length (L _SD ), the same gate width (W), and different gate lengths (Lg), the gate and source or drain Applying a DC bias voltage (Vg), a DC bias voltage (V _SUB ), and an AC voltage to a human, while varying the DC bias voltage (V _SUB ), the gate voltage (Vg) at V _SUB + V _FB , the Measuring a capacitance C _GSUB formed on a gate and the substrate; (b3) determining a built-in potential (Vbi) between the substrate and the source or drain; And (b4) The overlapping length L based on the C _FB × (Lg-2L _SD ) intercept on the C _GSUB axis in the regression line obtained by plotting the capacity C _GSUB with respect to (Vbi-V _SUB ) ^1/2 . _SD ) having a function of determining; (b) An overlapping length measuring device for a MOSFET having a processor. In the overlapping length measuring apparatus of a MOSFET, an overlapping length is defined as a length of an overlapping region measured in the longitudinal direction of a gate, and the overlapping region is defined as an overlapping region with a diffusion region in which the gate becomes a source or a drain. (a1) When the CV characteristic of the MOS capacitor pattern is measured, an AC voltage and a DC bias voltage (Vg) are applied between the gate electrode formed on the diffusion layer having the MOS capacitor pattern and the substrate, and between the gate electrode and the diffusion layer. Measuring a current flowing through the voltage applied between the gate electrode and the diffusion layer; (a2) When the capacitance Cgc between each gate and source or drain of a plurality of MOSFETs having different gate lengths is measured, a DC bias voltage V _SUB is applied to the substrate, and the gate and the drain or A current flowing between the gate and the source or drain while varying the DC bias voltage Vg or the DC bias voltage V _SUB applied to the substrate by applying a DC bias voltage Vg and an AC voltage between the sources. (A) measuring device for measuring; And (b1) Based on the measurement result performed by the measuring device, the CV characteristic indicating the relationship between the DC bias voltage Vg and the capacitance C is determined, and the DC bias is determined based on the CV characteristic. Determining a flat band capacitance (C _FB ) per unit area of the gate electrode at the point where the voltage (Vg) becomes equal to the flat band voltage (V _FB ); (b2) DC bias voltage (Vg) and AC voltage between each gate and source or drain of a plurality of MOSFETs having the same overlapping length (L _SD ), the same gate width (W), and different gate lengths (Lg). Is applied, and the current flowing between the gate and the source or the drain is measured while varying the DC bias voltage (Vg) as a gate voltage, and the capacitance between the gate and the source or the drain, respectively, based on the result of the current measurement. A function of determining a plurality of Cgc-Vg characteristics indicative of the relationship between Cgc and the gate voltage Vg; (b3) Based on the Cgc-Vg characteristics, the capacitance Cgc associated with the gate length Lg is determined at the gate voltage Vg at which the capacitance Cgc is saturated, and the determined capacitance Cgc is determined. Plotting the Cgc-Lg characteristics to determine the characteristics; (b4) determining a gate fringe capacitance C _FL based on the intercept on the Cgc axis of the Cgc-Lg characteristic; (b5) The capacitance defined as the capacitance Cgc respectively measured when the gate voltage Vg becomes zero (Vg = 0) while varying the DC bias voltage V _SUB applied to each substrate of the MOSFET. Determining (C _GSD ); (b6) determining a built-in potential (Vbi) between the substrate and the source or drain; And minimal _{- ((Vbi-V SUB)} 1/2 C GSD) determining a property, and the capacitance _{(C GSD) (b7) (} Vbi-V SUB) with respect to the ^half by the floating capacitance (C _GSD) wherein - on the basis of being a _{(C GSD (Vbi-V SUB} ) 1/2) in the characteristic (C _{FB SD} × L × W _FL + 2C), which has a function of determining the overlapping length (L _SD) (b Overlap length measuring device of MOSFET with processor. A computer-readable recording medium storing a program for causing a computer to execute the method defined in any one of claims 1 to 7. 15. A computer-readable recording medium having stored thereon a program for acting as a device as defined in any one of claims 8-14.