[go: up one dir, main page]

KR100334528B1 - Capacitor Manufacturing Method of Ferroelectric Ram - Google Patents

Capacitor Manufacturing Method of Ferroelectric Ram Download PDF

Info

Publication number
KR100334528B1
KR100334528B1 KR1019980044246A KR19980044246A KR100334528B1 KR 100334528 B1 KR100334528 B1 KR 100334528B1 KR 1019980044246 A KR1019980044246 A KR 1019980044246A KR 19980044246 A KR19980044246 A KR 19980044246A KR 100334528 B1 KR100334528 B1 KR 100334528B1
Authority
KR
South Korea
Prior art keywords
film
iro
feram
capacitor manufacturing
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019980044246A
Other languages
Korean (ko)
Other versions
KR20000026632A (en
Inventor
조준희
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1019980044246A priority Critical patent/KR100334528B1/en
Publication of KR20000026632A publication Critical patent/KR20000026632A/en
Application granted granted Critical
Publication of KR100334528B1 publication Critical patent/KR100334528B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/694—Electrodes comprising noble metals or noble metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Semiconductor Memories (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 강유전체 램(ferroelectric RAM, 이하 FeRAM이라 함)의 캐패시터 제조방법에 관한 것으로, 전극 재료로 IrO2막 또는 Ir/IrO2막을 사용하는 경우 Ar과 Cl2혼합가스를 이용한 플라즈마 식각공정을 실시함으로써 식각율을 향상시켜 식각공정을 용이하게 실시하여 저장전극의 전기적 특성이 우수하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 기술에 관한 것이다.The present invention relates to a method for manufacturing a capacitor of a ferroelectric RAM (hereinafter referred to as FeRAM), and when using an IrO 2 film or an Ir / IrO 2 film as an electrode material, a plasma etching process using Ar and Cl 2 mixed gas is performed. The present invention relates to a technique for improving an etching rate by easily performing an etching process to improve electrical characteristics of a storage electrode and thereby to improve characteristics and reliability of a semiconductor device.

Description

강유전체 램의 캐패시터 제조방법Capacitor Manufacturing Method of Ferroelectric Ram

본 발명은 FeRAM의 캐패시터 제조방법에 관한 것으로서, 특히 IrO2막을 전극재료로 사용하는 경우에 상기 IrO2막을 Cl2/Ar 혼합가스를 사용하여 식각함으로써 소자의 특성 및 신뢰성을 향상시킬 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of FeRAM. In particular, in the case where an IrO 2 film is used as an electrode material, the IrO 2 film is etched using Cl 2 / Ar mixed gas to improve the characteristics and reliability of the device. It is about.

일반적으로, 반도체소자의 고집적화가 증가됨에 따라 캐패시터의 고정전용량이 요구되고 있다. 이를 해결하기 위해 캐패시터의 유전상수가 높은 물질을 사용하거나 유전체막의 두께를 얇게 하거나 전하저장전극의 표면적을 증대시키는 방법 등이 대두되고 있다. 이를 해결하기 위한 방안 중의 하나로서 높은 유전상수를 갖는 물질을 적용하려는 시도가 이루어지고 있다.In general, as the high integration of semiconductor devices increases, a fixed capacitance of a capacitor is required. In order to solve this problem, a method of using a material having a high dielectric constant of a capacitor, reducing the thickness of a dielectric film, or increasing the surface area of a charge storage electrode has emerged. In order to solve this problem, attempts have been made to apply a material having a high dielectric constant.

상기와 같이 유전상수가 높은 물질 중에 하나로 PZT(Pb(ZrTi1-x)O3), BST((Ba1-xSrx)TiO3), Y-1(SrBi2Ta2O9) 등과 같은 물질은 상온에서 유전상 수가 수백에서 수천에 이르며 두 개의 안정한 잔류분극(remainent polarization) 상태를 갖는 강유전체로 박막화하여 비휘발성(nonvolatile)메모리인 FeRAM(Ferroelectric RAM) 소자 개발에 적용되고 있다.One of the materials having a high dielectric constant, such as PZT (Pb (ZrTi 1-x ) O 3 ), BST ((Ba 1-x Sr x ) TiO 3 ), Y-1 (SrBi 2 Ta 2 O 9 ) The material has been applied to the development of FeRAM (Ferroelectric RAM) devices, which are nonvolatile memories, by thinning them into ferroelectrics having a dielectric constant ranging from hundreds to thousands at room temperature and having two stable residual polarization states.

상기와 같은 종래기술에 따른 반도체소자의 캐패시터에서 유전체막으로 Y-1을 사용하는 경우 전극물질로 Pt막을 사용하나, 상기 PZT를 사용하는 경우에는 퍼티그(fatigue)문제로 전극물질로 IrO2막을 사용하지만 상기 Pt막보다 식각하기 어려운 문제점이 있다.When using Y-1 as the dielectric film in the capacitor of the semiconductor device according to the prior art as described above, a Pt film is used as an electrode material. However, when PZT is used, an IrO 2 film is used as an electrode material due to a puttig problem. Although it is used, there is a problem that is difficult to etch than the Pt film.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, Ar/Cl2혼합가스를 사용하여 전극물질인 IrO2막을 용이하게 식각하고, 식각잔류물의 발생을 최소화함으로써 소자의 특성 및 신뢰성을 향상시키는 FeRAM의 캐패시터 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the FeRAM to easily etch the IrO 2 film, which is an electrode material using Ar / Cl 2 mixed gas, and to improve the characteristics and reliability of the device by minimizing the generation of etching residues It is an object of the present invention to provide a capacitor manufacturing method.

도 1 내지 도 3 은 본 발명에 따른 FeRAM의 캐패시터 제조방법을 도시한 단면도.1 to 3 are cross-sectional views showing a capacitor manufacturing method of FeRAM according to the present invention.

도 4 는 본 발명에 따라 식각된 IrO2막의 식각상태도.Figure 4 is an etching state of the IrO 2 film etched in accordance with the present invention.

도 5 는 본 발명에 따라 Cl2가스를 식각가스로 사용하였을 때의 IrO2막의 식각률을 도시한 그래프도.5 is a graph showing the etching rate of an IrO 2 film when Cl 2 gas is used as an etching gas according to the present invention.

〈도면의 주요부분에 대한 부호 설명〉<Explanation of symbols on main parts of the drawing>

11 : 층간절연막 13 : IrO2막11 interlayer insulating film 13 IrO 2 film

15 : 감광막 패턴15 photosensitive film pattern

이상의 목적을 달성하기 위하여 본 발명에 따른 FeRAM의 캐패시터 제조방법은,In order to achieve the above object, a capacitor manufacturing method of FeRAM according to the present invention,

FeRAM의 캐패시터 제조방법에 있어서,In the capacitor manufacturing method of FeRAM,

전극물질인 IrO2막 상부에 전극으로 예정되는 부분을 보호하는 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the IrO 2 film as an electrode material to protect a portion intended as an electrode;

상기 감광막패턴을 식각마스크로 사용하고, Cl2/Ar 혼합가스를 식각가스로 사용하여 상기 IrO2막을 플라즈마식각하는 공정과,Plasma etching the IrO 2 film using the photoresist pattern as an etching mask and Cl 2 / Ar mixed gas as an etching gas;

상기 감광막패턴을 제거하는 공정을 포함하는 것을 특징으로 한다.It characterized in that it comprises a step of removing the photosensitive film pattern.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 3 은 본 발명에 따른 FeRAM의 캐패시터 제조방법을 도시한 단면도이고, 도 4 는 본 발명에 의해 식각된 IrO2막의 식각상태도이다.1 to 3 are cross-sectional views illustrating a method of manufacturing a capacitor of FeRAM according to the present invention, and FIG. 4 is an etched state diagram of an IrO 2 film etched by the present invention.

먼저, 반도체기판(도시안됨) 상에 소자분리 산화막(도시안됨)과 게이트산화막(도시안됨)을 형성하고, 게이트전극(도시안됨)과 소오스/드레인전극(도시안됨)으로 구성되는 모스 전계효과 트랜지스터과 비트라인을 형성한 다음, 전체표면 상부에 층간절연막(11)을 형성한다.First, an MOS field effect transistor including a device isolation oxide film (not shown) and a gate oxide film (not shown) on a semiconductor substrate (not shown) and a gate electrode (not shown) and a source / drain electrode (not shown); After the bit lines are formed, an interlayer insulating film 11 is formed over the entire surface.

다음, 상기 층간절연막(11) 상부에 하부전극용 IrO2막(13)을 1500 ∼ 2500Å두께로 형성한다.Next, an IrO 2 film 13 for lower electrodes is formed on the interlayer insulating film 11 to a thickness of 1500 to 2500 Å.

그 다음, 상기 IrO2막(13) 상부에 하부전극으로 예정되는 부분을 보호하는 감광막 패턴(15)을 형성한다. 이때, 상기 감광막 패턴(15)은 0.5 ∼ 1.0㎛ 두께로 형성한다. (도 1참조)Next, a photosensitive film pattern 15 is formed on the IrO 2 film 13 to protect a portion intended as a lower electrode. At this time, the photosensitive film pattern 15 is formed to a thickness of 0.5 ~ 1.0㎛. (See Fig. 1)

다음, 상기 감광막 패턴(15)을 식각마스크로 사용하여 상기 IrO2막(13)을 식각하되, 30 ∼ 40%의 과도식각을 실시한다.Next, the IrO 2 film 13 is etched using the photoresist pattern 15 as an etching mask, and 30 to 40% transient etching is performed.

상기 식각공정은 5 ∼ 50sccm의 Ar가스와 5 ∼ 20sccm의 Cl2가스를 5 : 1 ∼ 2 : 1의 혼합비로 혼합한 가스와 500 ∼ 700W의 소오스 파워(source power)와 100 ∼ 300W의 바이어스 파워(bias power)를 사용하여 실시한다.The etching process is a mixture of 5 to 50 sccm Ar gas and 5 to 20 sccm Cl 2 gas at a mixing ratio of 5: 1 to 2: 1, source power of 500 to 700 W, and bias power of 100 to 300 W (bias power).

그리고, 상기 식각공정은 챔버의 온도가 70∼80℃이고, 압력이 3∼5mTorr인 식각조건에서 실시한다. 이때, 상기와 같이 고온에서 공정을 하는 이유는 식각공정시 발생하는 부산물인 IrCl4는 휘발성이 매우 강하기 때문이다. (도 2참조)The etching process is performed under etching conditions in which the temperature of the chamber is 70 to 80 ° C. and the pressure is 3 to 5 mTorr. At this time, the reason for the process at a high temperature as described above is that the by-product IrCl 4 generated during the etching process is very volatile. (See Fig. 2)

그 다음, 상기 감광막 패턴(15)을 제거하면, 도 4 와 같은 식각상태를 갖는다. (도 3, 도 4참조)Then, when the photosensitive film pattern 15 is removed, an etching state as shown in FIG. 4 is obtained. (See Figs. 3 and 4)

도 5 에 도시된 바와 같이 Cl2가스를 사용하여 상기 IrO2막을 식각하게 되면, 1600∼1800Å/분의 높은 식각률을 갖는다.As shown in FIG. 5, when the IrO 2 film is etched using Cl 2 gas, the etching rate of 1600 to 1800 μs / min is high.

한편, 실제 공정에서는 소자의 특성을 향상시키기 위하여 Ir/IrO2적층구조의 전극물질을 사용하는데, 상기 적층구조를 동시에 식각하기 위해 Cl2가스를 식각가스로 사용한다. 이때, 상기 Ir/IrO2적층구조의 전극물질을 사용함으로써 유전막인 PZT막에서 Pb가 Ir 내부로 확산되는 것을 방지할 수 있다.Meanwhile, in the actual process, an electrode material of an Ir / IrO 2 layered structure is used to improve device characteristics, and Cl 2 gas is used as an etching gas to simultaneously etch the layered structure. In this case, by using the electrode material of the Ir / IrO 2 stacked structure, it is possible to prevent Pb from diffusing into the Ir in the PZT film, which is a dielectric film.

이상에서 설명한 바와 같이 본 발명에 따른 FeRAM의 캐패시터 제조방법은, 전극 재료로 IrO2막 또는 Ir/IrO2막을 사용하는 경우 Ar과 Cl2혼합가스를 이용한 플라즈마 식각공정을 실시함으로써 식각율을 향상시켜 식각공정을 용이하게 실시하여 저장전극의 전기적 특성이 우수하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the FeRAM capacitor manufacturing method according to the present invention, when an IrO 2 film or an Ir / IrO 2 film is used as an electrode material, the etching rate is improved by performing a plasma etching process using a mixed gas of Ar and Cl 2. By performing the etching process easily, there is an advantage in that the electrical characteristics of the storage electrode are excellent and thus the characteristics and reliability of the semiconductor device are improved.

Claims (5)

FeRAM의 캐패시터 제조방법에 있어서,In the capacitor manufacturing method of FeRAM, 전극물질인 IrO2막 상부에 전극으로 예정되는 부분을 보호하는 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the IrO 2 film as an electrode material to protect a portion intended as an electrode; 상기 감광막패턴을 식각마스크로 사용하고, Cl2/Ar 혼합가스를 식각가스로 사용하여 상기 IrO2막을 플라즈마식각하는 공정과,Plasma etching the IrO 2 film using the photoresist pattern as an etching mask and Cl 2 / Ar mixed gas as an etching gas; 상기 감광막 패턴을 제거하는 공정을 포함하는 FeRAM의 캐패시터 제조방법.Capacitor manufacturing method of FeRAM comprising the step of removing the photosensitive film pattern. 제 1 항에 있어서,The method of claim 1, 상기 혼합가스는 5∼20sccm의 Cl2가스와 5∼50sccm의 Ar가스가 함유하는 것을 특징으로 하는 FeRAM의 캐패시터 제조방법.The mixed gas is a FeRAM capacitor manufacturing method, characterized in that containing 5 to 20sccm Cl 2 gas and 5 to 50sccm Ar gas. 제 1 항에 있어서,The method of claim 1, 상기 플라즈마식각공정은 500 ∼ 700W의 소오스 파워와 100 ∼ 300W의 바이어스 파워를 사용하여 실시되는 것을 특징으로 하는 반도체소자의 전하저장전극 제조방법.The plasma etching process is performed using a source power of 500 to 700W and a bias power of 100 to 300W. 제 1 항에 있어서,The method of claim 1, 상기 플라즈마식각공정은 챔버의 온도가 70∼80℃이고, 압력이 3∼5mTorr인 식각조건에서 실시되는 것을 특징으로 하는 FeRAM의 캐패시터 제조방법.The plasma etching process is a capacitor manufacturing method of a FeRAM, characterized in that the temperature of the chamber is 70 ~ 80 ℃, the pressure is carried out in the etching conditions of 3 to 5mTorr. 제 1 항에 있어서,The method of claim 1, 상기 플라즈마식각공정은 30∼40%의 과도식각공정으로 실시되는 것을 특징으로 하는 FeRAM의 캐패시터 제조방법.The plasma etching process is a capacitor manufacturing method of FeRAM, characterized in that the 30 to 40% transient etching process.
KR1019980044246A 1998-10-22 1998-10-22 Capacitor Manufacturing Method of Ferroelectric Ram Expired - Fee Related KR100334528B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019980044246A KR100334528B1 (en) 1998-10-22 1998-10-22 Capacitor Manufacturing Method of Ferroelectric Ram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980044246A KR100334528B1 (en) 1998-10-22 1998-10-22 Capacitor Manufacturing Method of Ferroelectric Ram

Publications (2)

Publication Number Publication Date
KR20000026632A KR20000026632A (en) 2000-05-15
KR100334528B1 true KR100334528B1 (en) 2002-09-05

Family

ID=19554935

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980044246A Expired - Fee Related KR100334528B1 (en) 1998-10-22 1998-10-22 Capacitor Manufacturing Method of Ferroelectric Ram

Country Status (1)

Country Link
KR (1) KR100334528B1 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990086483A (en) * 1998-05-28 1999-12-15 윤종용 Platinum group metal etching method and method for forming lower electrode of capacitor using same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990086483A (en) * 1998-05-28 1999-12-15 윤종용 Platinum group metal etching method and method for forming lower electrode of capacitor using same

Also Published As

Publication number Publication date
KR20000026632A (en) 2000-05-15

Similar Documents

Publication Publication Date Title
KR100465374B1 (en) Semiconductor device and its manufacturing method
US6432767B2 (en) Method of fabricating semiconductor device
KR20010109610A (en) A method for forming ferroelectric capacitor in semiconductor device
EP1455385A1 (en) Method for Forming FerroElectric Memory Capacitor
US6764896B2 (en) Semiconductor manufacturing method including patterning a capacitor lower electrode by chemical etching
KR100334528B1 (en) Capacitor Manufacturing Method of Ferroelectric Ram
KR100329612B1 (en) Capacitor Manufacturing Method of Semiconductor Device
KR0159013B1 (en) Capacitor Formation Method of Semiconductor Device
KR100457747B1 (en) Method for forming storage node of semiconductor device to improve electrical characteristic of storage node
KR20010026495A (en) Ferroelectric Memory Device and Fabrication Method Thereof
KR100337926B1 (en) Method of forming storage electrode of semiconductor device
KR100329759B1 (en) Method for forming ferroelectric capacitor
KR100324016B1 (en) Method for forming charge storage electrode of semiconductor device
KR100353805B1 (en) A method for forming capacitor in semiconductor device
KR100333641B1 (en) Method for forming capacitor of feram capable of preventing damage of bottom electrode
KR19990055813A (en) Method for forming charge storage electrode of semiconductor device
KR20040085805A (en) Method for electrode formation of semiconductor element
KR20020002570A (en) Method for forming ferroelectric memory device capable of preventing generation of ferroelectric capacitor degradation caused by reactive ion etching
KR100275337B1 (en) Manufacturing method for capacitor of fedram
KR20000025682A (en) Method for fabricating capacitor of ferroelectric ram
KR20000045366A (en) Method for fabricating storage electrode
KR20000042490A (en) Method for fabricating storage electrode of semiconductor device
KR20000025679A (en) Method for fabricating capacitor of ferro electric ram
KR20010004293A (en) Method for forming ferroelectric capacitor capable of preventing short between top and bottom electrode
KR20020002606A (en) Method for forming FeRAM by using plasma treatment for recovering degradation of ferroelectric capacitor

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

FPAY Annual fee payment

Payment date: 20100325

Year of fee payment: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20110417

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20110417

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000