KR100343462B1 - Chip size package - Google Patents
Chip size package Download PDFInfo
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- KR100343462B1 KR100343462B1 KR1019990055770A KR19990055770A KR100343462B1 KR 100343462 B1 KR100343462 B1 KR 100343462B1 KR 1019990055770 A KR1019990055770 A KR 1019990055770A KR 19990055770 A KR19990055770 A KR 19990055770A KR 100343462 B1 KR100343462 B1 KR 100343462B1
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- South Korea
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- chip
- heat sink
- substrate
- size package
- hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
본 발명 열방출이 용이한 칩 사이즈 패키지는 칩(12)의 하면에 밀착되도록 설치되는 히트 싱크(20)의 인서팅 바(20a)가 기판(11)에 형성된 히트 싱크 설치공(20a)에 삽입된 상태에서 인서팅 바(20a)의 단부에 솔더(21)를 형성하여 히트싱크(20)가 이탈되지 않도록 고정함으로써, 패키지의 동작시 칩에서 발생되는 열이 직접 히트 싱크를 통하여 충분히 방출된다.In the chip size package of the present invention, the insert bar 20a of the heat sink 20, which is installed to be in close contact with the bottom surface of the chip 12, is inserted into the heat sink installation hole 20a formed in the substrate 11. In this state, the solder 21 is formed at the end of the inserting bar 20a to fix the heat sink 20 so that the heat sink 20 is not separated, so that the heat generated from the chip during the operation of the package is sufficiently discharged through the heat sink.
Description
본 발명은 열방출이 용이한 칩 사이즈 패키지에 관한 것으로, 특히 반도체 칩에서 발생되는 열을 히트 싱크를 통하여 충분히 방출할 수 있도록 하는데 적합한 열방출이 용이한 칩 사이즈 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip size package that is easy to dissipate heat, and more particularly to a chip size package that is easy to dissipate heat, which is suitable for dissipating heat generated in a semiconductor chip through a heat sink.
종래 칩 사이즈 패키지의 일예가 도 1에 도시되어 있는 바, 이를 간단히 설명하면 다음과 같다.An example of a conventional chip size package is illustrated in FIG. 1, which is briefly described as follows.
도시된 바와 같이, 종래 칩 사이즈 패키지는 사각 판체인 절연성의 기판(1) 상면 중앙에 접착제(2)로 반도체 칩(3)이 고정부착되어 있고, 그 칩(3)의 칩패드(미도시)들은 칩(3)의 주변에 형성되는 본드 핑거(4)와 금속와이어(5)로 전기적인 연결이 각각 이루어져 있고, 그 본드 핑거(4)는 기판(1)의 측면에 설치된 아웃리드(6)들에 시그널 라인(7)으로 연결되어 있으며, 상기 칩(3), 금속와이어(5)를 감싸도록 기판(1)의 상면에는 봉지제(8)가 몰딩되어 있다.As shown in the drawing, the conventional chip size package has a semiconductor chip 3 fixedly attached to the center of an upper surface of an insulated substrate 1, which is a rectangular plate, with an adhesive 2, and a chip pad (not shown) of the chip 3. The electrical connection is made to each of the bond fingers 4 and the metal wires 5 formed around the chip 3, and the bond fingers 4 are arranged on the side of the substrate 1. And an encapsulant 8 is molded on the upper surface of the substrate 1 to surround the chip 3 and the metal wire 5.
상기와 같이 구성되어 있는 종래 칩 사이즈 패키지는 기판(1)의 상면에 접착제(2)를 이용하여 반도체 칩(3)을 고정부착하는 다이본딩작업을 실시하고, 그 칩(3)의 칩패드(미도시)와 기판(1)의 상면에 형성된 본드 핑거(4)를 금속와이어(5)로 연결하는 와이어본딩작업을 실시하며, 상기 칩(3), 금속와이어(5)를 감싸도록 기판(1)의 상면에 봉지제(8)를 몰딩하여 패키지를 완성한다.In the conventional chip size package configured as described above, the die bonding operation for fixing and attaching the semiconductor chip 3 to the upper surface of the substrate 1 using the adhesive agent 2 is carried out, and the chip pad of the chip 3 ( The wire bonding operation for connecting the bond finger 4 formed on the upper surface of the substrate 1 with the metal wire 5 is performed, and the substrate 1 is wrapped around the chip 3 and the metal wire 5. The package is molded by molding the encapsulant (8) on the upper surface.
그러나, 상기와 같이 구성되어 있는 종래 칩 사이즈 패키지는 패키지의 동작시 칩(3)에서 발생되는 신호는 금속와이어(5)→시그널 라인(7)→아웃리드(6)를 통하여 외부로 전달됨과 아울러 칩(3)에서 발생되는 열도 동일한 경로를 통하여 주로 외부로 방출되는데, 칩(3)들이 고집적화됨에 따라 충분한 열방출이 이루어지지 못하여 패키지의 오동작을 유발시키는 문제점이 있었다.However, in the conventional chip size package configured as described above, the signal generated from the chip 3 during the operation of the package is transmitted to the outside through the metal wire 5 → the signal line 7 → the outlead 6. Heat generated in the chip 3 is also mainly emitted to the outside through the same path, and as the chips 3 are highly integrated, sufficient heat dissipation is not achieved, which causes a malfunction of the package.
상기와 같은 문제점을 감안하여 안출한 본 발명의 목적은 충분한 열방출이 이루어지도록 하여 패키지의 오동작이 발생되는 것을 방지하도록 하는데 적합한 열방출이 용이한 칩 사이즈 패키지를 제공함에 있다.SUMMARY OF THE INVENTION An object of the present invention devised in view of the above problems is to provide a chip size package that is easily heat dissipated to prevent a malfunction of the package by causing sufficient heat dissipation.
도 1은 종래 칩 사이즈 패키지의 구성을 보인 종단면도.1 is a longitudinal sectional view showing a configuration of a conventional chip size package.
도 2는 본 발명 열방출이 용이한 칩 사이즈 패키지의 구성을 보인 종단면도.Figure 2 is a longitudinal cross-sectional view showing the configuration of the chip size package easy heat dissipation of the present invention.
도 3은 본 발명에서의 기판을 보인 평면도.3 is a plan view showing a substrate in the present invention.
도 4는 본 발명에서의 히트 싱크를 보인 사시도.Figure 4 is a perspective view showing a heat sink in the present invention.
도 5a 내지 5g는 본 발명 열방출이 용이한 칩 사이즈 패키지의 제조순서를 보인 종단면도.Figures 5a to 5g is a longitudinal cross-sectional view showing the manufacturing process of the chip size package easy heat dissipation of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
11 : 기판 11a : 단차부11 substrate 11a stepped portion
11b : 관통부 11c : 히트 싱크 설치공11b: penetration part 11c: heat sink installation hole
12 : 칩 13 : 시그널 라인12 chip 13 signal line
15 : 금속와이어 16 : 아웃리드15 metal wire 16: out lead
17 : 봉지제 20 : 히트 싱크17: sealing agent 20: heat sink
20a : 인서팅 바 21 : 솔더20a: Inserting bar 21: Solder
상기와 같은 본 발명의 목적을 달성하기 위하여 중앙에 단차부와 관통공이 연속적으로 형성되어 있는 절연성 기판과, 그 관통공의 내부에 위치되는 반도체 칩과, 상기 기판의 내부에 내설됨과 아울러 단차부에 인출되어 있는 복수개의 시그널 라인과, 그 시그널 라인의 내측 단부와 반도체 칩의 칩패드를 전기적으로 연결하는 금속와이어와, 상기 시그널 라인의 외측단부에 연결됨과 아울러 기판의 측면에 일정간격을 두고 설치되는 복수개의 아웃리드와, 상기 칩의 하면에 밀착되도록 설치되어 칩에서 발생되는 열을 외부로 방출하기 위한 히트 싱크를 구비하되, 상기 히트 싱크의 본체부 4모서리 부분에는 일체로 인서팅 바가 설치되고, 기판의 4모서리 부분에는 각각 히트 싱크 설치공이 형성되어 있어서, 상기 히트 싱크 설치공에 인서팅 바를 삽입한 상태에서 단부에 솔더를 형성하여 고정할 수 있도록 한 것을 특징으로 하는 열방출이 용이한 칩 사이즈 패키지가 제공된다.In order to achieve the object of the present invention as described above, an insulating substrate having a stepped portion and a through hole continuously formed in the center, a semiconductor chip positioned inside the through hole, and embedded in the substrate, A plurality of drawn signal lines, metal wires electrically connecting the inner ends of the signal lines and the chip pads of the semiconductor chip, and connected to the outer ends of the signal lines and provided at regular intervals on the side of the substrate; A plurality of outleads and a heat sink installed to be in close contact with the lower surface of the chip to discharge heat generated from the chip to the outside, and an inserting bar is integrally installed at the four corners of the main body of the heat sink; Heat sink mounting holes are formed in each of the four corners of the substrate, and an insert bar is inserted into the heat sink mounting holes. Provided is a heat dissipation easy chip size package which can be fixed by forming solder at the end in a state.
이하, 상기와 같이 구성되는 본 발명 열방출이 용이한 칩 사이즈 패키지를 첨부된 도면의 실시예를 참고하여 보다 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in more detail with reference to the embodiment of the accompanying drawings, the chip size easy heat dissipation package configured as follows.
도 2는 본 발명 열방출이 용이한 칩 사이즈 패키지의 구성을 보인 종단면도이고, 도 3은 본 발명에서의 기판을 보인 평면도이며, 도 4는 본 발명에서의 히트 싱크를 보인 사시도로서, 도시된 바와 같이, 본 발명 열방출이 용이한 칩 사이즈 패키지는 중앙에 단차부(11a)와 관통공(11b)가 연속적으로 형성된 기판(11)의 관통공(11b)에는 반도체 칩(12)이 위치되어 있고, 그 반도체 칩(12)의 패드(미도시)와 상기 기판(11)에 내설된 시그널 라인(13)의 내측 단부에 형성된 본드 핑거(14)는 금속와이어(15)로 연결되어 있으며, 그 시그널 라인(13)의 외측 단부는 기판(11)의 측면에 등간격으로 나열형성된 아웃리드(16)에 연결되어 있고, 상기 칩(12), 금속와이어(15)를 감싸도록 단차부(11a)와 관통공(11b)의 내부에는 봉지제(17)가 몰딩되어 있고, 상기 반도체 칩(12)의 하면에 밀착되도록 열방출이 잘되는 금속판재인 히트 싱크(20)가 설치되어 있다.Figure 2 is a longitudinal cross-sectional view showing the configuration of a chip size package easy to heat dissipation of the present invention, Figure 3 is a plan view showing a substrate in the present invention, Figure 4 is a perspective view showing a heat sink in the present invention, As described above, in the chip size package of the present invention, the semiconductor chip 12 is positioned in the through hole 11b of the substrate 11 in which the stepped portion 11a and the through hole 11b are continuously formed in the center. The pad (not shown) of the semiconductor chip 12 and the bond finger 14 formed at the inner end of the signal line 13 in the substrate 11 are connected by a metal wire 15. The outer end of the signal line 13 is connected to an outlead 16 arranged at equal intervals on the side of the substrate 11, and has a stepped portion 11a so as to surround the chip 12 and the metal wire 15. The encapsulant 17 is molded in the inside of the through hole 11b and is in close contact with the bottom surface of the semiconductor chip 12. There is a well plate recognition heat sink 20 rock heat is installed.
상기 기판(11)은 사각 판체상으로된 절연성 판재로 되어 있으며, 그 4모서리 부분에는 각각 상기 히트 싱크(20)를 설치하기 위한 히트 싱크 설치공(11c)이 형성되어 있다.The board | substrate 11 is made of the insulating plate-shaped board | substrate shape, and the heat sink installation hole 11c for installing the said heat sink 20 is formed in the four corner parts, respectively.
상기 히트 싱크(20)는 사각형의 금속판재로된 본체부의 4모서리 부분에 상기 기판(11)에 형성된 히트 싱트 설치공(11c)에 삽입하기 위한 인서팅 바(20a)가 본체부에 일체로 형성되어 있고, 그와 같이 삽입되는 인서팅 바(20a)의 상단부는 솔더(21)가 부착되어 인서팅 바(20a)가 빠지지 않도록 함으로써 기판(11)에 히트 싱크(20)를 부착시킬 수 있도록 되어 있다.The heat sink 20 is integrally formed with an inserting bar 20a for inserting into the heat sink mounting hole 11c formed in the substrate 11 at four corners of the main body portion made of a rectangular metal plate. The upper end of the insert bar 20a inserted as described above is attached to the substrate 21 by attaching the solder 21 to prevent the insert bar 20a from being pulled out. have.
상기와 같이 구성되어 있는 열방출이 용이한 칩 사이즈 패키지의 제조는 패키지의 본체이 기판(11)을 미리 준비하는 기판제작작업과 그와 같이 준비된기판(11)을 이용하여 패키지를 조립하는 패키지조립작업의 순서로 진행된다.The manufacture of a chip size package with easy heat dissipation as described above includes a substrate fabrication operation in which the body of the package prepares the substrate 11 in advance, and a package assembly operation for assembling the package using the substrate 11 thus prepared. Proceeds in the order of.
먼저, 기판(11)은 일반적인 피시비(PCB: PRINTED CIRCUIT BOARD)의 제작순서와 마찬가지로 일정길이와 넓이를 갖는 절연성 판재를 다층으로 구성하며 내부에 시그널 라인(13)이 패터닝되도록 하고, 후가공을 실시하여 도 5a와 같이 단차부(11a)와 관통공(11b) 및 히트 싱크 설치공(11c)이 형성되도록 한다.First, the substrate 11 is composed of an insulating plate having a certain length and width in a multi-layered manner, as in the manufacturing process of the general PCB (PCB: PRINTED CIRCUIT BOARD), the signal line 13 is patterned therein, and then subjected to post-processing As shown in FIG. 5A, the stepped portion 11a, the through hole 11b, and the heat sink installation hole 11c are formed.
상기와 같이 제작된 기판(11)의 하면에 5b에서와 같이 사각 판체상인 기판(11)에 형성된 관통공(11b)의 하측을 완전히 막을 수 있도록 열가소성 테이프(30)를 부착하고, 도 5c에서와 같이, 상기 테이프(30)에 부착됨과 아울러 상기 관통공(11b)의 내부에 위치되도록 반도체 칩(12)을 설치하는 다이본딩을 실시한다.The thermoplastic tape 30 is attached to the lower surface of the substrate 11 manufactured as described above so as to completely block the lower side of the through hole 11b formed in the square plate-like substrate 11 as in 5b, Similarly, die bonding is performed to install the semiconductor chip 12 to be attached to the tape 30 and positioned inside the through hole 11b.
상기와 같이 반도체 칩(12)이 설치된 기판(11)은 와이어본더로 이동하여 도 5d에서와 같이 반도체 칩(12)의 칩패드(미도시)와 시그널 라인(13)에 형성된 본드 핑거(14)가 전기적으로 연결되도록 금속와이어(15)로 연결하는 와이어본딩을 실시한다.As described above, the substrate 11 having the semiconductor chip 12 installed thereon moves to the wire bonder and bonds 14 formed on the chip pad (not shown) and the signal line 13 of the semiconductor chip 12 as shown in FIG. 5D. Wire bonding is performed to connect the metal wires 15 so as to be electrically connected to each other.
상기와 같이 와이어본딩이된 상태에서 몰딩장비로 이동하여 칩(12)과 금속와이어(15)를 감싸도록 단차부(11a)와 관통공(11b)의 내측에 에폭시와 같은 봉지제(17)를 몰딩하고, 기판(11)의 하면에 부착되어 있던 테이프(30)을 도 5f와 같이 떼어낸다.As described above, the encapsulant 17 such as epoxy is disposed inside the stepped portion 11a and the through hole 11b to move to the molding equipment to surround the chip 12 and the metal wire 15 in the wire bonding state. Molding is carried out, and the tape 30 attached to the lower surface of the board | substrate 11 is peeled off like FIG. 5F.
상기와 같이 테이프(30)를 떼어내어 칩(12)의 하면이 노출된 상태에서 히트 싱크(20)가 칩(12)의 하면에 밀착되도록 기판(11)의 하면에 히트 싱크(20)를 설치함과 동시에 히트 싱크(20)의 인서팅 바(20a)를 기판(11)의 히트싱크 설치공(11c)에 삽입시킨 상태에서 인서팅 바(20a)의 단부에 각각 솔더(21)를 형성하여 히트 싱크(20)가 칩(12)에 밀착된 상태로 기판(11)에서 떨어지지 않도록 함으로써, 본 발명의 열방출이 용이한 칩 사이즈 패키지가 완성된다.The heat sink 20 is installed on the bottom surface of the substrate 11 so that the heat sink 20 adheres to the bottom surface of the chip 12 while the tape 30 is removed and the bottom surface of the chip 12 is exposed as described above. At the same time, the solder bar 21 is formed at each end of the insert bar 20a while the insert bar 20a of the heat sink 20 is inserted into the heat sink mounting hole 11c of the substrate 11. By preventing the heat sink 20 from falling off from the substrate 11 in a state in which the heat sink 20 is in close contact with the chip 12, the chip size package that facilitates heat dissipation of the present invention is completed.
이상에서 상세히 설명한 바와 같이, 본 발명 열방출이 용이한 칩 사이즈 패키지는 칩의 하면에 히트 싱크가 밀착되도록 설치하여 칩에서 발생되는 열이 히트 싱크를 통하여 충분히 방출되도록 함으로써, 충분한 열방출이 이루어지지 못하여 패키지의 오동작이 발생되는 것을 방지할 수 있는 효과가 있다.As described in detail above, the heat dissipation chip size package of the present invention is installed so that the heat sink is in close contact with the bottom surface of the chip so that the heat generated from the chip is sufficiently discharged through the heat sink, so that sufficient heat dissipation is not achieved. There is an effect that can prevent the malfunction of the package occurs.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990055770A KR100343462B1 (en) | 1999-12-08 | 1999-12-08 | Chip size package |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990055770A KR100343462B1 (en) | 1999-12-08 | 1999-12-08 | Chip size package |
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| KR20010054797A KR20010054797A (en) | 2001-07-02 |
| KR100343462B1 true KR100343462B1 (en) | 2002-07-11 |
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| KR1019990055770A Expired - Fee Related KR100343462B1 (en) | 1999-12-08 | 1999-12-08 | Chip size package |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108346587A (en) * | 2017-01-25 | 2018-07-31 | 新加坡有限公司 | Chip package device and packaging method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960019678A (en) * | 1994-11-04 | 1996-06-17 | 황인길 | How to attach heat sink and lead frame of semiconductor package |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960019678A (en) * | 1994-11-04 | 1996-06-17 | 황인길 | How to attach heat sink and lead frame of semiconductor package |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108346587A (en) * | 2017-01-25 | 2018-07-31 | 新加坡有限公司 | Chip package device and packaging method |
| US10937767B2 (en) | 2017-01-25 | 2021-03-02 | Inno-Pach Technology Pte Ltd | Chip packaging method and device with packaged chips |
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| KR20010054797A (en) | 2001-07-02 |
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