KR100357015B1 - Cdma base station transmission power controller, base station apparatus using the same, and tpc timing method - Google Patents

Abstract

By the CDMA base station transmission power controller, it is possible to provide a circuit for controlling the timing of insertion of the transmission power control bits, and to perform power control with high accuracy. Such a transmission power controller controls transmission power of a transmission station by using transmission control bits sequentially transmitted from the reception station to the transmission station. The transmit power controller measures the allowable time until the downlink TPC bit is reflected in the transmit data. When a propagation delay occurs, the TPC timing measuring unit reflects the TPC bit in the insertion timing of the transmission power control bit.

Description

CDMA base station transmission power controller, base station apparatus and TPC timing method using the same {CDMA BASE STATION TRANSMISSION POWER CONTROLLER, BASE STATION APPARATUS USING THE SAME, AND TPC TIMING METHOD}

The present invention relates to a CDMA base station transmission power controller, a base station apparatus using the same, and a TPC timing method.

In the conventional code division multiple access (hereinafter referred to as CDMA) scheme, there is a risk of far to near problems. The perspective problem is that interference from a mobile station located close to the base station makes it impossible to receive a signal from another mobile station. In the CDMA system, when the signal level from the mobile station located close to the base station is high, interference occurs in the uplink circuit from the mobile station to the base station. In this manner, the base station can receive the same level of signal from any mobile station by controlling the transmission power of each mobile station. For this reason, it is necessary to control the transmission power of each mobile station so that the base station can receive the same level of signal from any mobile station. Transmission power control is a technique that allows signals of the same level to be received from any mobile station. This transmission power control technique solves the perspective problem. Transmit power control is an indispensable technique for increasing subscriber capacity.

In the uplink circuit in the mobile communication system, it is necessary to control and maintain the transmission power of the mobile station at high speed so that the reception power from each mobile station is equalized. Slot is a unit of transmit power control. The base station compares a predetermined reference SIR (signal-to-interference power ratio) and uplink SIR measurements against the received power in the slot. The base station instructs the mobile terminal to up / down the transmit power so that the received power matches the reference power value. In the CDMA system, communication is performed at the same frequency. For this reason, mutual interference occurs in the CDMA scheme. The communication quality is determined by such mutual interference. The transmit power from the base station should be the minimum power that can guarantee the quality of the communication. Radio waves from a base station ensure that radio waves from a particular mobile station do not interfere with other mobile stations. This increases subscriber capacity (number of subscribers per area).

Therefore, in the CDMA system, it is necessary to perform power control with high accuracy. In order to perform the high-precision power control as described above, it is very important to properly operate the circuit which controls the insertion timing of the transmission power control bits (hereinafter referred to as TPC bits).

In particular, it is necessary to reflect the SIR measurement result of the uplink transmission power in the downlink TPC bit. If there is no time to reflect the SIR measurement result of the uplink transmission power in the downlink TPC bits, in some cases it is impossible to insert the correct TPC bits in the slot unit, resulting in deterioration of the precision of the power control of the mobile station.

For this reason, the present invention provides a circuit capable of measuring the time interval between the time when the uplink SIR measurement is confirmed and the TPC insertion time of the downlink transmission data. This measures the current allowable time interval until downlink TPC bit insertion. The circuit adjusts the SIR measurement time corresponding to the allowable time interval.

In view of the foregoing, it is an object of the present invention to solve the above-mentioned problem, and to solve the above-mentioned problems, including a CDMA base station transmission power controller, a base station apparatus having this controller, and a downlink TPC bit until it is inserted into transmission data. It is to provide a TPC timing method capable of measuring the allowable time and adjusting the SIR measurement time.

According to a first aspect of the present invention, in order to achieve the above object, a code division multiple access (CDMA) base station for controlling transmission power of a transmission station by using transmission power control bits sequentially transmitted from a reception station to a transmission station. As a transmission power controller, a TPC (transmission power control) which measures an allowable time until a downlink TPC bit is reflected in the transmission data and reflects the TPC bit in transmission data at an insertion timing when a propagation delay occurs. CDMA base station transmit power controller comprising timing measuring means.

According to a second aspect of the invention, in a first aspect, an uplink / downlink TPC bit generator consisting of despreading means, a demodulator for demodulating an output signal from the despreading means, and an SIR calculator is used to determine the number of received digital signals. A code division multiple access (CDMA) base station transmit power controller is provided.

According to a third aspect of the present invention, in a second aspect, the uplink TPC bits are extracted in parallel from the received signal despread by the uplink / downlink TPC bit generator through the demodulator and the uplink There is provided a CDMA (Code Division Multiple Access) base station transmit power controller further comprising uplink TPC bit extraction means for outputting the TPC in series.

According to a fourth aspect of the present invention, in a second or third aspect, CDMA (Code Division Multiple Access) further includes a downlink TPC bit determiner for processing the output signal from the uplink / downlink TPC bit generator in parallel. A base station transmit power controller is provided.

According to a fifth aspect of the present invention, in a fourth aspect, there is provided a CDMA (Code Division Multiple Access) base station transmission power controller in which the TPC timing measuring means outputs in parallel a parallel signal from the TPC bit determiner.

According to a sixth aspect of the present invention, in any one of the first to fifth aspects, the TPC timing measuring means stores a timing position at the time of inputting the downlink TPC bit, and stores the timing position to the generated clock. A first counter latching and counting by; A second counter for outputting an input position of the downlink transmission data TPC; And calculating a difference between the output value of the counter value from the first counter and the TPC of the current transmission data from the second counter to determine the timing position at the time of the downlink TPC bit input and the downlink transmission data TPC. A code division multiple access (CDMA) base station transmit power controller is provided that includes a TPC tolerance time calculator that compares each of the input positions with a predetermined value.

According to a seventh aspect of the invention, in the sixth aspect, the TPC timing measuring means includes:

A monitor for determining the presence or absence of insertion of a TPC bit into downlink transmission data according to the output from the comparing means; A status bad notification register for notifying both an adjustment of an SIR measurement time from the monitor and an over slot unit flag; And a TPC timing adjusting unit which outputs the previously informed adjustment of the SIR measurement time and outputs the slot-information excess flag notified in advance.

According to an eighth aspect of the present invention, there is provided a base station apparatus having a CDMA base station transmission power controller described in any of the first to seventh aspects.

According to the ninth aspect of the present invention, the TPC timing is measured in which the allowable time until the downlink TPC bit is reflected in the transmission data, and the TPC bit is reflected in the transmission data at the instant insertion timing even when a propagation delay occurs. A method is provided.

The above and other objects and novel features of the present invention will be more fully understood with reference to the accompanying drawings. It is to be understood, however, that the drawings are for illustrative purposes only and are not intended to limit the invention.

1 is a diagram showing a configuration of a first embodiment of a base station apparatus according to the present invention.

Fig. 2 is a diagram showing the configuration of a TPC timing measuring unit used in the first embodiment of the base station apparatus according to the present invention.

3 is a block diagram showing timing of a TPC timing measuring unit.

4 is a diagram showing the configuration of a second embodiment of a base station apparatus according to the present invention;

5 shows serial bus data fetched in the format (TPC indication).

Fig. 6 is a flowchart related to the TPC timing measuring unit in the first embodiment of the base station apparatus according to the present invention.

7 is a flowchart of a second embodiment of a base station apparatus according to the present invention;

<Explanation of symbols for the main parts of the drawings>

2: transceiver

3: receiving wireless unit

4: despreading unit

5: demodulator

6: Upstrip TPC Bit Extractor

7: transmit power controller

8: desired wave reception power detector

9: interference wave receiving power detector

10: SIR Calculator

11: downstream TPC bit determiner

12: TPC timing measuring unit

13: signal generator

14: modulator

15: diffusion part

16 transmission radio unit

Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Until the downlink TPC bit is reflected in the transmission data, a time interval, which is an allowable time interval, is required. The CDMA base station transmit power controller according to the present invention measures the allowable time interval until the downlink TPC bits are reflected in the transmit data. Occasionally, propagation delay occurs in the CDMA system. According to the circuit of the present invention, even when a propagation delay occurs, it is possible to immediately reflect the TPC bit in the insertion timing.

The downlink TPC bit of the user is input to the TPC timing measuring unit 12 in the apparatus having the CDMA base station transmission power controller. The CDMA base station transmit power controller according to the present invention latches the downlink TPC bit. Downlink TPC bits may be inserted using the allowed time interval at the TPC bit insertion position in the predetermined transmission data format. The CDMA base station transmit power controller measures this allowed time interval to determine whether the downlink TPC bits can be inserted at the TPC bit insertion position. Always observe the permissible time. The CDMA base station transmit power controller adjusts the SIR measurement time to enable timing adjustment of the TPC bit insertion. The base station apparatus according to the present invention has the above-described transmission power controller.

As shown in FIG. 1, the user downlink TPC bits output from the downlink TPC bit determiner 11 are input to the TPC timing measuring unit 12. 2 shows the TPC allowable time calculator 12-4. The TPC allowable time calculator 12-4 measures the allowable time interval until the input downlink TPC bit is reflected in the transmission data. Thereby, the processing state of TPC insertion timing is grasped | ascertained. Therefore, the measurement time of SIR is adjusted. On the other hand, if a state failure occurs at the time of insertion timing, the state failure notification register section 12-6 shown in Fig. 2 is notified that a state failure has occurred.

As shown in Fig. 2, in the state failure notification register 12-6, after the flag for notifying the measurement of the state failure is set in the register, it is instructed to the TPC timing adjustment unit 12-7. The TPC timing adjusting unit 12-7 reflects the adjustment of the measurement time of the SIR and a defective state (missing slot, excess slot, etc.) in the TPC insertion timing. In the signal generation unit 13, the format of the transmission data including the TPC bit is performed.

[First Embodiment]

1 is a diagram showing the configuration of a first embodiment of a base station apparatus according to the present invention. As shown in FIG. 1, the base station apparatus according to the present invention includes an antenna 1, a transceiver 2, a reception radio 3, a despreader 4, a demodulator 5, and an uplink TPC bit. Extractor 6, transmit power controller 7, SIR calculator 10, downlink TPC bit determiner 11, TPC timing measurer 12, signal generator 13, modulator 14, spreading Section 15, and a transmitting radio section 16. In FIG. In addition, the despreader 4 includes a desired wave reception power detector 8 and an interference wave reception power detector 9.

The operation of such a base station apparatus will be described with reference to the drawings.

The signal transmitted from the mobile station is a spread signal. As shown in Fig. 1, the antenna 1 receives this spreading signal transmitted from the mobile station. The receiving radio section 3 inputs a spread signal through the transmission / reception separator 2. In the reception radio section 3, subsequent processing is performed. That is, a signal is received by the antenna 1 and input to the receiving radio section 3 through the transmission / reception separator 2. The signal then passes through a band pass filter (BPF) of the receiving radio 3. As the signal passes through a band pass filter (BPF), out-of-band components are removed from the signal. The received signal from which the out-of-band component has been removed is frequency converted. The local transmitter generates a signal capable of converting the frequency of the received signal from which the out-of-band component has been removed to the intermediate frequency band IF. The received signal is frequency converted to the intermediate frequency band IF by the signal generated by the local transmitter. The received signal is then compensated to the proper signal level by the automatic gain controller AGC after passing through the band pass filter BPF. The converted received signal is then quasi-synchronously detected and frequency converted to a baseband signal. The received signal frequency-converted into the baseband signal passes through the low pass filter (LPF) and then A / D converted to become a digital signal. Therefore, the digital signal is output from the reception radio section 3.

After passing through each of the circuits described above, the received digital signal is output from the receive radio section 3. The received digital signal is despread by the despreader 4. The despreader 4 then outputs the received digital signal as a narrowband modulated signal. The signal thus output is demodulated by the demodulator 5. The TPC bit is sent out from the mobile station. The TPC bit extraction section 6 extracts the TPC bits from the demodulated signal. This TPC bit is output to the transmit power controller 7. After the transmission power is determined based on the output TPC bits, control information is output to the transmission radio section 16.

On the other hand, the desired wave reception power detector 8 and the interference wave reception power detector 9 in the despreader 4 receive the desired wave reception power from the mobile station and the interference wave reception power for the desired wave. Is detected from the signal. Based on the detected desired wave reception power and the detected interference wave reception power, the SIR calculator 10 calculates a received SIR value of the signal from the mobile station. The received SIR value is compared with the target SIR value preset in the TPC bit determiner 11. If the received SIR value is smaller than the target SIR value, a control bit for generating an increase in transmission power is generated. If the received SIR value is larger than the target SIR value, a control bit for generating a decrease in transmission power is generated. .

As described above, the TPC timing measuring unit 12 measures the time until the downlink TPC bit is reflected in the transmission data. Therefore, the insertion timing process is managed. The downlink TPC bits are then output to the signal generator 13. When there is no allowable time for the TPC bit (or when the allowable time is insufficient), timing control is performed by adjusting the SIR measurement time. As shown in Fig. 2, the TPC timing measuring unit 12 includes an internal counter 12-1, a latching clock generator 12-2, a downlink transmission data TPC position output counter 12-3, and a TPC allowable time. The measuring unit 12-4, the monitor 12-5, the state bad notification register 12-6, and the TPC timing adjusting unit 12-7 are included.

The downlink TPC bit is input in the manner described above (step S1), and the timing position when the downlink TPC bit is input is set in the internal counter 12-1 (chip rate: speed above spreading bandwidth, unit Mcps). Remember (step S2). The latching clock generator 12-2 generates a clock. The counter value is latched using the clock generated from the latching clock generator 12-2 (step S3). The latched counter value is read using the clock generated by the latching clock generator 12-2 (step S4). From the downlink transmission data TPC position output counter 12-3, a position for outputting the TPC of the current transmission data is obtained. The allowable time calculator 12-4 calculates the difference between the timing position and the position where the TPC of the current transmission data is output (step S5).

According to the downlink transmission data, the timing of the TPC position is obtained. The difference in input timing with respect to the TPC bit is obtained. The monitor 12-5 determines the timing of the TPC position of the downlink transmission data when the difference value is smaller than the set threshold, and it is determined that the time until the TPC bit is inserted into the downlink transmission data is not sufficient. The difference from the input timing of the TPC bits is processed (step S6). The state failure notification register 12-6 notifies the TPC timing adjustment unit 12-7 of the adjustment of the SIR measurement time and the setting of the slot unit excess flag (step S7). If the difference value is larger than the set threshold value, the TPC bit is inserted into the downlink transmission data. This insertion of the TPC bit is notified to the TPC timing adjusting unit 12-7 via the state failure notification register 12-6, and the TPC bit is inserted into the downlink transmission data (step S8).

The configuration of the transmission frame containing the downlink TPC bits is implemented by the signal generator 13. The signal generator 13 outputs a transmission frame as a transmission signal to the modulator 14. That is, the signal generator 13 constructs a transmission frame including the downlink TPC bits transmitted from the TPC timing measuring unit 12, and outputs the transmission frame to the modulator 14 as a transmission signal. The transmission signal is modulated by the modulator 14. The modulated transmission signal is spread by the spreader 15. In other words, the output transmission signal is modulated by the modulator 14, then spread by the spreader 15, and output to the transmission radio section 16. FIG.

The transmission radio section 16 converts the transmission signal into IF and RF by frequency conversion. The transmission power is output from the transmission power controller 7 based on the control information. The converted transmission signal is transmitted by the transmission power based on the control information output from the transmission power controller 7.

The operation of the first embodiment will be described with reference to the drawings showing the following timing examples.

As shown in FIG. 1, the downlink TPC bits are determined by the downlink TPC bit determiner 11 from the calculation result of the SIR calculator 10 and then input to the TPC timing measuring unit 12.

3 is a block diagram showing the timing of the TPC timing measuring unit 12. As shown in FIG.

A time interval is required until the input downlink TPC bit is reflected in the transmission data. As shown in Fig. 3, the TPC timing measuring unit 12 has a function of measuring a time interval until the downlink TPC bit is reflected in the transmission data. Measurement start (X in Fig. 3) is a timing at which the TPC bit is to be inserted into the transmission data. A valid TPC bit from the downlink TPC bit determiner 11, i.e., a bit that can be inserted at the current insertion position, is input. On the other hand, attention is paid to the timing when one (1) slot passes. For the end of the measurement (Y in Fig. 3), only the earliest one is selected between the timing when the valid TPC bit is inserted at the current insertion position and another timing when one (1) slot passes. Note the time interval "a", which is the time interval from when the downlink TPC bit reaches the insertion position until the downlink TPC bit is output. The TPC timing measuring unit 12 sets a time interval " a " in every register in a register on the inside of the monitor 12-5. When the value of the allowable time "a" gradually decreases, it becomes difficult to take the TPC insertion timing. The state failure notification register 12-6 notifies the TPC timing adjustment unit 12-7 of the insertion timing state. The SIR measurement time adjustment process is performed.

In addition, the time interval passes through the corresponding one slot from the start of measurement. If a valid TPC bit is not input even after one slot has elapsed since the start of the measurement, a flag (a flag missing a TPC bit) for notifying this is set in the register. The state bad notification register 12-6 sets a flag in the register, and then starts counting repeatedly from zero (zero). At this time, a new measurement result is not obtained. Since unupdated data remains in the register, the preceding TPC bits stored in the register are reflected in the current transmission data.

Next, a second embodiment of the present invention will be described. A plurality of users (eight users) use the CDMA base station transmission power control according to the present invention. This example is shown in accordance with the drawings. 4 is a configuration showing a second embodiment of a base station apparatus according to the present invention.

As shown in FIG. 4, the despreader 4, the demodulator 5, and the SIR calculator 10 are provided as one block # 1. The number of blocks (eg, # 1 to # 8) increases in correspondence with the number of users.

According to the above scheme, the downlink TPC bits of each user of each block are transmitted in parallel to the downlink TPC bit determiner 11. At this time, the TPC bits transmitted to the TPC timing section measuring section 12 are processed in parallel-serial by the S / P converter 17. Further, in the second embodiment, a plurality of blocks (e.g., eight blocks) are provided. However, the number of blocks is not specifically limited.

Thus, the S / P converter 17 allows eight users of the downlink TPC bits to be transmitted over the serial bus. The downlink TPC bit is introduced into the TPC timing measuring unit 12 in the format (TPC indication) as shown in FIG. The serial bus is composed of three kinds of signals CLK, SYNC and DATA as shown in FIG. CLK is used for sampling SYNC and DATA. In addition, SYNC is a synchronization signal indicating the beginning of DATA. DATA is data consisting of N bits. Bits 0 through 2 (U0, U1, U2, ... U8) located at the beginning of the TPC indication indicate the user channel number (e.g., data "010" represents the third user). 5, bit M (TPC) is a TPC bit. Further, in Fig. 5, bit N (parity) is a parity bit of even / odd numbers (showing even / odd numbers as "1" / "0", respectively) of bits 0 to N-1.

In the second embodiment, the operation of the second embodiment differs from the operation of the first embodiment in the following points. That is, the received digital signal is output in parallel from the transmission / reception radio section 3 (step S10). Each despreader 4 inside each block # 1 to # 8 inputs the despread received digital signal therein (step S11). Thus, the received digital signal is output as a narrowband modulated signal. The signals thus output are demodulated in each demodulator 5 of each block (step S12). The uplink TPC bit extraction section 6 then sends out demodulation signals from the mobile station in parallel (step S13). The TPC bits included in the demodulation signal are sent from the mobile station. The TPC bits contained in the demodulated signal are extracted in series. The TPC bit is output in series to the transmit power controller 7. The transmission power is determined according to the output TPC bit, and the control information is output to the transmission radio section 16 (step S14).

On the other hand, the desired wave receiving power detector 8 and the interference wave receiving power detector 9 are provided on the inside of each despreading unit 4 of each of the above-described blocks # 1 to # 8. The desired wave reception power detector 8 detects the desired wave reception power from the mobile station. The interference wave reception power detector 9 detects interference wave reception power for a desired wave. The desired wave from the mobile station and the interference wave reception power for the desired wave are respectively detected from the parallel input received digital signals (steps S15 and S17). The SIR calculator 10 finds the received SIR value of the signal from the mobile station according to the detected desired wave reception power and the detected interference wave reception power (step S16). Each received SIR value is obtained by the SIR calculator 10 as described above. These received SIR values are compared with the target SIR set in advance in the TPC bit determiner 11 (step S18). If the received SIR value is smaller than the target SIR value, control bits indicating an increase in the transmit power are generated in parallel (step S19). If the received SIR value is larger than the target SIR value, control bits indicative of a decrease in transmit power are generated in parallel (step S20).

The TPC timing measuring unit inputs the signals, which are the above-described control bits generated in parallel, in parallel. Preferably, these parallel signals are serialized by the S / P converter (serial / parallel converter) provided at the first stage. After that, the parallel signal is processed in the same manner as in the first embodiment (step S21).

In addition, in the present embodiment, the downlink TPC bit input processed in parallel is implemented in the same manner as described in the first embodiment, for example, as shown in FIG.

As described above, according to the present invention shown in the first embodiment of the base station apparatus, the time difference from the downlink TPC bit insertion time to the insertion position of the TPC bit in the transmission format is measured. If the allowable time is small, the SIR measurement time can be adjusted. For this reason, the downlink TPC bits are immediately reflected in correspondence with the allowable time interval.

Further, according to the invention shown in the first embodiment, a circuit capable of measuring the TPC bit input position with a counter and a circuit for storing the value thereof are provided, and it is possible to realize the TPC timing relatively easily. The TPC timing measurement unit can be implemented by simple hardware.

Further, according to the invention shown in the second embodiment of the base station apparatus, even when control according to a plurality of users is implemented in the serial bus, as shown in Fig. 5, in the fact that a user identification number is provided in the TPC instruction. This enables TPC bit control of each user.

While the preferred embodiments of the present invention have been described using specific terminology, it is to be understood that this is merely illustrative and that various changes and modifications may be made without departing from the spirit and scope of the following claims. .

Claims (43)

A CDMA (Code Division Multiple Access) base station transmit power controller which controls a transmit power of a transmit station by using transmit power control bits sequentially transmitted from a receiving station to a transmitting station. Transmit Power Control (TPC) timing measurement that measures the allowable time until a downlink TPC bit is reflected in the transmission data, and causes the TPC bit to be reflected in the transmission data at the insertion timing when a propagation delay occurs. Means, The TPC timing measuring means, A first counter for storing a timing position when the downlink TPC bit is input, and latching and counting the timing position by a generated clock; A second counter for outputting an input position of the downlink transmission data TPC; And The difference between the output value of the counter value from the first counter and the TPC of the current transmission data from the second counter is calculated, the timing position at the time of the downlink TPC bit input, and the input of the downlink transmission data TPC. TPC time tolerance calculator to compare each location with a predetermined value CDMA base station transmission power controller comprising a. 2. An uplink / downlink TPC bit generator comprising a despreading means, a demodulator for demodulating an output signal from said despreading means, and an SIR calculator, provided by the number of received digital signals. CDMA base station transmit power controller. 3. The uplink of claim 2, wherein an uplink TPC bit is extracted in parallel from the received signal despread by the uplink / downlink TPC bit generator and outputs the uplink TPC in series through the demodulator. And a TPC bit extracting means. 3. The CDMA base station transmit power controller according to claim 2, further comprising a downlink TPC bit determiner for processing the output signals from the uplink / downlink TPC bit generator in parallel. 4. The CDMA base station transmit power controller according to claim 3, further comprising a downlink TPC bit determiner for processing the output signals from the uplink / downlink TPC bit generator in parallel. 5. The CDMA base station transmit power controller according to claim 4, wherein said TPC timing measuring means outputs a parallel signal from said TPC bit determiner in series. 6. The CDMA base station transmit power controller according to claim 5, wherein said TPC timing measuring means outputs a parallel signal from said TPC bit determiner in series. delete delete delete delete delete delete delete According to claim 1, wherein the TPC timing measuring means, A monitor for determining the presence or absence of insertion of a TPC bit into downlink transmission data according to the output from the comparing means; A status bad notification register for notifying both an adjustment of a SIR measurement time from the monitor and a slot unit over flag; And TPC timing adjustment unit for adjusting the SIR measurement time notified in advance and outputting the slot unit excess flag notified in advance The CDMA base station transmit power controller further comprises. According to claim 2, The TPC timing measuring means, A monitor for determining the presence or absence of insertion of a TPC bit into downlink transmission data according to the output from the comparing means; A status bad notification register for notifying both an adjustment of an SIR measurement time from the monitor and an over slot unit flag; And TPC timing adjustment unit for adjusting the SIR measurement time notified in advance and outputting the slot unit excess flag notified in advance The CDMA base station transmit power controller further comprises. The method of claim 3, wherein the TPC timing measuring means, A monitor for determining the presence or absence of insertion of a TPC bit into downlink transmission data according to the output from the comparing means; A status bad notification register for notifying both an adjustment of an SIR measurement time from the monitor and an over slot unit flag; And TPC timing adjustment unit for adjusting the SIR measurement time notified in advance and outputting the slot unit excess flag notified in advance The CDMA base station transmit power controller further comprises. The method of claim 4, wherein the TPC timing measuring means, A monitor for determining the presence or absence of insertion of a TPC bit into downlink transmission data according to the output from the comparing means; A status bad notification register for notifying both an adjustment of an SIR measurement time from the monitor and an over slot unit flag; And TPC timing adjustment unit for adjusting the SIR measurement time notified in advance and outputting the slot unit excess flag notified in advance The CDMA base station transmit power controller further comprises. According to claim 5, The TPC timing measuring means, A monitor for determining the presence or absence of insertion of a TPC bit into downlink transmission data according to the output from the comparing means; A status bad notification register for notifying both an adjustment of an SIR measurement time from the monitor and an over slot unit flag; And TPC timing adjustment unit for adjusting the SIR measurement time notified in advance and outputting the slot unit excess flag notified in advance The CDMA base station transmit power controller further comprises. According to claim 6, The TPC timing measuring means, A monitor for determining the presence or absence of insertion of a TPC bit into downlink transmission data according to the output from the comparing means; A status bad notification register for notifying both an adjustment of an SIR measurement time from the monitor and an over slot unit flag; And TPC timing adjustment unit for adjusting the SIR measurement time notified in advance and outputting the slot unit excess flag notified in advance The CDMA base station transmit power controller further comprises. The method of claim 7, wherein the TPC timing measuring means, A monitor for determining the presence or absence of insertion of a TPC bit into downlink transmission data according to the output from the comparing means; A status bad notification register for notifying both an adjustment of an SIR measurement time from the monitor and an over slot unit flag; And TPC timing adjustment unit for adjusting the SIR measurement time notified in advance and outputting the slot unit excess flag notified in advance The CDMA base station transmit power controller further comprises. A base station apparatus comprising the CDMA base station transmit power controller according to claim 1. A base station apparatus comprising the CDMA base station transmit power controller according to claim 2. A base station apparatus comprising the CDMA base station transmit power controller according to claim 3. A base station apparatus comprising the CDMA base station transmit power controller according to claim 4. A base station apparatus comprising the CDMA base station transmission power controller according to claim 5. A base station apparatus comprising the CDMA base station transmission power controller according to claim 6. A base station apparatus comprising the CDMA base station transmit power controller according to claim 7. delete delete delete delete delete delete delete A base station apparatus comprising the CDMA base station transmit power controller according to claim 15. A base station apparatus comprising the CDMA base station transmit power controller according to claim 16. A base station apparatus comprising the CDMA base station transmission power controller according to claim 17. A base station apparatus comprising the CDMA base station transmission power controller according to claim 18. A base station apparatus comprising the CDMA base station transmit power controller according to claim 19. A base station apparatus comprising the CDMA base station transmit power controller according to claim 20. A base station apparatus comprising the CDMA base station transmission power controller according to claim 21. A TPC timing method characterized by measuring an allowable time until a downlink TPC bit is reflected in transmission data, and even when a propagation delay occurs, the TPC bit is immediately reflected in transmission data at the insertion timing. Storing a timing position when the downlink TPC bit is input at a first counter, and latching and counting the timing position by a generated clock; Outputting an input location of the downlink transmission data TPC at a second counter; And The difference between the output value of the counter value from the first counter and the TPC of the current transmission data from the second counter is calculated, the timing position at the time of the downlink TPC bit input, and the input of the downlink transmission data TPC. Calculating the TPC tolerance time by comparing each location with a predetermined value TPC timing method characterized in that it further comprises.