KR100357876B1 - semiconductor package and its manufacturing method - Google Patents
semiconductor package and its manufacturing method Download PDFInfo
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- KR100357876B1 KR100357876B1 KR1019990044648A KR19990044648A KR100357876B1 KR 100357876 B1 KR100357876 B1 KR 100357876B1 KR 1019990044648 A KR1019990044648 A KR 1019990044648A KR 19990044648 A KR19990044648 A KR 19990044648A KR 100357876 B1 KR100357876 B1 KR 100357876B1
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- inner lead
- lead
- mounting plate
- chip mounting
- semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 94
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 229910000679 solder Inorganic materials 0.000 claims abstract description 21
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 12
- 239000000853 adhesive Substances 0.000 claims abstract description 8
- 230000001070 adhesive effect Effects 0.000 claims abstract description 8
- 238000007747 plating Methods 0.000 claims description 19
- 230000004927 fusion Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 12
- 239000010931 gold Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 239000011093 chipboard Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229920006336 epoxy molding compound Polymers 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
이 발명은 반도체패키지 및 그 제조 방법에 관한 것으로, 반도체패키지를 마더보드(mother board)에 실장시 솔더 조인트력(solder joint force)이 향상되도록 다수의 입출력패드가 형성된 반도체칩과; 상기 반도체칩의 저면에 접착제로 접착된 칩탑재판과; 상기 칩탑재판의 외주연에 일정거리 이격되어 형성된 다수의 내부리드와; 상기 반도체칩의 입출력패드와 내부리드를 전기적으로 접속하는 도전성와이어와; 상기 반도체칩, 도전성와이어, 칩탑재판 및 내부리드 등이 봉지재로 봉지되어 있되, 상기 칩탑재판 및 내부리드의 저면과 측면은 외부로 노출되도록 봉지되어 형성된 패키지몸체로 이루어진 반도체패키지에 있어서, 상기 내부리드의 외측면에는 패키지몸체의 상부 방향을 향하여 버가 형성된 것을 특징으로 하는 반도체패키지 및 그 제조 방법.The present invention relates to a semiconductor package and a method of manufacturing the same, comprising: a semiconductor chip having a plurality of input / output pads formed thereon to improve solder joint force when the semiconductor package is mounted on a mother board; A chip mounting plate adhered to the bottom of the semiconductor chip with an adhesive; A plurality of internal leads formed at a predetermined distance apart from an outer circumference of the chip mounting plate; Conductive wires electrically connecting the input / output pads and the internal leads of the semiconductor chip; In the semiconductor package, the semiconductor chip, the conductive wire, the chip mounting plate and the inner lead is sealed with an encapsulant, the bottom and side surfaces of the chip mounting plate and the inner lead is sealed to be exposed to the outside. A semiconductor package and a method for manufacturing the package, characterized in that the burr is formed on the outer surface of the inner lead toward the upper direction of the package body.
Description
본 발명은 반도체패키지 및 그 제조 방법에 관한 것으로, 더욱 상세하게 설명하면 반도체패키지를 마더보드(mother board)에 실장시 솔더 조인트력(solder joint force)을 향상시킬 수 있는 반도체패키지 및 그 제조 방법에 관한 것이다.The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package and a method for manufacturing the semiconductor package capable of improving solder joint force when the semiconductor package is mounted on a motherboard. It is about.
최근의 전자기기 예를 들면, 휴대폰, 셀룰러 폰, 노트북 등의 마더보드에는 많은 수의 반도체칩들이 패키징되어 최소시간내에 그것들이 다기능을 수행할 수 있도록 설계되는 동시에, 전자기기 자체가 초소형화 되어가는 추세에 있다. 이에 따라 반도체칩이 고집적화됨은 물론, 이를 패키징한 반도체패키지의 크기도 축소되고 있으며, 또한 실장밀도도 고밀도화되어 가고 있다.In modern electronic devices such as mobile phones, cellular phones, and notebooks, a large number of semiconductor chips are packaged and designed so that they can perform multifunction in a minimum amount of time. There is a trend. As a result, semiconductor chips are not only highly integrated, but also the size of the semiconductor package packaged therein is also being reduced, and the packaging density is also becoming higher.
이러한 추세에 따라 최근에는 반도체칩의 전기적 신호를 마더보드로 전달해줌은 물론 마더보드(mother board) 상에서 일정한 형태로 지지되도록 하는 반도체패키지의 크기가 대략 1×1mm ~ 10×10mm 내외로 개발되고 있으며, 이러한 반도체패키지의 예로서 MLF(Micro LeadFrame)형 패키지 등이 알려져 있다.Recently, the size of the semiconductor package that delivers electrical signals of semiconductor chips to the motherboard and is supported on the motherboard (mother board) in a certain shape has been developed to about 1 × 1mm ~ 10 × 10mm. As examples of such semiconductor packages, MLF (Micro LeadFrame) packages and the like are known.
여기서 상기 MLF형 반도체패키지(100')를 도1a 및 도1b에 도시하였다.The MLF type semiconductor package 100 'is shown in FIGS. 1A and 1B.
도시된 바와 같이 상면에 다수의 입출력패드(2a)가 형성된 반도체칩(2)이 구비되어 있고, 상기 반도체칩(2)의 저면에는 접착제로 칩탑재판(4)이 접착되어 있다. 상기 칩탑재판(4)은 측면 둘레에 할프에칭부(4a)가 형성되어 있고 모서리에는 외측으로 연장되고 역시 할프에칭부(도시되지 않음)가 구비된 타이바(28)가 형성되어 있다. 상기 칩탑재판(4)의 외주연에는 방사상으로 배열되어 있으며 칩탑재판(4)을 향하는 단부에 할프에칭부(6a)가 형성된 다수의 내부리드가 구비되어 있다. 상기 반도체칩(2)의 입출력패드(2a)와 내부리드는 도전성와이어(8)에 의해 서로 전기적으로 접속되어 있다. 계속해서 상기 반도체칩(2), 도전성와이어(8), 칩탑재판(4) 및 내부리드는 봉지재로 봉지되어 소정의 패키지몸체(10)를 형성하고 있으며, 상기 칩탑재판(4), 내부리드(6) 및 타이바(28)의 저면은 패키지몸체(10) 저면으로 노출되어 있다.As shown in the drawing, a semiconductor chip 2 having a plurality of input / output pads 2a formed thereon is provided, and a chip mounting plate 4 is attached to the bottom of the semiconductor chip 2 with an adhesive. The chip mounting plate 4 has a half etched portion 4a formed around the side, and a tie bar 28 extending outward at the corner and also provided with a half etched portion (not shown). The outer periphery of the chip mounting plate 4 is arranged radially and has a plurality of internal leads formed with a half etching portion 6a at an end facing the chip mounting plate 4. The input / output pad 2a and the inner lead of the semiconductor chip 2 are electrically connected to each other by conductive wires 8. Subsequently, the semiconductor chip 2, the conductive wire 8, the chip mounting plate 4 and the inner lead are encapsulated with an encapsulant to form a predetermined package body 10. The chip mounting plate 4, The bottom of the inner lead 6 and the tie bar 28 is exposed to the bottom of the package body 10.
여기서 상기 칩탑재판(4), 내부리드(6) 및 타이바(28)에 형성된 할프에칭부(4a,6a)는 봉지재로 형성된 패키지몸체(10)와 인터락킹(interlocking)됨으로써 수직 또는 수평으로 이탈됨을 방지하도록 되어 있다. 또한 상기 타이바(28)에 형성된 할프에칭부(도시되지 않음)는 패키지몸체(10) 저면으로 노출되는 타이바(28) 및 내부리드(6)의 상대적 거리를 멀게 함으로써, 상기 반도체패키지(100')를 마더보드(도시되지 않음)에 실장시 솔더에 의한 쇼트 현상을 최소화할 수 있도록 되어 있다.Here, the half-etched portions 4a and 6a formed on the chip mounting plate 4, the inner lead 6, and the tie bar 28 are vertically or horizontally interlocked with the package body 10 formed of an encapsulant. It is to prevent the departure from. In addition, the half-etching portion (not shown) formed in the tie bar 28 may move the relative distance between the tie bar 28 and the inner lead 6 exposed to the bottom surface of the package body 10, thereby providing the semiconductor package 100. ') Is mounted on the motherboard (not shown) to minimize the short circuit caused by the solder.
또한, 상기 패키지몸체(10) 저면으로 노출되는 내부리드(6), 타이바(28) 또는 칩탑재판(4)의 저면에는 솔더로 일정두께의 도금층(30)이 형성되어, 차후 반도체패키지(100')의 실장시 마더보드와의 솔더 조인트력이 향상되도록 되어 있다.In addition, a plating layer 30 having a predetermined thickness is formed on the bottom surface of the inner lead 6, the tie bar 28, or the chip mounting plate 4 exposed to the bottom surface of the package body 10. 100 ') is designed to improve the solder joint strength with the motherboard.
도면중 미설명부호 6b는 리드프레임에서 반도체패키지(100')를 싱귤레이션할 때 발생되는 버(6b)(bur)이며 이는 하기에서 상세히 설명하기로 한다.In the figure, reference numeral 6b denotes a bur 6b generated when singulating the semiconductor package 100 'in a lead frame, which will be described in detail below.
한편, 상기와 같은 반도체패키지(100')의 제조 방법을 간단히 설명하면 다음과 같으며, 여기서는 도2 및 도3을 참조하여 싱귤레이션 방법을 중심으로 설명한다.Meanwhile, the method of manufacturing the semiconductor package 100 ′ as described above will be briefly described as follows. Here, the singulation method will be described with reference to FIGS. 2 and 3.
먼저, 대략 판상의 프레임몸체(22)와, 상기 프레임몸체(22)의 모서리에서 내측으로 연장된 다수의 타이바(28)와, 상기 타이바(28)에 연결되어 차후 반도체칩(2)이 탑재되는 칩탑재판(4)과, 상기 칩탑재판(4)의 외주연에 일정거리 이격되어 방사상으로 형성된 다수의 내부리드(6)와, 상기 내부리드(6)에 연장되어 다시 프레임몸체(22)에 연결되는 외부리드(26) 및 상기 내부리드(6)와 외부리드(26) 사이에 형성되어 프레임몸체(22)에 연결되는 댐바(24)로 이루어진 리드프레임(20)을 구비한다. 여기서 상기 칩탑재판(4)의 측면 둘레, 상기 칩탑재판(4)을 향하는 내부리드(6)의 단부 및 상기 칩탑재판(4)에 인접하는 타이바(28) 영역에는 할프에칭부를 형성한다.First, a substantially plate-shaped frame body 22, a plurality of tie bars 28 extending inwardly from the edge of the frame body 22, and the tie bars 28 are connected to the semiconductor chip 2 afterwards. The chip mounting plate 4 to be mounted, a plurality of inner leads 6 radially spaced apart from the outer periphery of the chip mounting plate 4, and extended to the inner lead 6, and again frame body ( And a lead frame 20 formed between an outer lead 26 connected to the 22 and a dam bar 24 formed between the inner lead 6 and the outer lead 26 and connected to the frame body 22. Here, a half etched portion is formed in the circumference of the side of the chip mounting plate 4, the end of the inner lead 6 facing the chip mounting plate 4 and the region of the tie bar 28 adjacent to the chip mounting plate 4. do.
이어서, 상기 리드프레임(20)의 칩탑재판(4)에 양품의 반도체칩(2)을 접착제로 접착한다.Subsequently, a good semiconductor chip 2 is bonded to the chip mounting plate 4 of the lead frame 20 with an adhesive.
이어서, 상기 반도체칩(2)의 입출력패드(2a)와 리드프레임(20)의내부리드(6)를 도전성와이어(8)를 이용하여 전기적으로 접속한다.Subsequently, the input / output pad 2a of the semiconductor chip 2 and the inner lead 6 of the lead frame 20 are electrically connected using the conductive wires 8.
이어서, 상기 반도체칩(2), 도전성와이어(8), 칩탑재판(4), 내부리드(6) 등을 봉지재로 봉지하여 패키지몸체(10)를 형성하되, 상기 칩탑재판(4)과 내부리드(6)의 저면 및 측면은 패키지몸체(10) 외측으로 노출되도록 한다. 이때, 상기 칩탑재판(4), 내부리드(6) 및 패키지몸체(10)의 저면은 동일평면이 되도록 하며, 상기 내부리드(6)의 상면 일부가 패키지몸체(10) 외측으로 노출될 수 있다.Subsequently, the package body 10 is formed by encapsulating the semiconductor chip 2, the conductive wire 8, the chip mounting plate 4, the inner lead 6, and the like with an encapsulant, and the chip mounting plate 4 The bottom and side surfaces of the inner lead 6 are exposed to the outside of the package body 10. At this time, the bottom surface of the chip mounting plate 4, the inner lead 6 and the package body 10 to be the same plane, a portion of the upper surface of the inner lead 6 may be exposed to the outside of the package body (10). have.
이어서, 상기 반도체패키지(100)의 내부리드(6) 등이 마더보드에 용이하게 실장되도록 패키지몸체(10) 외부로 노출된 내부리드(6) 및 타이바(28)와 칩탑재판(4) 저면에 솔더와 융착력이 양호한 일정두께의 도금층(30)을 형성한다.Subsequently, the inner lead 6 and the tie bar 28 and the chip mounting plate 4 exposed to the outside of the package body 10 so that the inner lead 6 of the semiconductor package 100 is easily mounted on the motherboard. On the bottom, a plating layer 30 having a predetermined thickness having good solder and welding strength is formed.
상기와 같은 공정을 완료하면 도2에 도시된 형상으로 되며, 이후에는 리드프레임(20)에서 낱개의 반도체패키지(100')로 싱귤레이션하는 공정을 따른다.When the above process is completed, the shape shown in FIG. 2 is completed. Subsequently, the lead frame 20 is singulated with a single semiconductor package 100 '.
상기 싱귤레이션 공정은 도3에 도시된 바와 같이 패키지몸체(10)가 상부를 향하여 위치하도록 바텀클램프(44) 상에 위치되고, 이 상태에서 상기 리드프레임(20)을 탑클램프(42)로 클램핑한 후, 펀치(P)가 수직으로 하강함으로서 내부리드 (6) 및 타이바(28) 등이 싱귤레이션된다. 이때, 상기 펀치(P)에 의해 상기 내부리드(6)의 측면 단부에는 하부를 향하여(차후 마더보드와 접촉되는 영역을 향하여) 일정길이의 버(6b)가 발생한다. 상기와 같이 버(6b)가 형성된 반도체패키지(100')는 도1a를 참조하여 위에서 이미 설명했다.The singulation process is located on the bottom clamp 44 so that the package body 10 is located upward as shown in FIG. 3, and in this state, the lead frame 20 is clamped to the top clamp 42. After that, the punch P is lowered vertically so that the inner lead 6 and the tie bar 28 and the like are singulated. At this time, a burr 6b of a predetermined length is generated at the side end of the inner lead 6 by the punch P (toward the area in contact with the motherboard later). The semiconductor package 100 ′ in which the burr 6b is formed as described above has been described above with reference to FIG. 1A.
그러나, 상기와 같은 구조 및 제조 방법(또는 싱귤레이션 방법)에 의해 제조된 반도체패키지는 싱귤레이션 공정시 내부리드의 절단면 또는 외측면 하부를 향하여 버가 발생됨으로서 차후 마더보드에 실장시 마더보드와 접촉하는 내부리드의 접촉 면적을 최소화시켜 결국 솔더 조인트력을 저하시키는 원인이 되고 있다. 더불어 마더보드에의 실장시 상기 내부리드의 측면 단부에는 도금층이 형성되어 있지 않기 때문에 실장을 위한 솔더가 내부리드의 측면을 타고 상부로 움직이지 않음으로써 그 내부리드의 솔더 조인트력이 더욱 저하되는 문제점이 있다.However, the semiconductor package manufactured by the above-described structure and manufacturing method (or singulation method) generates burrs toward the cutting surface of the inner lead or the bottom of the outer surface during the singulation process, so that it is in contact with the motherboard when it is mounted on the motherboard later. This minimizes the contact area of the inner lead, which in turn causes a decrease in the solder joint force. In addition, since the plating layer is not formed at the side end of the inner lead when mounting on the motherboard, the solder joint force of the inner lead is further lowered because the solder for mounting does not move upward along the side of the inner lead. There is this.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 반도체패키지를 마더보드에 실장시 솔더 조인트력을 향상시킬 수 있는 반도체패키지 및 그 제조 방법을 제공하는데 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, to provide a semiconductor package and a method of manufacturing the same that can improve the solder joint force when mounting the semiconductor package on the motherboard.
도1a 및 도1b는 종래의 반도체패키지를 도시한 단면도 및 저면도이다.1A and 1B are a cross-sectional view and a bottom view showing a conventional semiconductor package.
도2는 리드프레임상에 패키지몸체가 형성된 상태를 도시한 저면도이다.2 is a bottom view showing a state in which a package body is formed on a lead frame.
도3은 도2의 리드프레임에서 반도체패키지를 싱귤레이션하는 상태를 도시한 단면도이다.3 is a cross-sectional view illustrating a state in which a semiconductor package is singulated in the lead frame of FIG. 2.
도4는 본 발명에 의한 반도체패키지를 도시한 단면도이다.4 is a cross-sectional view showing a semiconductor package according to the present invention.
도5는 본 발명에 의한 반도체패키지가 마더보드에 실장되는 상태를 도시한 단면도이다.5 is a cross-sectional view showing a state in which a semiconductor package according to the present invention is mounted on a motherboard.
도6은 본 발명에 의해 리드프레임에서 반도체패키지가 싱귤레이션되는 상태를 도시한 단면도이다.6 is a cross-sectional view illustrating a state in which a semiconductor package is singulated in a lead frame according to the present invention.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
100; 반도체패키지 2; 반도체칩100; Semiconductor package 2; Semiconductor chip
2a; 입출력패드 4; 칩탑재판2a; Input / output pad 4; Chip board
4a; 칩탑재판의 할프에칭부 6; 내부리드4a; Half etching part 6 of a chip mounting board; Internal lead
6a; 내부리드의 할프에칭부 6b; 버(bur)6a; Half etched portion 6b of the inner lead; Bur
8; 도전성와이어 10; 패키지몸체8; Conductive wire 10; Package body
20; 리드프레임 22; 프레임몸체20; Leadframe 22; Frame
24; 댐바 26; 외부리드24; Dambar 26; External lead
28; 타이바 30; 도금층28; Tie bar 30; Plating layer
42; 탑클램프 44; 바텀클램프42; Top clamp 44; Bottom clamp
46; 솔더 S; 싱귤레이션 라인46; Solder S; Singulation Line
M; 마더보드M; Motherboard
상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 다수의 입출력패드가 형성된 반도체칩과; 상기 반도체칩의 저면에 접착제로 접착된 칩탑재판과; 상기 칩탑재판의 외주연에 일정거리 이격되어 형성된 다수의 내부리드와; 상기 반도체칩의 입출력패드와 내부리드를 전기적으로 접속하는 도전성와이어와; 상기 반도체칩, 도전성와이어, 칩탑재판 및 내부리드 등이 봉지재로 봉지되어 있되, 상기 칩탑재판 및 내부리드의 저면과 측면은 외부로 노출되도록 봉지되어 형성된 패키지몸체로 이루어진 반도체패키지에 있어서, 상기 내부리드의 외측면에는 패키지몸체의 상부 방향을 향하여 버가 형성된 것을 특징으로 한다.In order to achieve the above object, the semiconductor package according to the present invention comprises a semiconductor chip having a plurality of input and output pads; A chip mounting plate adhered to the bottom of the semiconductor chip with an adhesive; A plurality of internal leads formed at a predetermined distance apart from an outer circumference of the chip mounting plate; Conductive wires electrically connecting the input / output pads and the internal leads of the semiconductor chip; In the semiconductor package, the semiconductor chip, the conductive wire, the chip mounting plate and the inner lead is sealed with an encapsulant, the bottom and side surfaces of the chip mounting plate and the inner lead is sealed to be exposed to the outside. The outer surface of the inner lead is characterized in that the burr formed toward the upper direction of the package body.
여기서, 상기 내부리드는 저면 및 외측면 일부 영역에까지 솔더 등으로 도금층이 형성되어 있다.Here, the inner lead is formed with a plating layer on the bottom and part of the outer surface by solder or the like.
또한 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지의 제조 방법은 대략 판상의 프레임몸체와, 상기 프레임몸체의 모서리에서 내측으로 연장된 다수의 타이바와, 상기 타이바에 연결되어 차후 반도체칩이 탑재되는 칩탑재판과, 상기 칩탑재판의 외주연에 일정거리 이격되어 방사상으로 형성된 다수의 내부리드와, 상기 내부리드에 연장되어 다시 프레임몸체에 연결되는 외부리드 및 상기 내부리드와 외부리드 사이에 형성되어 프레임몸체에 연결되는 댐바로 이루어진 리드프레임을 구비하는 단계와; 상기 칩탑재판에 반도체칩을 접착제로 접착하는 단계와; 상기 반도체칩의 입출력패드와 리드프레임의 내부리드를 전기적으로 접속하는 단계와; 상기 반도체칩, 도전성와이어, 칩탑재판, 내부리드 등을 봉지재로 봉지하되, 상기 칩탑재판과 내부리드의 저면 및 측면은 외부로 노출되도록 봉지하여 패키지몸체를 형성하는 단계와; 상기 몸체 저면으로 노출되는 내부리드의 저면에 차후 마더보드에의 융착이 용이하게 실시되도록 솔더 등으로 도금층을 형성하는 단계와; 상기 리드프레임으로부터 반도체패키지가 독립되도록 싱귤레이션하는 단계로 이루어진 반도체패키지의 제조 방법에 있어서, 상기 싱귤레이션 단계는 패키지몸체가 하부를 향하도록 리드프레임을 뒤집은 상태로 바텀클램프 및 탑클램프 사이에 위치시켜 리드프레임을 클램핑하는 단계와, 상기 리드프레임의 댐바, 내부리드와 외부리드의 경계 부분, 타이바 등을 펀치로 절단하되, 내부리드에 형성되는 버가 패키지몸체쪽을 향하도록 탑클램프쪽에서 바텀클램프쪽으로 하강하여 싱귤레이션함을 특징으로 한다.In addition, the method for manufacturing a semiconductor package according to the present invention in order to achieve the above object is a substantially plate-shaped frame body, a plurality of tie bars extending inwardly from the corner of the frame body, and is connected to the tie bars and subsequently mounted semiconductor chip A chip mounting plate which is spaced apart from the outer periphery of the chip mounting plate by a plurality of inner leads formed radially, and an outer lead extending to the inner lead and connected to the frame body again between the inner lead and the outer lead. Forming a lead frame formed of a dam bar connected to the frame body; Adhering a semiconductor chip to the chip mounting plate with an adhesive; Electrically connecting the input / output pad of the semiconductor chip and the inner lead of the lead frame; Encapsulating the semiconductor chip, the conductive wire, the chip mounting plate, and the inner lead with an encapsulant, wherein the bottom and side surfaces of the chip mounting plate and the inner lead are exposed to the outside to form a package body; Forming a plating layer with solder or the like on the bottom of the inner lead exposed to the bottom of the body to facilitate fusion to the motherboard later; In the semiconductor package manufacturing method comprising the step of singulating the semiconductor package to be independent from the lead frame, the singulation step is located between the bottom clamp and the top clamp with the lead frame inverted so that the package body facing downward Clamping the lead frame, cutting the dam bar, the boundary between the inner lead and the outer lead, and the tie bar of the lead frame with a punch, wherein the burrs formed on the inner lead face the package body toward the bottom clamp. It is characterized by a singulation down to the side.
상기와 같이 하여 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면,싱귤레이션 공정시 리드프레임이 뒤집힌 상태로 싱귤레이션됨으로써 내부리드의 외측면에 형성되는 버가 반도체패캐지의 패키지몸체 상면 방향을 향하여 형성되고, 따라서 내부리드의 저면에 형성된 도금층이 내부리드의 외측면까지 밀려 올라가, 반도체패키지의 실장시 솔더가 상기 도금층을 따라 내부리드의 외측면까지 융착되도록 함으로써 결국 솔더 조인트력이 향상된다.According to the semiconductor package according to the present invention and the manufacturing method as described above, the burrs formed on the outer surface of the inner lead is formed toward the upper surface of the package body of the semiconductor package by singulation in the state that the lead frame is inverted during the singulation process Therefore, the plating layer formed on the bottom of the inner lead is pushed up to the outer surface of the inner lead, so that the solder is welded to the outer surface of the inner lead along the plating layer when the semiconductor package is mounted, thereby improving the solder joint force.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
도4는 본 발명에 의한 반도체패키지(100)를 도시한 단면도이다.4 is a cross-sectional view showing a semiconductor package 100 according to the present invention.
도시된 바와 같이 다수의 입출력패드(2a)가 형성된 반도체칩(2)이 구비되어 있고, 상기 반도체칩(2)의 저면에는 접착제로 칩탑재판(4)이 접착되어 있다. 또한, 상기 칩탑재판(4)의 네모서리에는 외측을 향해 연장된 타이바(도시되지 않음)가 형성되어 있다. 상기 칩탑재판(4)의 외주연에는 일정거리 이격되어 다수의 내부리드(6)가 방사상으로 형성되어 있다. 상기 반도체칩(2)의 입출력패드(2a)와 내부리드(6)는 골드와이어 또는 알루미늄와이어 등과 같은 도전성와이어(8)에 의해 전기적으로 접속되어 있다. 상기 반도체칩(2), 도전성와이어(8), 칩탑재판(4) 및 내부리드 등은 에폭시몰딩컴파운드 또는 액상봉지재와 같은 봉지재로 봉지되어 있되, 상기 칩탑재판(4) 및 내부리드(6)의 저면과 측면은 외부로 노출되도록 봉지되어 패키지몸체(10)를 이루고 있다. 상기 내부리드(6)의 상면 일정영역은 패키지몸체(10) 외측으로 노출될 수도 있으며, 이와 같은 구조는 종래와 동일하다.As illustrated, a semiconductor chip 2 having a plurality of input / output pads 2a is provided, and the chip mounting plate 4 is bonded to the bottom of the semiconductor chip 2 with an adhesive. In addition, a tie bar (not shown) extending toward the outside is formed at the corner of the chip mounting plate 4. On the outer circumference of the chip mounting plate 4, a plurality of inner leads 6 are radially spaced apart by a predetermined distance. The input / output pad 2a and the inner lead 6 of the semiconductor chip 2 are electrically connected by conductive wires 8 such as gold wires or aluminum wires. The semiconductor chip 2, the conductive wire 8, the chip mounting plate 4 and the inner lead are encapsulated with an encapsulant such as an epoxy molding compound or a liquid encapsulant, and the chip mounting plate 4 and the inner lead are The bottom and side surfaces of 6 are encapsulated so as to be exposed to the outside to form a package body 10. A certain region of the upper surface of the inner lead 6 may be exposed to the outside of the package body 10, the same structure as in the prior art.
도면중 미설명 부호 4a 및 6a는 칩탑재판 및 내부리드에 형성된 할프에칭부이다.In the figure, reference numerals 4a and 6a are half-etched portions formed in the chip mounting plate and the inner lead.
다만 본 발명은 상기 패키지몸체(10) 외측으로 노출된 내부리드(6)의 단면 즉, 외측면에 형성된 버(6b)가 패키지몸체(10) 상면을 향하고 있는 것이 특징이다. 또한 상기 내부리드(6) 저면에는 도금층(30)이 형성되어 있는데 이 도금층(30)이 내부리드(6)의 측면까지 연장 형성되어 있다. 따라서, 상기 내부리드(6)의 저면이 종래와 다르게 평탄하게 형성됨으로써 마더보드(M)와 접촉이 양호해질 뿐만 아니라 상기 반도체패키지(100)를 마더보드(M)에 실장하게 될 때에는 도5에 도시된 바와 같이 솔더(46)가 상기 내부리드(6)의 측면까지 따라 올라간 채 융착됨으로써 결국 반도체패키지(100)의 솔더 조인트력이 향상된다.However, the present invention is characterized in that the burr 6b formed on the end surface of the inner lead 6 exposed to the outside of the package body 10, that is, on the outer surface thereof faces the upper surface of the package body 10. In addition, a plating layer 30 is formed on the bottom of the inner lead 6, and the plating layer 30 extends to the side surface of the inner lead 6. Therefore, when the bottom surface of the inner lead 6 is formed to be flat, unlike the prior art, not only the contact with the motherboard M is good, but also when the semiconductor package 100 is mounted on the motherboard M, as shown in FIG. 5. As shown in the drawing, the solder 46 is welded up to the side surface of the inner lead 6, thereby improving the solder joint force of the semiconductor package 100.
한편 상기와 같은 반도체패키지(100)의 제조 방법은 다음과 같다.Meanwhile, the manufacturing method of the semiconductor package 100 as described above is as follows.
먼저 대략 판상의 프레임몸체(22)와, 상기 프레임몸체(22)의 모서리에서 내측으로 연장된 다수의 타이바(28)와, 상기 타이바(28)에 연결되어 차후 반도체칩(2)이 탑재되는 칩탑재판(4)과, 상기 칩탑재판(4)의 외주연에 일정거리 이격되어 방사상으로 형성된 다수의 내부리드(6)와, 상기 내부리드(6)에 연장되어 다시 프레임몸체(22)에 연결되는 외부리드(26) 및 상기 내부리드(6)와 외부리드(26) 사이에 형성되어 프레임몸체(22)에 연결되는 댐바(24)로 이루어진 리드프레임(20)을 구비한다.First, a substantially plate-shaped frame body 22, a plurality of tie bars 28 extending inwardly from the corners of the frame body 22, and connected to the tie bars 28, and then the semiconductor chip 2 is mounted thereon. The chip mounting plate 4 and the plurality of inner leads 6 radially spaced apart from the outer periphery of the chip mounting plate 4 and the inner lead 6 and the frame body 22 again. And a lead frame 20 formed between the outer lead 26 and the inner lead 6 and the outer lead 26 and a dam bar 24 connected to the frame body 22.
이어서 상기 칩탑재판(4)에 반도체칩(2)을 접착제로 접착하여 고정시킨다.Subsequently, the semiconductor chip 2 is adhered to and fixed to the chip mounting plate 4.
이어서 상기 반도체칩(2)의 입출력패드(2a)와 리드프레임(20)의 내부리드(6)를 골드와이어나 알루미늄와이어등과 같은 도전성와이어를 이용하여 전기적으로 접속한다.Subsequently, the input / output pad 2a of the semiconductor chip 2 and the inner lead 6 of the lead frame 20 are electrically connected using conductive wires such as gold wires or aluminum wires.
이어서 상기 반도체칩(2), 도전성와이어(8), 칩탑재판(4), 내부리드(6) 등을 봉지재로 봉지하되, 상기 칩탑재판(4)과 내부리드(6)의 저면 및 측면은 외부로 노출되도록 하여 소위 패키지몸체(10)를 형성한다.Subsequently, the semiconductor chip 2, the conductive wire 8, the chip mounting plate 4, the inner lead 6, and the like are encapsulated with an encapsulant, and the bottom surfaces of the chip mounting plate 4 and the inner lead 6 and the like. The side surface is exposed to the outside to form a so-called package body (10).
이어서, 상기 패키지몸체(10) 저면으로 노출되는 내부리드(6)의 저면에 차후 마더보드(M)에의 융착이 용이하게 실시되도록 구리(Cu), 금(Au), 솔더(Pb/Sn), 주석(Sn), 니켈(Ni) 또는 팔라디엄(Pd) 등을 이용하여 일정 두께의 도금층(30)을 형성한다.Subsequently, copper (Cu), gold (Au), solder (Pb / Sn), and the like may be easily adhered to the motherboard M later on the bottom of the inner lead 6 exposed to the bottom of the package body 10. A plating layer 30 having a predetermined thickness is formed using tin (Sn), nickel (Ni), palladium (Pd), or the like.
마지막으로 상기 리드프레임(20)으로부터 반도체패키지(100)가 독립되도록 싱귤레이션한다.Finally, the semiconductor package 100 is singulated from the lead frame 20 to be independent.
여기서 본 발명의 특징은 도6에 도시된 바와 같이 상기 싱귤레이션 공정에 있다. 즉, 패키지몸체(10)가 하부를 향하도록(반도체칩(2)이 하부를 향하도록) 리드프레임(20)을 뒤집은 다음 그 리드프레임(20)을 바텀클램프(44) 및 탑클램프(42) 사이에 위치시켜 리드프레임(20)의 댐바(24) 및 타이바(28) 등을 강하게 클램핑한다.The feature of the present invention lies in the singulation process as shown in FIG. That is, the lead frame 20 is turned over so that the package body 10 faces downward (the semiconductor chip 2 faces downward), and then the lead frame 20 is bottom clamped 44 and the top clamp 42. Positioned between the clamps strongly to the dam bar 24 and tie bar 28 of the lead frame 20.
이어서, 상기 리드프레임(20)의 댐바(24), 내부리드(6)와 외부리드(26)의 경계 부분, 타이바(28) 및 봉지재로 형성된 패키지몸체(10)를 펀치(P)로 동시에 펀칭한다. 이때, 상기 펀치(P)는 탑클램프(42)쪽에서 바텀클램쪽으로 하강하도록 하여 싱귤레이션을 실시한다.Subsequently, the package body 10 formed of the dam bar 24 of the lead frame 20, the boundary between the inner lead 6 and the outer lead 26, the tie bar 28, and the encapsulant is punched (P). Punch at the same time. At this time, the punch (P) is subjected to singulation by lowering from the top clamp 42 side to the bottom clamp side.
따라서 상기 펀치(P)와의 마찰에 의해 싱귤레이션되는 내부리드(6)의 측면에는 버(6b)가 패키지몸체(10)쪽 즉, 반도체칩(2)쪽을 향하여 형성되며 결과물은 도4와 같은 반도체패키지(100)를 얻을 수 있게 된다.Therefore, a burr 6b is formed on the side of the inner lead 6 singulated by friction with the punch P toward the package body 10, that is, the semiconductor chip 2, and the result is shown in FIG. The semiconductor package 100 can be obtained.
상기와 같이 버(6b)가 형성되는 도중, 내부리드(6) 저면에 형성된 도금층(30)은 펀치(P)에 의해 패키지몸체(10) 또는 반도체칩(2)의 상방을 향해 일정거리 밀려나게 된다. 즉, 버(6b)가 형성된 방향을 향하여 상기 도금층(30)이 내부리드(6) 측면을 따라 일정거리 밀려나게 된다. 다시말하면, 펀치(P)에 의해 내부리드(6) 저면에 형성되어 있던 도금층(30)이 벗겨져 제거되는 것이 아니고, 상기 내부리드(6)의 측면을 따라 약간 늘어나면서 상기 내부리드(6) 측면까지 위치된다는 것이다.While the burr 6b is formed as described above, the plating layer 30 formed on the bottom surface of the inner lead 6 is pushed by a punch P for a predetermined distance upwards of the package body 10 or the semiconductor chip 2. do. That is, the plating layer 30 is pushed by a predetermined distance along the side of the inner lead 6 in the direction in which the burr 6b is formed. In other words, the plating layer 30 formed on the bottom surface of the inner lead 6 is not removed by the punch P, and is slightly removed along the side surface of the inner lead 6 while removing the plating layer 30 formed on the bottom surface of the inner lead 6. Is located until.
결과적으로 상기 도금층은 내부리드의 저면뿐만 아니라 내부리드의 측면 일정영역에도 자연스럽게 형성됨으로써 차후 반도체패키지를 마더보드에 실장시 솔더가 상기 내부리드 측면까지 자연스럽게 타고 올라와 융착되어 솔더 조인트력이 향상되는 것이다.As a result, the plating layer is naturally formed not only on the bottom of the inner lead but also on a predetermined region of the inner lead, and when soldering the semiconductor package to the motherboard later, the solder naturally rises to the inner lead and is fused to improve solder joint force.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.
따라서 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면, 싱귤레이션 공정시 리드프레임이 뒤집힌 상태로 펀치가 하강하여 싱귤레이션됨으로써 내부리드의 외측면에 형성되는 버가 패키지몸체 상면 방향을 향하여 형성됨으로써 내부리드의 저면에 형성된 도금층이 내부리드의 외측면을 따라 밀려 올라가, 반도체패키지의 실장시 솔더가 상기 버의 형성 방향까지 따라 올라 감으로써 솔더 조인트력이 향상되는 효과가 있다.Therefore, according to the semiconductor package and the manufacturing method thereof according to the present invention, the burrs formed on the outer surface of the inner lead is formed toward the upper surface of the package body by punching down while the lead frame is turned upside down during the singulation process, so that the burrs are formed inside the package body. The plating layer formed on the bottom surface of the lead is pushed up along the outer surface of the inner lead, so that the solder joint force is improved when the semiconductor package is mounted up along the direction of formation of the burr.
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990044648A KR100357876B1 (en) | 1999-10-15 | 1999-10-15 | semiconductor package and its manufacturing method |
| JP2000015004A JP2001077278A (en) | 1999-10-15 | 2000-01-24 | Semiconductor package, lead frame thereof, manufacture of semiconductor package and mold thereof |
| US09/687,049 US6525406B1 (en) | 1999-10-15 | 2000-10-13 | Semiconductor device having increased moisture path and increased solder joint strength |
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| KR1019990044648A KR100357876B1 (en) | 1999-10-15 | 1999-10-15 | semiconductor package and its manufacturing method |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07176673A (en) * | 1993-12-21 | 1995-07-14 | Hitachi Ltd | Lead frame and method of manufacturing semiconductor device using the same |
| JPH08124950A (en) * | 1994-10-26 | 1996-05-17 | Toshiba Corp | Method for manufacturing semiconductor device |
| KR19980066329A (en) * | 1997-01-22 | 1998-10-15 | 문정환 | Lead Structure of Semiconductor Package |
| KR19980086249A (en) * | 1997-05-31 | 1998-12-05 | 문정환 | Ridged lead package and its manufacturing method |
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1999
- 1999-10-15 KR KR1019990044648A patent/KR100357876B1/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07176673A (en) * | 1993-12-21 | 1995-07-14 | Hitachi Ltd | Lead frame and method of manufacturing semiconductor device using the same |
| JPH08124950A (en) * | 1994-10-26 | 1996-05-17 | Toshiba Corp | Method for manufacturing semiconductor device |
| KR19980066329A (en) * | 1997-01-22 | 1998-10-15 | 문정환 | Lead Structure of Semiconductor Package |
| KR19980086249A (en) * | 1997-05-31 | 1998-12-05 | 문정환 | Ridged lead package and its manufacturing method |
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