KR100353816B1 - receiving device for communication - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication receiver capable of outputting standardized data for enabling communication with an external device by a four-phase phase modulation (QPSK) receiving device, which is a communication semiconductor, with a single memory. By implementing the FIFO memory structure using only the control unit of the, to provide a communication receiver that can reduce the power consumption while minimizing the chip area, the present invention for this purpose is to provide a second clock having an average period of the first clock A generating clock generator; An address controller configured to generate read and write selection signals and an address increment signal in accordance with the first and second clocks; An address generator which increases an address according to the address increase signal and determines whether an address generated according to a read and write selection signal of the address controller is read or write; And a RAM for storing input data according to an address signal of the address generator and outputting the input data, wherein the address controller controls the address generator to generate a write address after data is written to the RAM by a predetermined ratio or more. There is provided a receiving device for communication comprising the.

Description

Receiving device for communication

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication receiver, and more particularly, to a communication receiver capable of outputting standardized data for enabling communication with an external device by a QPSK receiving device, which is a communication semiconductor, with only one memory.

All conventional semiconductor devices for communication are also implemented to adapt the data clock according to the channel currently being broadcast. In general, all FIFOs (First In First Out) use a FIFO memory structure. This is because atypical data is continuously input in the communication device, and on the contrary, the formatted data must be sent outside the communication device. In order to implement such a FIFO memory structure, a conventional method of connecting two single-port static random access memory (SRAM) in parallel is used. That is, since one SRAM cannot simultaneously perform read and write operations, data is continuously written from one SRAM and output data from another SRAM. This approach is widely used because it is the most common and simple to implement. However, two memories must be used, and many gates are required to implement a control unit such as an adaptation unit according to a transmission speed. At this time, the memory size cannot be arbitrarily reduced. In order to improve this, dual port SRAM may be used. However, since the transmission cannot be started until one frame is received, the memory size cannot be reduced.

SUMMARY OF THE INVENTION The present invention provides a communication receiver capable of minimizing power consumption while reducing chip area by implementing a FIFO memory structure using only a single memory and a simple structure controller to solve the above-mentioned problems. have.

1 is a view for explaining the configuration of a communication receiving apparatus according to the present invention.

FIG. 2 is a detailed configuration diagram of the clock generator shown in FIG. 1. FIG.

FIG. 3 is a detailed configuration diagram of the address generator shown in FIG. 1. FIG.

4 is a view for explaining the operation of the input and output clock of the clock generator shown in FIG.

5A to 5D are views for explaining the operation of the RAM shown in FIG.

6 is a state machine diagram of the address control unit shown in FIG.

* Description of the main parts of the drawing

10: clock generator 20: address controller

30: address generator 40: RAM

According to an aspect of the present invention for achieving the above object, a clock generator for generating a second clock having an average period of the first clock; An address controller configured to generate read and write selection signals and an address increment signal in accordance with the first and second clocks; An address generator which increases an address according to the address increase signal and determines whether an address generated according to a read and write selection signal of the address controller is read or write; And a RAM for storing input data according to an address signal of the address generator and outputting the input data, wherein the address controller controls the address generator to generate a write address after data is written to the RAM by a predetermined ratio or more. According to another aspect of the present invention, there is provided a communication receiving apparatus including a clock generator for generating a second clock having an average period of a first clock; An address controller configured to generate read and write selection signals and an address increment signal in accordance with the first and second clocks; An address generator which increases an address according to the address increase signal and determines whether an address generated according to a read and write selection signal of the address controller is read or write; And a RAM configured to store input data according to an address signal of the address generator and to output the read data, wherein the address controller is configured to read a read address rather than a write address so that the RAM can read data at predetermined time intervals when the data is output. There is provided a communication receiving apparatus including controlling the address generator so as to occur preferentially.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a view for explaining the configuration of the communication receiving apparatus according to the present invention, wherein reference numeral 10 denotes a clock generator, 20 denotes an address controller, 30 denotes an address generator, and 40 denotes a RAM. .

First, the clock generator 10 calculates an average period of the input clock CLK1 and generates an output clock CLK2 corresponding thereto. At this time, the output clock CLK2 is always faster than the input clock CLK1. The address controller 20 receives the input / output clocks CLK1 and CLK2 as inputs, and generates read and write selection signals Read / Write and read and write address increment signals Rinc and Winc, respectively, for controlling the address. The address generator 30 generates a corresponding address under the control of the address controller 20. That is, a read address or a write address is selectively generated according to the read and write selection signals (Read / Write), and the corresponding address is incremented by one according to the address increase signals (Rinc and Winc). The RAM stores the input data Din according to the address Addr generated by the address generator 30 and outputs the same as the output data Dout.

FIG. 2 shows a detailed configuration diagram of the clock generator 10 shown in FIG. 1, with reference numeral 11 designating an edge detector, 12 and 14 a counter, 15 an AND gate, 16 a comparator, and 18 shows each data clock generator.

In Fig. 2, the input clock CLK1 is inputted before the lock signal indicating that valid data is transmitted from the communication element (not shown) is generated. At this time, when the lock signal is generated, the edge detector 11 detects an edge and outputs it as a reset signal to the counters 12 and 14 to initialize it. The counter 12 counts the input clock CLK1 and passes the value to the comparator 16. In this case, the comparator 16 compares whether the counting value is '7' and outputs '1' when it is determined as '7' according to the result. In this case, since the system clock system_CLK is disabled by the AND gate 15, the counter 14 stops the counting operation. That is, the clock generator 10 counts the input clock CLK1 through the counter 12 and calculates the time. This is possible by counting through the counter 14 by enabling the system clock system_CLK while counting the eight input clocks CLK1. At this time, the data clock generator 18 changes the clock period in proportion to the counting value of the counter 14.

3 shows a detailed configuration diagram of the address generator 30 shown in FIG.

The address generator 30 shown in FIG. 3 is reset by a reset signal, and the read address generator 32 increases the read address by '1' according to the read address increase signal Rinc, and the reset signal. The reset address is reset by (reset), and the write address generator 34 which increases the read address by '1' according to the write address increase signal Winc, and the addresses generated by the two address generators 32 and 34 are read. The multiplexer 36 selects and outputs the data by the / write selection signal Read / Write.

The operation according to the above configuration will be described in detail with reference to FIGS. 4, 5A to 5D, and FIG. 6.

The present invention implements a FIFO memory structure in which a conventional communication receiver is connected to two memories in parallel. This is possible by utilizing the characteristics of the communication device where the input data is atypical but the average transfer rate is determined by the value of the channel and the device's status register (not shown). That is, the input clock CLK1 reads the average amount of time for a predetermined time to generate an output clock CLK2, and outputs data recorded at the time when the frame is mostly recorded (approximately 90%) according to the standardized clock. At this time, since the output and the input should be accessed through the same address of the RAM 40, the address control unit 20 is used to determine the timing. In addition, since the output data must be output formally at regular time intervals, the read operation should have a higher priority than the write operation. That is, the address for writing data to the RAM 40 is stored using the remaining time after the read operation is completed. At this time, the clock signal used for the address controller 20 and the address generator 30 may be at least eight times faster than the input / output clocks CLK1 and CLK2. This is because the read and write operations must be performed simultaneously for one clock cycle. The communication receiver according to the present invention is a quadrature phase shift keying (QPSK) receiver and receives signals transmitted wirelessly and transmits them in MPEG frame units to a moving picture expert group (MPEG) frame processing board. It will play a role. In this case, in order to transmit a frame to an external device other than the MPEG frame processing board, the output terminal signal should be shaped to be suitable for a common interface (CI) module. That is, the data clock must be constant, and a signal indicating that the data output and valid data are output should be generated. However, communication devices such as QPSK have a disadvantage in that they cannot fundamentally format the data clock because the data transmission speed is different for each broadcast channel. If the data clock is not formatted, the phase-lock loop (PLL) in the common interface module cannot operate normally. Therefore, the final output stage must be connected to the FIFO structure to solve this problem and to be transmitted to the standardized data clock. Accordingly, the clock generator 10 calculates an average period of the input clock CLK1 and generates a corresponding output clock CLK2. In this case, a time point that can be written to the RAM 40 will be described with reference to FIG. 4.

In Fig. 4, the output clock CLK2 has an average period of the input clock CLK1 and thus precedes the input clock CLK1. The address controller 20 generates a read / write selection signal (Read / Write) for selecting an address type (read / write), and generates read and write address increase signals (Rinc, Winc) for increasing the corresponding address. Will occur. At this time, the address controller 20 controls the address generator 30 to generate a read address for a quarter period at the rising edge of the output clock CLK2, stops the write address during that time, and then inputs the input clock. The write address is controlled to occur at the high level of CLK1. Thus, read and write operations are performed simultaneously for one period of the clock. In this case, the addressing operation will be described in detail with reference to FIGS. 5A to 5D.

First, in Fig. 5A, both read address and write address have the same lowest value before performing an operation. Thereafter, as the input data Din starts to be written to the RAM 40, the write address gradually increases, and the read address does not increase. Then, when the write address reaches a predetermined value, that is, when data corresponding to 90% of the memory size of the RAM 40 is written, the read address is gradually increased as shown in Fig. 5C. At this time, if the write address has the highest value, it starts to increase again from the lowest value. Subsequently, when all data written to the RAM 40 is read, the read address has the lowest value again, and the lowest value is maintained until the data is written about 90%. At this time, since the output clock CLK2 is faster than the input clock CLK1 as described above, no underflow or overflow occurs. Therefore, the existing FIFO memory structure can be implemented only with a single memory and a simple structure controller for controlling the same.

FIG. 6 shows a state machine diagram of the address control unit 20 shown in FIG. 1, where READ indicates a read state, WRITE indicates a write state, and WAIT WRITE indicates a write wait state.

In FIG. 6, the address controller 20 controls the address generator 30 to perform a read operation for each output clock CLK2, and conversely, performs a write operation for each input clock CLK1. At this time, the write operation is conditionally determined by determining whether the write operation is possible. For example, if the current write operation is possible (①), the write operation is performed after the read operation, and the read operation is performed again after the write operation is completed (③). On the contrary, if the current write operation is impossible (②), the state transitions to the write standby state, and when the write operation becomes possible again (④), the write operation is performed.

As described above, the present invention reads and writes signals for controlling the RAM by changing the address several times when the data clock is input once by utilizing the access time supported by the RAM by using a fast system clock. By repeating, address and control signals are generated by the input clock much slower than the RAM access time, thereby overcoming the limitations of the existing SRAM and the inability to read and write. The controller to perform the RAM operation does not require much logic, so the chip area can be optimized to implement the FIFO memory structure.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The communication receiving apparatus according to the present invention made as described above may implement a FIFO memory structure implemented using two conventional memories using only a single memory. Therefore, the memory size can be reduced by half, compared to a method in which two memories having a frame size are connected in parallel.

Claims (5)

delete A clock generator which generates a second clock having an average period of the first clock; An address controller configured to generate read and write selection signals and an address increment signal in accordance with the first and second clocks; An address generator which increases an address according to the address increase signal and determines whether an address generated according to a read and write selection signal of the address controller is read or write; And A RAM for storing input data and outputting the data according to the address signal of the address generator; And the address controller controls the address generator to generate a write address after data is written to the RAM by a predetermined ratio or more. A clock generator which generates a second clock having an average period of the first clock; An address controller configured to generate read and write selection signals and an address increment signal in accordance with the first and second clocks; An address generator which increases an address according to the address increase signal and determines whether an address generated according to a read and write selection signal of the address controller is read or write; And A RAM for storing input data and outputting the data according to the address signal of the address generator; And the address control unit controls the address generation unit to generate a read address generation in preference to a write address generation so that data can be read at predetermined time intervals when data is output from the RAM. The method according to claim 2 or 3, The clock generator includes a first counter for counting the first clock; A comparator for determining whether a counting value of the first counter reaches a predetermined value; An AND gate for disabling a third clock according to the result of the comparator; A second counter counting an output of the AND gate; And And a clock generator for changing a clock period according to the counting value of the second counter. The method according to claim 2 or 3, The address generator may include: a read address generator for increasing a read address according to the address increase signal; A write address generator for increasing a write address according to the address increase signal; And And a multiplexer for selectively outputting an address generated from the read address generator and the write address generator in accordance with the read and write select signals.