KR100366091B1 - Plasma display panel having assistance electrode for reset, and drive method therefor - Google Patents

Abstract

The plasma display panel according to the present invention has a first substrate and a second substrate spaced apart from each other. X electrode lines, Y electrode lines and address electrode lines are aligned between the first and second substrates, X electrode lines are aligned parallel to the Y electrode lines, and address electrode lines are X electrode lines and Y electrodes Aligned orthogonally to the lines, pixels corresponding to each intersection are defined. Here, at least one reset auxiliary electrode line adjacent to and parallel to each pair of Y electrode lines and X electrode lines is formed. In addition, the driving method of the plasma display panel according to the present invention includes a reset step, an address step and a sustain-discharge step. In the reset phase, two steps are performed. In the first step, a voltage of a first polarity is applied to all the reset auxiliary electrode lines, so that wall charges of a second polarity opposite to the first polarity are formed around all the reset auxiliary electrode lines. In the second step, a voltage of a first polarity which increases in proportion to time is applied to all the Y electrode lines and the X electrode lines, so that wall charges of the second polarity are formed around all the Y electrode lines and the X electrode lines. do.

Description

Plasma display panel having assistance electrode for reset and driving method therefor}

The present invention relates to a plasma display panel and a driving method thereof, and more particularly, to a plasma display panel of a three-electrode surface discharge method and a driving method thereof.

1 shows a structure of a conventional three-electrode surface discharge plasma display panel. 2 illustrates a unit discharge cell of the panel of FIG. 1. Referring to the drawings, between the front and rear glass substrates 10 and 13 of the general surface discharge plasma display panel 1, the address electrode lines A _R1 ,..., A _Bm , the dielectric layers 11 and 15 ), Y electrode lines (Y ₁ , ..., Y _n ), X electrode lines (X ₁ , ..., X _n ), fluorescent layer 16, partition wall 17 and magnesium monoxide as protective layer (MgO) layer 12 is provided.

The address electrode lines A _R1 ,..., A _Bm are formed in a predetermined pattern on the front surface of the rear glass substrate 13. The lower dielectric layer 15 is formed in front of the address electrode lines A _R1 ,..., A _Bm . The barrier ribs 17 are formed on the front surface of the lower dielectric layer 15 in a direction parallel to the address electrode lines A _R1 ,..., A _Bm . These partitions 17 function to partition the discharge area of each discharge cell and to prevent optical cross talk between each discharge cell. The fluorescent layer 16 is formed between the partition walls 17.

The X electrode lines X ₁ , ..., X _n and the Y electrode lines Y ₁ , ..., Y _n are orthogonal to the address electrode lines A _R1 , ..., A _Bm . The rear surface of the front glass substrate 10 is formed in a predetermined pattern. Each intersection defines a corresponding discharge cell. Each X electrode line (X ₁ , ..., X _n ) and each Y electrode line (Y ₁ , ..., Y _n ) are indium tin oxide (ITO) electrode lines (X _{na in} FIG. 3) of a transparent conductive material. , Y _na ) and a bus electrode line (X _nb , Y _nb of FIG. 3) of a metal material are formed to be combined with each other. The upper dielectric layer 11 is formed after the X electrode lines X ₁ ,..., X _n and the Y electrode lines Y ₁ ,..., Y _n . A magnesium monoxide (MgO) layer 12 for protecting the panel 1 from a strong electric field is formed by applying the entire surface to the back surface of the upper dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

The driving method basically applied to the plasma display panel is a method in which the reset, address and sustain-discharge steps are sequentially performed in the unit subfield. In the reset step, the residual wall charges in the previous subfield are erased and driven so that the space charges are generated evenly. In the address step, the wall charges are driven to be formed in the selected discharge cells. In the sustain-discharge step, light is driven in discharge cells in which wall charges are formed in the addressing discharge step. That is, when a pulse of a relatively high voltage is alternately applied to all the X electrode lines X ₁ , ..., X _n and all the Y electrode lines Y ₁ , ..., Y _n , the wall charge Causes surface discharge in the formed discharge cells. At this time, a plasma is formed in the gas layer, and the fluorescent layer 16 is excited by the ultraviolet radiation to generate light.

3 shows driving signals applied to respective electrode lines for reset discharge in the panel of FIG. 1. Reference numerals in FIG. 3 S _Y1, ..., S _Yn by reference to the driving signals applied to all the Y electrode lines _{(Y 1, ..., Y n} ), reference numeral S _X1, ..., S _Xn is The driving signals applied to all the X electrode lines X ₁ , ..., X _n , and reference symbols S _AR1 , ..., S _{ABm denote} all the address electrode lines A _R1 , ..., A _Bm ) indicates the driving signals applied to each. The driving signals of FIG. 3 retain positive and negative wall charges around the X electrode of the pixels that were selected in the previous subfield and caused sustain-discharge, and negative (+) wall charges around the Y electrode. Applies if If the polarities of the residual wall charges are opposite, the driving signals S _X1 , ..., S _Xn should be applied to all the Y electrode lines Y ₁ , ..., Y _n , and the driving signals S _Y1 , ..., S _Yn should be applied to all X electrode lines (X ₁ , ..., X _n ). The reason is to increase the efficiency of the discharge.

Referring to Figure 3, the voltage at the first time (T _R1), the signals applied to all the X electrode lines (X _1, ..., X _n) (S _X1, ..., _Xn S) in proportion to the time increases to a first voltage (V ₃₁₎ of the positive polarity (+). Accordingly, negative (−) wall charges are formed around all the X electrode lines (X ₁ ,..., X _n ), and around all Y electrode lines (Y ₁ , ..., Y _n ). Bipolar (+) wall charges are formed.

At the second time T _R2 , the voltages of the signals S _Y1 , ..., S _Yn applied to all the Y electrode lines Y ₁ ,..., And Y _n are 0 volts (the ground voltage). after higher V) to the second voltage (V ₃₂₎ of the positive polarity (+), the time increases in proportion to the to the third voltage (V ₃₃₎ of the positive polarity (+). Accordingly, the negative (−) wall charges are sufficiently formed around all the Y electrode lines Y ₁ ,..., Y _n .

At the third time T _R3 , all of the Y electrode lines in a state in which the first positive voltage V ₃₁ of the positive polarity (+) is applied to all of the X electrode lines X ₁ ,..., X _n . The voltages of the signals S _Y1 , ..., S _Yn applied to (Y ₁ , ..., Y _n ) are 0 volts (the ground voltage at the second voltage V ₃₂ of positive polarity (+). Lower to V). Accordingly, the negative (−) wall charges are uniformly formed around all the X electrode lines X ₁ ,..., X _n and the Y electrode lines (Y ₁ ,..., Y _n ).

According to the conventional surface discharge plasma display panel and the driving method thereof, all the X electrode lines (X ₁ , ..., X _n ) and all the Y electrode lines (Y ₁ , ..., Y _n ) As a direct reset discharge is performed by using only, there are the following problems.

First, the time T _R2 for sufficient wall charges to form around all Y electrode lines (Y ₁ , ..., Y _n ), and all X electrode lines (X ₁ , ..., X _n ) Since the time T _R3 is required to uniformly form negative (−) wall charges around the Y electrode lines Y ₁ ,..., And Y _n , the overall reset time is long. Accordingly, the contrast of the plasma display device is relatively low. In addition, since the time allocated to sustain discharge in the unit sub-field becomes relatively short, the luminance of the plasma display device is relatively low.

Second, since a high voltage V ₃₃ is applied in proportion to the distance between the X electrode line and the Y electrode line, relatively bright light is emitted through the screen in the reset step. As a result, the contrast of the plasma display device is lowered, and the power consumption is increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a plasma display panel and a method of driving the same which enable the luminance and contrast of the plasma display device to be high and the power consumption to be low.

1 is an internal perspective view showing the structure of a conventional three-electrode surface discharge plasma display panel.

2 is a cross-sectional view illustrating a unit discharge cell of the panel of FIG. 1.

3 is a timing diagram illustrating driving signals applied to respective electrode lines for reset discharge in the panel of FIG. 1.

4 is an internal perspective view showing the structure of a three-electrode surface discharge plasma display panel according to an embodiment of the present invention.

FIG. 5 is a timing diagram illustrating driving signals applied to respective electrode lines for reset discharge in the panel of FIG. 4.

FIG. 6 is a diagram illustrating a wall voltage state of a unit discharge cell when application of the driving signals of FIG. 5 is terminated.

FIG. 7 is an internal perspective view illustrating a structure of a three-electrode surface discharge plasma display panel according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

1 ... plasma display panel, 10 ... front glass substrate,

11, 15 dielectric layer, 12 magnesium monoxide layer,

13 ... back glass substrate, 14 ... discharge space,

16 fluorescent layers, 17 bulkheads,

X ₁ , ..., X _n ... X electrode line, Y ₁ , ..., Y _n ... Y electrode line,

A _R1 , ..., A _Bm ... address electrode line, X _na , Y _na ... ITO electrode line,

X _nb , Y _nb ... bus electrode line.

The surface discharge plasma display panel of the present invention for achieving the above object has a first substrate and a second substrate spaced apart from each other. X electrode lines, Y electrode lines, and address electrode lines are aligned between the first and second substrates, the X electrode lines are aligned in parallel with the Y electrode lines, and the address electrode lines are at the X electrode. Aligned orthogonally to the lines and the Y electrode lines, a pixel corresponding to each intersection point is defined. Here, at least one reset auxiliary electrode line adjacent to each of the pair of Y electrode lines and X electrode lines is formed in parallel.

In addition, a method of driving the surface discharge plasma display panel for achieving the above object includes a reset step, an address step and a sustain-discharge step in a unit sub-field. In the reset step, the charge distribution state of each pixel becomes uniform. In the address step, wall charges are formed in the selected pixels while a scan driving signal is applied to the Y electrode lines while display data signals are applied to the address electrode lines. In the sustain-discharge step, light is generated in the selected pixels by applying an alternating voltage to the X electrode lines and the Y electrode lines after wall charges are formed in the selected pixels.

Here, two steps are performed in the reset step. In a first step, a voltage of a first polarity is applied to all of the reset auxiliary electrode lines, so that wall charges of a second polarity opposite to the first polarity are formed around all of the reset auxiliary electrode lines. . In a second step, a voltage of the first polarity which increases in proportion to time is applied to all the Y electrode lines and the X electrode lines, so that the second polarity is around all the Y electrode lines and the X electrode lines. Wall charges are formed.

According to the plasma display panel and the driving method thereof of the present invention, indirect reset discharge is performed by using respective auxiliary auxiliary electrode lines adjacent to and parallel to each pair of the Y electrode lines and the X electrode lines. The execution time of the reset step can be shortened and the upper limit voltage can be lowered. As a result, dark light is emitted during a short reset time, so that the contrast of the plasma display device is high and power consumption is low. In addition, since the time allocated to sustain discharge in the unit sub-field becomes relatively long, the luminance of the plasma display device is relatively high.

Hereinafter, preferred embodiments of the present invention will be described in detail.

Figure 4 shows the structure of a three-electrode surface discharge plasma display panel according to an embodiment of the present invention. In FIG. 4, the same reference numerals as used in FIG. 1 indicate objects of the same function.

4, the respective Y electrode lines (Y _1, ..., Y _n) and the X-electrode lines (X _1, ..., X _n) 1 of the reset line for the auxiliary electrode in the center of the pair ( C ₁ , ..., C _n ) is formed. Drive signals applied to the respective electrode lines for the reset discharge in such a panel are shown in FIG. 5.

Reference numerals in Figure 5 S _Y1, ..., S _Yn by reference to the driving signals applied to all the Y electrode lines _{(Y 1, ..., Y n} ), reference numeral S _X1, ..., S _Xn is For driving signals applied to all X electrode lines (X ₁ , ..., X _n ), reference numerals S _C1 , ..., S _Cn denote all reset auxiliary electrode lines (C ₁ , ..., C _n ), and reference numerals S _AR1 , ..., S _ABm indicate driving signals applied to all address electrode lines A _R1 , ..., A _Bm , respectively.

5, of the first time (T _R1), the signals being applied to all of the auxiliary electrode line for reset (C _1, ..., C _n) (S _C1, ..., _Cn S) The voltage is increased in proportion to time to the first voltage V ₅₁ of positive polarity (+). Accordingly, negative (−) wall charges are formed around all of the reset auxiliary electrode lines C ₁ ,..., C _n .

At the second time T _R2 , the signals S _Y1 , ..., S _Yn and all the X electrode lines X ₁ applied to all the Y electrode lines Y ₁ ,..., Y _n . The voltages of the signals S _X1 , ..., S _Xn applied to _,, ..., X _n are from 0 volt (V), the ground voltage, to the second voltage (V ₅₂ ) of the positive polarity (+). After the increase, the voltage is increased up to the third voltage V ₅₃ of positive polarity in proportion to time. Accordingly, all the Y electrode lines (Y _1, ..., Y _n) and all the X electrode lines negative polarity around the _{(X 1, ..., X n} ) (-) wall charges are formed uniformly .

FIG. 6 illustrates a wall voltage state of a unit discharge cell when the application of the driving signals of FIG. 5 is terminated. In FIG. 6, the same reference numerals as used in FIG. 2 indicate objects of the same function. Referring to FIG. 6, the negative (−) wall charges are uniform around all Y electrode lines (Y ₁ , ..., Y _n ) and all X electrode lines (X ₁ , ..., X _n ). It can be seen that the wall voltage (-V _W ) is also uniform because it is formed.

According to the panel structure and the reset driving method as above, in parallel with respect to the adjacent pairs of the respective Y electrode lines (Y _1, ..., Y _n) and the X-electrode lines (X _1, ..., X _n) Each reset auxiliary electrode line C ₁ , ..., C _n is used to perform indirect reset discharge. Accordingly, half of the negative (−) wall charges formed around the Y electrode line (Y ₁ , ..., Y _n ) in the conventional reset step is X electrode line (X ₁ , ..., X _n ). The third time to move around (T _{R3 in} FIG. ₃ ) can be omitted. In addition, the first time T _R1 and the second time T _R2 may also be shorter than the first time T _R1 of FIG. 3 and the second time T _R2 of FIG. 3, respectively, in the conventional reset step. have. In addition, the upper limit voltage V ₅₃ may also be lower than the upper limit voltage V ₃₃ in the conventional reset step.

7 shows a structure of a plasma display panel of a three-electrode surface discharge method according to another embodiment of the present invention. In FIG. 7, the same reference numerals as used in FIG. 1 indicate objects of the same function.

Referring to FIG. 7, one reset auxiliary electrode line C _Y1 , ..., C _Yn is formed on one side of each Y electrode line Y ₁ , ..., Y _n , and each X is formed. One reset auxiliary electrode line C _X1 , ..., C _Xn is formed on one side of the electrode line X ₁ ,..., X _n . The reset driving method is as described in the first embodiment with reference to FIGS. 5 and 6, and will be omitted. Here, reference numerals S _C1 , ..., S _Cn of FIG. 5 denote driving signals applied to all the reset auxiliary electrode lines C _Y1 , ..., C _Yn , C _X1 , ..., C _Xn . Point to them. Compared with the first embodiment, there is a disadvantage in that the auxiliary electrode lines for resetting are twice as many as those of the present invention, which further increases the effect of the present invention.

As described above, according to the plasma display panel and the driving method thereof according to the present invention, indirect reset is performed by using respective auxiliary auxiliary electrode lines for parallel adjacent to each pair of Y electrode lines and X electrode lines. Since the discharge is performed, the execution time of the reset step can be shortened and the upper limit voltage can be lowered. As a result, dark light is emitted during a short reset time, so that the contrast of the plasma display device is high and power consumption is low. In addition, since the time allocated to sustain discharge in the unit sub-field becomes relatively long, the luminance of the plasma display device is relatively high.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the claims.

Claims (4)

A first substrate and a second substrate spaced apart from each other, wherein X electrode lines, Y electrode lines, and address electrode lines are aligned between the first and second substrates, and the X electrode lines are the Y electrode lines A surface discharge plasma display panel, wherein the address electrode lines are aligned in parallel with each other, and the address electrode lines are orthogonally aligned with respect to the X electrode lines and the Y electrode lines, so that a pixel corresponding to each intersection point is defined. And at least one reset auxiliary electrode line adjacent to each of the pair of Y and X electrode lines in parallel with each other. 2. The surface discharge plasma display panel according to claim 1, wherein one reset auxiliary electrode line is formed at the center of each of the pair of Y electrode lines and X electrode lines. The surface discharge plasma display panel of claim 1, wherein one auxiliary electrode line for reset is formed on one side of each of the Y electrode lines, and one auxiliary electrode line for reset is formed on one side of each of the X electrode lines. . A first substrate and a second substrate spaced apart from each other, wherein X electrode lines, Y electrode lines, and address electrode lines are aligned between the first and second substrates, and the X electrode lines are the Y electrode lines And the address electrode lines are orthogonally aligned with respect to the X electrode lines and the Y electrode lines, so that a pixel corresponding to each intersection point is defined, and each of the Y electrode line and the X electrode line A driving method of a surface discharge plasma display panel in which at least one reset auxiliary electrode line adjacent to a pair is disposed in parallel with each other, A reset step in which the charge distribution state of each pixel is uniform, and an address step in which wall charges are formed in selected pixels while a scan driving signal is applied to the Y electrode lines while display data signals are applied to the address electrode lines. And a sustain-discharge step in which light is generated in the selected pixels by applying an alternating voltage to the X electrode lines and the Y electrode lines after wall charges are formed in the selected pixels, in the unit sub-field, In the reset step, Applying a voltage of a first polarity to all of the reset auxiliary electrode lines to form wall charges of a second polarity opposite to the first polarity around all of the reset auxiliary electrode lines; And Applying the voltage of the first polarity which increases in proportion to time to all the Y electrode lines and the X electrode lines, thereby forming wall charges of the second polarity around all the Y electrode lines and the X electrode lines; A method of driving a surface discharge plasma display panel in which a step is performed.