KR100369347B1 - Method for fabricating coil - Google Patents
Method for fabricating coil Download PDFInfo
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- KR100369347B1 KR100369347B1 KR10-2000-0084461A KR20000084461A KR100369347B1 KR 100369347 B1 KR100369347 B1 KR 100369347B1 KR 20000084461 A KR20000084461 A KR 20000084461A KR 100369347 B1 KR100369347 B1 KR 100369347B1
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- South Korea
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- film
- metal film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
- H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
- H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
- H01F41/041—Printed circuit coils
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Coils Or Transformers For Communication (AREA)
- Manufacturing Cores, Coils, And Magnets (AREA)
Abstract
본 발명은 집적회로 외부에 별도로 제조함에 따른 소자의 면적 증가를 방지하고 컨덕턴스 특성을 개선시키도록 한 코일의 제조 방법에 관한 것으로, 반도체기판상에 제 1 유전막을 형성하는 단계, 상기 제 1 유전막을 선택적으로 식각하여 반원통형 요부를 형성하는 단계, 상기 반원통형 요부의 표면상에 나선형 제 1 금속막패턴을 형성하는 단계;, 상기 제 1 금속막패턴을 포함한 전면에 제 2 유전막을 형성하는 단계, 상기 제 1 금속막패턴 상부에만 상기 제 2 유전막을 잔류시키는 단계, 상기 잔류된 제 2 유전막을 리플로우시켜 상기 제 1 금속막패턴상에 원통형 유전막 막대를 형성하는 단계, 및 상기 유전막 막대상에 상기 제 1 금속막패턴의 일측에 접속되는 나선형 제 2 금속막패턴을 형성하는 단계를 포함하여 이루어진다.The present invention relates to a method of manufacturing a coil to prevent an increase in the area of a device and to improve conductance characteristics by separately fabricating an external circuit, and to form a first dielectric film on a semiconductor substrate. Selectively etching to form a semi-cylindrical recess, forming a spiral first metal film pattern on the surface of the semi-cylindrical recess, forming a second dielectric film on the entire surface including the first metal film pattern; Remaining the second dielectric film only on the first metal film pattern, reflowing the remaining second dielectric film to form a cylindrical dielectric film rod on the first metal film pattern, and And forming a spiral second metal film pattern connected to one side of the first metal film pattern.
Description
본 발명은 집적 회로(Intergrated circuit)에 관한 것으로서, 특히 작은 면적, 큰 전도성(Conductance)를 필요로하는 장치 및 통신 장치에 적용가능한 집적 코일(Coil)의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to integrated circuits, and more particularly, to a device requiring a small area, a large conductance, and a manufacturing method of an integrated coil applicable to a communication device.
일반적으로 코일을 집적회로내에 제조하지 않고 외부에 별도로 제조하여 인쇄회로기판(Printed Circuit Board; PCB)을 이용하여 집적회로와 연결하여 사용하므로써 상대적으로 큰 면적을 차지하는 코일로 인하여 장치의 소형화를 이루는데 많은 어려움이 있다.In general, the coil is not manufactured in an integrated circuit, but manufactured separately to connect to an integrated circuit using a printed circuit board (PCB) to achieve a miniaturization of a device due to a coil occupying a relatively large area. There are many difficulties.
도 1은 종래기술에 따른 코일을 도시한 도면으로서, 유전막 막대(11)에 물리적으로 구리선(12)을 감아서 형성한다.1 is a view illustrating a coil according to the prior art, and is formed by winding a copper wire 12 physically on a dielectric film rod 11.
그러나, 상술한 것처럼 종래기술의 코일은 유전막 막대(11)에 구리선(12)을 감아서 형성하므로 부피가 매우 클 수 밖에 없으며, 집적회로내에 형성하지 못하고 별도로 형성하여 집적회로와 연결하기 때문에 소자의 면적이 증가하는 문제점이 있다.However, as described above, the coil of the prior art is formed by winding the copper wire 12 on the dielectric film rod 11, which is inevitably very large, and is not formed in the integrated circuit, but formed separately and connected to the integrated circuit. There is a problem that the area is increased.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 집적회로와 별도로 제조함에 따른 소자의 면적 증가를 방지하는데 적합한 코일의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art, an object of the present invention is to provide a method for manufacturing a coil suitable for preventing the increase in the area of the device by manufacturing separately from the integrated circuit.
도 1은 종래기술에 따른 코일을 도시한 도면,1 is a view showing a coil according to the prior art,
도 2a 내지 도 2d는 본 발명의 실시예에 따른 코일의 제조 방법을 도시한 공정 단면도,2A to 2D are cross-sectional views illustrating a method of manufacturing a coil according to an embodiment of the present invention;
도 3은 본 발명의 실시예에 따른 코일의 평면도.3 is a plan view of a coil according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 유전막21 semiconductor substrate 22 dielectric film
22a : 반원통형 요부 23, 26 : 감광막22a: semi-cylindrical recess 23, 26: photosensitive film
24 : 제 1 금속막패턴 25 : BPSG24: first metal film pattern 25: BPSG
25a : 원통형 BPSG 막대 27 : 제 2 금속막패턴25a: cylindrical BPSG rod 27: second metal film pattern
상기의 목적을 달성하기 위한 본 발명의 코일의 제조 방법은 반도체기판상에제 1 유전막을 형성하는 단계, 상기 제 1 유전막을 선택적으로 식각하여 반원통형 요부를 형성하는 단계, 상기 반원통형 요부의 표면상에 나선형 제 1 금속막패턴을 형성하는 단계;, 상기 제 1 금속막패턴을 포함한 전면에 제 2 유전막을 형성하는 단계, 상기 제 1 금속막패턴 상부에만 상기 제 2 유전막을 잔류시키는 단계, 상기 잔류된 제 2 유전막을 리플로우시켜 상기 제 1 금속막패턴상에 원통형 유전막 막대를 형성하는 단계, 및 상기 유전막 막대상에 상기 제 1 금속막패턴의 일측에 접속되는 나선형 제 2 금속막패턴을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.Method of manufacturing a coil of the present invention for achieving the above object comprises the steps of forming a first dielectric film on a semiconductor substrate, selectively etching the first dielectric film to form a semi-cylindrical recess, the surface of the semi-cylindrical recess Forming a spiral first metal film pattern on the surface, forming a second dielectric film on the entire surface including the first metal film pattern, and leaving the second dielectric film only on the first metal film pattern; Reflowing the remaining second dielectric film to form a cylindrical dielectric film rod on the first metal film pattern, and forming a spiral second metal film pattern connected to one side of the first metal film pattern on the dielectric film bar. Characterized in that it comprises a step.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2d는 본 발명의 실시예에 따른 코일의 제조 방법을 도시한 도면이다.2A to 2D illustrate a method of manufacturing a coil according to an exemplary embodiment of the present invention.
도 2a에 도시된 바와 같이, 반도체 기판(21)상에 유전막(22)을 형성한 후, 유전막(22)상에 감광막(23)을 도포하고 노광 및 현상으로 감광막(23)을 패터닝한다. 계속해서, 패터닝된 감광막(23)을 마스크로 이용하여 유전막(22)을 습식식각하여 반원통형 요부(22a)를 형성한다.As shown in FIG. 2A, after the dielectric film 22 is formed on the semiconductor substrate 21, the photosensitive film 23 is coated on the dielectric film 22, and the photosensitive film 23 is patterned by exposure and development. Subsequently, the dielectric film 22 is wet-etched using the patterned photosensitive film 23 as a mask to form the semi-cylindrical recess 22a.
여기서, 유전막(22)은 CVD(Chemical Vapor Deposition) 산화막, 열산화막 또는 BPSG(Boro Phospho Silicate Glass) 중 어느 하나를 이용한다.Here, the dielectric film 22 uses any one of a chemical vapor deposition (CVD) oxide film, a thermal oxide film, or Boro Phospho Silicate Glass (BPSG).
도 2b에 도시된 바와 같이, 패터닝된 감광막(23)을 제거한 후, 전면에 제 1금속막을 증착하고, 제 1 금속막상에 감광막을 도포하고 노광 및 현상으로 감광막을 패터닝한다. 계속해서, 패터닝된 감광막을 마스크로 이용하여 제 1 금속막을 식각하여 반원통형 요부(22a) 표면에만 나선형 제 1 금속막패턴(24)을 형성한다.As shown in FIG. 2B, after the patterned photoresist film 23 is removed, a first metal film is deposited on the entire surface, a photoresist film is applied on the first metal film, and the photoresist film is patterned by exposure and development. Subsequently, the first metal film is etched using the patterned photosensitive film as a mask to form the spiral first metal film pattern 24 only on the surface of the semi-cylindrical recess 22a.
여기서, 나선형 제 1 금속막패턴(24)은 구리(Cu) 또는 알루미늄(Al) 중 어느 하나를 이용한다.Here, the spiral first metal film pattern 24 uses either copper (Cu) or aluminum (Al).
도 2c에 도시된 바와 같이, 제 1 금속막패턴(24) 형성시 이용된 감광막을 제거하고, 전면에 BPSG(25)를 형성한다. 계속해서, BPSG(25)상에 감광막(26)을 도포하고 노광 및 현상으로 감광막(26)을 패터닝한 후, 패터닝된 감광막(26)을 마스크로 이용하여 BPSG(25)을 습식 식각한다. 이 때, BPSG(25)는 습식식각후, 제 1 금속막패턴(24)상에만 잔류한다.As shown in FIG. 2C, the photoresist film used when the first metal film pattern 24 is formed is removed, and the BPSG 25 is formed on the entire surface. Subsequently, the photoresist film 26 is applied onto the BPSG 25, and the photoresist film 26 is patterned by exposure and development. Then, the BPSG 25 is wet-etched using the patterned photoresist film 26 as a mask. At this time, the BPSG 25 remains only on the first metal film pattern 24 after the wet etching.
도 2d에 도시된 바와 같이, 습식식각된 BPSG(25)을 리플로우(Reflow)시켜 원통형 BPSG 막대(25a)를 형성한 후, 전면에 제 2 금속막을 증착한다. 계속해서, 제 2 금속막을 선택적으로 패터닝하여 제 1 금속막패턴(24)의 일측에 접속되는 나선형 제 2 금속막패턴(27)을 형성한다. 여기서, 제 2 금속막패턴(27)은 제 1 금속막패턴(22)과 동일하게 구리 또는 알루미늄 중 어느 하나를 이용한다.As shown in FIG. 2D, the wet etched BPSG 25 is reflowed to form a cylindrical BPSG rod 25a, and then a second metal film is deposited on the entire surface. Subsequently, the second metal film is selectively patterned to form a spiral second metal film pattern 27 connected to one side of the first metal film pattern 24. Here, the second metal film pattern 27 uses either copper or aluminum in the same manner as the first metal film pattern 22.
이 때, 하부의 제 1 금속막패턴(24)과 상부의 제 2 금속막패턴(27)은 원통형 BPSG 막대(25a)를 감고 있는 형태를 갖는데, 도 3에 도시된 바와 같이, 제 1 금속막패턴(24) 및 제 2 금속막패턴(27)은 나선형태로 형성됨에 따라 제 1 금속막패턴(24)의 일측과 제 2 금속막패턴(27)의 일측이 접속되고, 제 2 금속막패턴(27)의 타측과 다른 제 1 금속막패턴의 일측이 접속되어 계속 이어지는 나선 형태의 코일을 형성한다.At this time, the lower first metal film pattern 24 and the upper second metal film pattern 27 have a shape in which a cylindrical BPSG rod 25a is wound. As shown in FIG. 3, the first metal film As the pattern 24 and the second metal film pattern 27 are formed in a spiral shape, one side of the first metal film pattern 24 is connected to one side of the second metal film pattern 27, and the second metal film pattern is connected. The other side of (27) and one side of the other first metal film pattern are connected to form a spiral coil that continues.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 코일의 제조 방법은 반도체 소자의 제조 공정을 이용하여 집적회로내에 제조하므로써 인덕턴스(Inductance)를 필요로하는 회로 구성시 필요로 하는 비용이 절감되며, 단일 집적회로내에 외부 코일을 위한 넓은 공간이 불필요하므로 코일을 적용하는 소자의 면적을 감소시킬 수 있는 효과가 있다.The coil manufacturing method of the present invention as described above is manufactured in the integrated circuit using the manufacturing process of the semiconductor device, the cost required to configure the circuit requiring inductance (Inductance) is reduced, the external coil in a single integrated circuit Since there is no need for a large space, there is an effect that can reduce the area of the device applying the coil.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0084461A KR100369347B1 (en) | 2000-12-28 | 2000-12-28 | Method for fabricating coil |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0084461A KR100369347B1 (en) | 2000-12-28 | 2000-12-28 | Method for fabricating coil |
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| Publication Number | Publication Date |
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| KR20020055104A KR20020055104A (en) | 2002-07-08 |
| KR100369347B1 true KR100369347B1 (en) | 2003-01-24 |
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| KR10-2000-0084461A Expired - Fee Related KR100369347B1 (en) | 2000-12-28 | 2000-12-28 | Method for fabricating coil |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980042515A (en) * | 1996-11-19 | 1998-08-17 | 윤종용 | Integrated circuit inductor and manufacturing method |
| US5863806A (en) * | 1996-11-21 | 1999-01-26 | United Microelectronics Corp. | Method of forming microcoil structure for integrated circuits |
| KR19990027353A (en) * | 1997-09-29 | 1999-04-15 | 구본준 | Inductor manufacturing method of semiconductor device |
| KR19990084726A (en) * | 1998-05-11 | 1999-12-06 | 김영환 | Inductor manufacturing method of semiconductor device |
-
2000
- 2000-12-28 KR KR10-2000-0084461A patent/KR100369347B1/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980042515A (en) * | 1996-11-19 | 1998-08-17 | 윤종용 | Integrated circuit inductor and manufacturing method |
| US5863806A (en) * | 1996-11-21 | 1999-01-26 | United Microelectronics Corp. | Method of forming microcoil structure for integrated circuits |
| KR19990027353A (en) * | 1997-09-29 | 1999-04-15 | 구본준 | Inductor manufacturing method of semiconductor device |
| KR19990084726A (en) * | 1998-05-11 | 1999-12-06 | 김영환 | Inductor manufacturing method of semiconductor device |
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| KR20020055104A (en) | 2002-07-08 |
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