KR100369351B1 - Data input buffer of semiconductor device - Google Patents

Abstract

The present invention provides a data input buffer of a semiconductor device capable of reducing power consumption by standby current and static current. According to the present invention, the PMOS transistor included in the input buffer is not turned on unnecessarily by lowering the power supply voltage by the threshold voltage and supplying it to the input buffer without supplying the power supply voltage for driving the chip as it is. A chip power supply line VCC supplied with a chip power supply potential; A power supply voltage drop unit 200 coupled to the chip power supply line to lower the chip power supply potential by a predetermined voltage to provide a TTL-power supply potential; A TTL-power line (TVCCL) coupled to the power supply voltage drop to supply a TTL-power potential; An input data line DIN and an enable signal line / EN through which input data and an enable signal are transmitted, respectively; Combination logic 400 and combinatorial logic driven by a TTL-power potential delivered through a TTL-power line and coupled to the input data line and the enable signal line to deliver input data when the enable signal is active. Inverter unit 300 for inverting the negative output.

Description

DATA INPUT BUFFER OF SEMICONDUCTOR DEVICE}

The present invention relates to an input buffer circuit of a semiconductor device, and more particularly to a TTL-input buffer circuit of a semiconductor device capable of reducing static current consumption.

1 is a circuit diagram illustrating an example of a TTL-input buffer circuit of a semiconductor device according to the prior art.

Referring to FIG. 1, the TTL-input buffer circuit includes a NOR gate NR and an inverter INV1. The NOR gate NR is composed of PMOS transistors MP0 and MP1 and NMOS transistors MN0 and MN1, and input data applied through the pad PAD when the enable signal / EN is at the "low" level. The signal DIN is inverted and output, and the output of the NOR gate NR is inverted by the inverter INV1 and transferred to the internal circuit as data DATA. For semiconductor devices operating at a supply voltage of 3.0 / 3.3V, the TTL input is 2.2 / 0.4V. Therefore, even when the enable signal / EN is at the "low" level and the PMOS transistor MP0 is turned on, if the data DIN input through the data pad PAD is 0.4V, the NMOS transistor MN1 is not turned on. Will not. Therefore, the inversion data terminal / DATA is at the "high" level, and the output of the inverter INV1 is at the "low" level.

In contrast, when the data signal input through the data pad PAD is 2.2V, the NMOS transistor MN1 is turned on (in this case, V _GS = 2.2V) and the PMOS transistor MP1 may be weakly turned on ( In this case, V _GS = V _CC -2.2V). Specifically, considering the ± 10% variation in the 3.3V supply voltage, the power supply potential (VCC) is 2.97≤VCC≤3.63. In addition, the threshold voltage of a transistor manufactured by a general CMOS process can be regarded as 0.8V. Therefore, in the worst case, the voltage applied between the gate and the source of the PMOS transistor MP1 is 1.43V, which is not less than 0.8V, which is the threshold voltage Vt. Thus, the PMOS transistor MP1 may be weakly turned on. Thus, there is a problem in that a current path is formed in the NOR gate NR, and in some cases, a current path is formed in the next stage inverter. Such a current becomes a main component of the standby current or the static current, and there is a problem of unnecessary power consumption.

Accordingly, it is an object of the present invention to provide an input buffer circuit of a semiconductor device which can reduce the static current.

Another object of the present invention is to provide an input buffer circuit of a semiconductor device which can reduce power consumption.

1 is a circuit diagram of a TTL-input buffer circuit according to the prior art.

2 is a circuit diagram of a TTL-input buffer circuit in accordance with an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

200... Power supply voltage drop

300... Inverter section

400... NOR gate part

VCC… Chip power lines

TVCCL… TTL-power line

In order to achieve the above object, in the present invention, the PMOS transistor is unnecessarily included in the input buffer by supplying it to the input buffer by lowering the power supply voltage by a threshold voltage without supplying the power supply voltage for driving the chip as it is. Was not turned on.

A data input buffer of a semiconductor device according to an aspect of the present invention includes a chip power supply line (VCC) to which a chip power supply potential is supplied; A power supply voltage drop unit 200 coupled to the chip power line to lower the chip power potential by a predetermined voltage to provide a TTL-power potential; A TTL-power line (TVCCL) coupled to the power supply voltage drop to supply the TTL-power potential; An input data line DIN and an enable signal line / EN through which input data and an enable signal are transmitted, respectively; Combination logic 400, driven by a TTL-power potential delivered through the TTL-power line, coupled to the input data line and the enable signal line to transfer input data when the enable signal is active. It includes. In addition, the data input buffer of the semiconductor device further includes an inverter unit 300 for inverting the output of the combinational logic unit.

According to a preferred embodiment of the invention, the voltage drop comprises a diode connected in a forward direction between the chip power line and the TTL-power line. This diode may consist of a diode-connected PMOS transistor (PTTL) or a diode-connected NMOS transistor.

The power supply voltage drop includes: a resistor (RXF) coupled between the cathode of the diode and the TTL-power line; It may further include a capacitor CXF coupled between the TTL-power line and ground.

The combinational logic portion is composed of a NOR gate, which includes an inversion data terminal (/ DATA) provided with an output of the NOR gate; Two PMOS transistors (MP0, MP1) in which the enable signal and the data are applied to respective gates and whose source-drain paths are coupled in series between the TTL-power line and the inverting data terminal; The enable signal and the data are applied to their respective gates and their drain-source paths comprise two NMOS transistors (MN0, MN1) coupled in parallel between the inverted data terminal and ground.

The inverter unit may include a CMOS inverter including a PMOS transistor MP2 and an NMOS transistor MN2. In addition, the inverter unit 300 may further include a diode connected forward between the chip power line and the source of the PMOS transistor, which diode may comprise a diode-connected PMOS transistor (MPD) or a diode-connected NMOS. It may be composed of a transistor. The inverter section further comprises: a data terminal DATA provided with an output of the inverter section; A pull-up PMOS transistor (MPFB) having a source coupled to the chip power line and a drain coupled to the data terminal; The electronic device may further include a feedback inverter IFB for inverting a signal of the data terminal and applying the inverted signal to a gate of the pull-up PMOS transistor.

Next, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram illustrating a TTL-input buffer circuit of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2, the input buffer of the semiconductor device includes a power supply voltage drop unit 200, a NOR gate unit 400, and an inverter unit 300. The power supply voltage dropping unit 200 includes a PMOS transistor PTTL, a resistor RXF, and a capacitor CXF. The source of the PMOS transistor PTTL is coupled to the chip power line VCC, and the gate and the drain are commonly coupled to act as a diode. The resistor RXF is coupled between the common gate / drain terminal of the PMOS transistor PTTL and the TTL-power line TVCCL, and the capacitor CXF is between the TTL-power line TVCCL and the ground line VSS. Are combined. Here, it is also possible to configure a diode-connected PMOS transistor (PTTL) by substituting a diode-connected NMOS transistor. TTL-power lines (TVCCL) can generally be constructed from highly conductive metals.

The NOR gate part 400 includes PMOS transistors MP0 and MP1 and NMOS transistors MN0 and MN1. The source-drain paths of the PMOS transistors MP0 and MP1 are coupled in series between the TTL-power line TVCCL and the inverted data terminal / DATA, and the enable signal / EN is connected to the gate of the PMOS transistor MP0. , A "low" active signal) is applied, and the gate of the PMOS transistor MP1 is coupled to a pad PAD to which data is externally applied. The drain-source paths of the NMOS transistors MN0 and MN1 are coupled in parallel between the inverting data terminal / DATA and the ground potential VSS, and an enable signal / EN is applied to the gate of the NMOS transistor MN0. The data DIN is applied to the gate of the NMOS transistor MN1 from the outside through the data pad PAD.

The inverter unit 300 includes PMOS transistors MPD, MP2, and MPFB, an NMOS transistor MN2, and an inverter IFB. The diode-connected PMOS transistor MPD has a source coupled to the chip power supply line VCC, and a gate and a drain are commonly connected. The source-drain path of the PMOS transistor MP2 is coupled between the common gate / drain terminal and the data terminal DATA of the PMOS transistor MPD, and the gate is coupled to the inverted data terminal / DATA. The drain-source path of the NMOS transistor MN2 is coupled between the data terminal DATA and the ground line VSS, and its gate is coupled to the inverted data terminal / DATA. The source-drain path of the PMOS transistor MPFB is coupled between the chip power line VCC and the data terminal DATA. The input of the inverter IFB is coupled to the data terminal DATA and its output is applied to the gate of the PMOS transistor MPFB.

In the TTL-input buffer circuit having such a configuration, since the gate-source voltage V _GS of the PMOS transistor PTTL included in the power supply voltage drop 200 is always almost near the threshold voltage Vt, the driving force (drivability) It is preferable that the manufacturing process widen the width of the transistor in order to increase the size of the transistor).

For example, if there are N TTL-input buffer circuits in the entire chip, and the current consumption of the NOR gate portion 400 included in the input buffer by one input transition is y [㎃] during x [nsec] In this case, the amount of charge consumed is (N × x × y) [pC]. Even when this amount of charge is discharged, the potential variation of the TTL-power line (TVCCL) should be such that it does not affect the determination of the input data. Therefore, it is preferable to increase the capacitance of the capacitor CXF included in the power supply voltage drop 200 to suppress the potential variation. Here, if the capacitance of the capacitor CXF is C [pF], the maximum power supply voltage variation in one TTL-input change becomes ΔV = (N × x × y) / C [V]. For example, when N = 40, x = 5 [nsec], y = 100 ms, and C = 400 ms, ΔV = 0.05 [V].

In this case, since the amount of current consumed during the transition of the input data of the input buffer becomes a value when the power supply voltage VCC-Vt, it becomes smaller than in the case of the input buffer shown in FIG. In addition, when the static current is an important application, the length of one cycle becomes long, so that charge compensation by the PMOS transistor PTTL and the capacitor CXF is possible.

In addition, when the value of the input data DIN applied from the outside through the data pad PAD is at a "low" level of 0.4 [V], the inversion data terminal / DATA, which is an output of the NOR gate part 400, is Only up to (VCC-Vt). Therefore, when a normal inverter is used to invert the inversion data terminal / DATA, static current consumption occurs in the inverter. Specifically, when a normal CMOS inverter is used to invert the signal of the inversion data terminal / DATA, since the inversion data terminal / DATA is (VCC-Vt), the PMOS transistor included in the CMOS inverter is completely turned on. It does not remain off and turns on weakly. In order to prevent this, in the input buffer circuit according to the present invention, the inverter unit 300 includes a diode-connected PMOS transistor MPD. The PMOS transistor MPD voltage drops the chip power supply line VCC to supply power for driving a CMOS inverter including the PMOS transistor MP2 and the NMOS transistor MN2. Therefore, even if the inversion data terminal / DATA becomes (VCC-Vt), the PMOS transistor MP2 can be kept turned off completely. Thus, static current consumption can be prevented. Here, the diode-connected PMOS transistor MPD may be replaced with a diode-connected NMOS transistor.

On the other hand, when the inversion data terminal / DATA is at the "low" level, the data terminal DATA becomes (VCC-Vt), so that the signal of the data terminal DATA in order to fully raise it to the chip power line VCC. Is inverted through the inverter IFB and applied to the gate of the PMOS transistor MPFB. Here, if the drain of the PMOS transistor MPFB is connected to the inversion data terminal / DATA, a current path is formed from the chip power line VCC to the TTL-power line TVCCL through the PMOS transistors MP0 and MP1. It is not desirable.

On the other hand, unlike in Figure 2, it is also possible to configure the inverter unit 300 as a conventional CMOS inverter. In this case, since the PMOS transistors constituting the CMOS inverter are turned on weakly, there is an advantage that the current consumption can be reduced. Therefore, when the current consumption by the inverter is not greater than the current consumption generated at the NOR gate portion 400 at the 2.2 [V] "high" level of the input data DIN applied through the data pad PAD. Inverter 300 can be configured as a general CMOS inverter. In this case, when the inverter unit 300 is configured as a CMOS inverter, the current consumption of the inverter unit 300 is “low” level when the input data DIN applied through the data pad PAD is 0.4 [V]. Occurs in

In addition, the resistor RXF and the capacitor CXF included in the power supply voltage drop 200 form an RC filter to prevent power supply voltage noise from being transmitted to the TTL-power line TVCCL.

The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the spirit of the present invention.

As described above, the TTL-input buffer of the semiconductor device according to the present invention reduces the standby current and the static current of the semiconductor device operated by the TTL input, thereby reducing power consumption.

Claims (12)

A chip power line to which a chip power potential is supplied; A power supply voltage dropper coupled to the chip power supply line to lower the chip power supply potential by a predetermined voltage to provide a TTL-power supply potential; A TTL-power line coupled to the power supply voltage drop to supply the TTL-power potential; An input data line and an enable signal line to which input data and an enable signal are respectively transferred; A combinational logic unit, driven by a TTL-power supply potential delivered through the TTL-power supply line, coupled to the input data line and the enable signal line to deliver input data when the enable signal is active; An inverter unit for inverting the output of the combinational logic unit And a data input buffer of the semiconductor device. The method of claim 1, The voltage drop includes a diode connected in a forward direction between the chip power line and the TTL-power line. Data input buffer of semiconductor device. The method of claim 2, The diode is a diode-connected PMOS transistor having a source coupled to the chip power line and a drain and gate commonly coupled. Data input buffer of semiconductor device. The method of claim 2, The diode is a diode-connected NMOS transistor Data input buffer of semiconductor device. The method of claim 2, The power supply voltage drop unit, A resistor coupled between the cathode of the diode and the TTL-power line; And further comprising a capacitor coupled between the TTL-power line and ground. Data input buffer of semiconductor device. The method of claim 1, The combinational logic unit is characterized in that the NOR gate portion Data input buffer of semiconductor device. The method of claim 6, The NOR gate portion, An inverting data terminal provided with an output of the NOR gate; Two PMOS transistors having the enable signal and the data applied to respective gates and whose source-drain paths are coupled in series between the TTL-power line and the inverting data terminal; The enable signal and the data are applied to their respective gates and two NMOS transistors whose drain-source paths are coupled in parallel between the inverting data terminal and ground. Characterized in that it comprises Data input buffer of semiconductor device. The method of claim 1, The inverter section includes a CMOS inverter having one PMOS transistor and one NMOS transistor having their source-drain paths coupled in series between the chip power line and ground and the gates coupled to the output of the combinational logic section. Data input buffer of semiconductor device. The method of claim 8, The inverter unit Further comprising a diode forward connected between the chip power line and the source of the PMOS transistor. Data input buffer of semiconductor device. The method of claim 9, The diode is a diode-connected PMOS transistor whose source is coupled to the chip power line and whose gate and drain are coupled to the source of the PMOS transistor. Data input buffer of semiconductor device. The method of claim 9, The diode consists of a diode-connected NMOS transistor Data input buffer of semiconductor device. The method of claim 8, The inverter unit A data terminal provided with an output of the inverter section; A pull-up PMOS transistor having a source coupled to the chip power line and a drain coupled to the data terminal; And a feedback inverter for inverting the signal of the data terminal and applying it to the gate of the pull-up PMOS transistor. Data input buffer of semiconductor device.