KR100380883B1 - Method for making a fine pattern and metal line - Google Patents
Method for making a fine pattern and metal line Download PDFInfo
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- KR100380883B1 KR100380883B1 KR10-2000-0020911A KR20000020911A KR100380883B1 KR 100380883 B1 KR100380883 B1 KR 100380883B1 KR 20000020911 A KR20000020911 A KR 20000020911A KR 100380883 B1 KR100380883 B1 KR 100380883B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/20—Masks or mask blanks for imaging by charged particle beam [CPB] radiation, e.g. by electron beam; Preparation thereof
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/76—Patterning of masks by imaging
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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Abstract
본 발명은 미세 패턴 및 미세 메탈(metal) 라인을 형성하는 방법에 관한 것으로서, 특히 수천 옹스트롬 이하의 미세 패턴 및 미세 메탈 라인을 형성하는 방법에 관한 것이다. 본 발명에서는 반도체 기판위에 제 1물질을 일정 두께로 증착하고, 상기 제 1물질 상부면 일부에 마스킹 물질로 이루어진 마스크를 형성한다. 그리고 에칭방법을 사용하여 마스크가 형성되지 않은 상기 제 1물질을 제거하고, 상기 마스크 하부면의 제 1물질 일단도 에칭하여 마스크 밑으로 일정 깊이의 홈을 형성하며, 상기 제 1물질을 상기 마스크면 상부와 기판 상부면에 재증착하여 상기 홈을 구멍으로 변환시킨다. 이후 상기 마스크와 그 상부면에 재증착된 제1물질을 제거하여 미세 패턴을 형성하고, 형성된 미세 패턴위에 기존의 일반적인 반도체 리소그라피 방법 및 메탈 증착방법을 이용하여 미세 메탈라인을 형성함을 특징으로 한다.The present invention relates to a method for forming fine patterns and fine metal lines, and more particularly to a method for forming fine patterns and fine metal lines of several thousand angstroms or less. In the present invention, a first material is deposited to a predetermined thickness on a semiconductor substrate, and a mask made of a masking material is formed on a portion of the upper surface of the first material. The first material having no mask formed thereon is removed using an etching method, and one end of the first material on the bottom surface of the mask is also etched to form a groove having a predetermined depth under the mask. The grooves are converted into holes by redepositing on the top and the top surface of the substrate. Thereafter, the mask and the first material redeposited on the upper surface thereof are removed to form a fine pattern, and a fine metal line is formed on the formed fine pattern by using a conventional semiconductor lithography method and a metal deposition method. .
Description
본 발명은 미세 패턴 및 메탈 라인 형성 방법에 관한 것으로서, 더욱 상세하게는 수천 옹스트롬(Å) 이하의 미세 패턴 및 메탈 라인 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to methods of forming fine patterns and metal lines, and more particularly, to methods of forming fine patterns and metal lines of thousands of angstroms or less.
최근 보다 많은 정보를 보다 빠르게 처리하기 위해서 반도체 소자의 크기를 가능한 축소하려는 연구가 활발하게 진행중이다. 적당한 플라즈마 가스 상태에서 식각 속도가 다른 두 층의 금속을 이용하는 방법(IEEE Trans.E.D.S. Takarashi 1978 ED-25 pp. 1213-1218)과, 감도가 서로 다른 전자 빔을 감광원으로 사용하는 방법(Electron letter M. Matsumura 1981 vol 12 pp 429-430)등의 방법을 이용하여미소패턴을 형성하여 소자의 크기를 최소화하려는 연구를 그 예로 들 수 있다.In recent years, studies are being actively conducted to reduce the size of a semiconductor device in order to process more information more quickly. Method of using two layers of metals with different etching rates in a suitable plasma gas state (IEEE Trans.EDS Takarashi 1978 ED-25 pp. 1213-1218) and using electron beams of different sensitivity as photosensitive sources (Electron letter For example, M. Matsumura 1981 vol 12 pp 429-430) is a method to minimize the size of the device by forming a micro pattern using a method such as.
한편, FET(field effect transistodr), HBT(hetero-bipolar trasistor), HEMT(high eletron mobility transistor) 등과 같은 고성능 전자 소자들의 성능을 향상시켜 보다 빠르게 동작시키는 연구가 진행 중인데, 상기와 같은 경우 보다 빠르게 동작시키기 위해 수천 옹스트롬(angstrom)이하의 미세 메탈 라인의 형성이 반드시 이루어져야 한다. 그 이유는 전자소자들의 동작속도를 향상시키기 위해서는 전자들이 소자내에서 움직이는 거리를 최소화하여야 하기 때문이다. 그러나, 기존의 기술은 미세라인을 형성하기 위해서 이-빔 리소그라피 공정을 이용하는데 상기이-빔 리소그라피 공정에서 사용하는 장비는 일렉트론 빔을 직접 반도체 기판위에 주사하여 미세 패턴을 얻기 때문에 미세 패턴을 얻고자 하는 모든 곳에 일일이 전자빔을 주사하여야 하는 어려운 공정을 거쳐야 한다. 따라서 대량 생산의 어려움이 있고 상기와 같은 이유로 제조 단가가 매우 높은 단점이 있다.Meanwhile, research is being conducted to improve the performance of high-performance electronic devices such as a field effect transistodr (FET), a hetero-bipolar trasistor (HBT), and a high eletron mobility transistor (HEMT) to operate faster. In order to achieve this, the formation of fine metal lines of several thousand angstroms or less must be achieved. The reason for this is that in order to improve the operating speed of electronic devices, the distance that electrons move within the device must be minimized. However, the existing technology uses an e-beam lithography process to form fine lines, and the equipment used in the e-beam lithography process scans an electron beam directly onto a semiconductor substrate to obtain a fine pattern. It must go through a difficult process of scanning electron beams everywhere. Therefore, there is a difficulty in mass production and the manufacturing cost is very high for the same reason as described above.
따라서 본 발명의 목적은 일반적인 반도체 공정인 UV 리소그라피 공정과 유전체 에칭 방법을 이용하여 수천 옹스트롬 이하의 미세라인을 간단히 형성하고, 기존의 반도체 리소그라피 방법과 메탈 증착 방법을 이용하여 최종적으로 T모양의 메탈 라인을 형성하는 방법을 제공함에 있다.Accordingly, an object of the present invention is to simply form fine lines of several thousand angstroms or less using a UV lithography process and a dielectric etching method, which are general semiconductor processes, and finally form a T-shaped metal line using a conventional semiconductor lithography method and a metal deposition method. In providing a method for forming.
도 1은 반도체 기판위에 SiNx와 SiO2와 같은 유전체를 일정 두께만큼 증착한 것을 도시한 도면.1 is a diagram showing a deposition of a dielectric such as SiNx and SiO2 by a predetermined thickness on a semiconductor substrate.
도 2는 도 1에서 생성된 반도체 샘플 위에 메탈(metal)이나 포토레지스트(Photoresist)을 마스킹 물질로 임의 크기의 마스크를 형성한 것을 도시한 도면.FIG. 2 is a view illustrating a mask having an arbitrary size formed of a metal or photoresist masking material on a semiconductor sample generated in FIG. 1; FIG.
도 3은 유전체를 RIE(Reactive Ion Etching)와 같은 반도체 건식에칭 또는 습식에칭을 이용하여 제1도에서 증착된 유전체중 마스킹되지 않은 부분과 마스크 밑의 일부를 에칭한 것을 도시한 도면.FIG. 3 illustrates etching of the unmasked portion of the dielectric deposited in FIG. 1 and under the mask using semiconductor dry etching or wet etching, such as Reactive Ion Etching (RIE). FIG.
도 4는 이-빔 증착(e-beam evaperation )과 같은 유전체 증착방법을 이용하여 SiO2 또는 SiNx와 같은 유전체를 재증착한 것을 도시한 도면.FIG. 4 shows redeposition of a dielectric such as SiO 2 or SiN x using a dielectric deposition method such as e-beam evaperation.
도 5는 마스킹 물질로 사용된 메탈 또는 포토레지스터 및 마스크 위에 증착된 유전체를 제거한 것을 도시한 도면.5 shows the removal of the dielectric deposited on the metal or photoresist and mask used as the masking material.
도 6은 기존의 일반적인 반도체 리소그라피 공정을 이용하여 최종적으로 메탈라인을 형성한 것을 도시한 도면.FIG. 6 is a diagram illustrating finally forming a metal line using a conventional general semiconductor lithography process. FIG.
도 7은 건식 또는 습식 방법을 이용하여 메탈 아래에 있는 유전체를 제거하여 T자형 메탈 라인을 형성한 도면.FIG. 7 illustrates a T-shaped metal line formed by removing a dielectric under metal using a dry or wet method. FIG.
상기 목적을 달성하기 위한 본 발명은 미세 패턴 및 메탈 라인 형성 방법에 있어서,The present invention for achieving the above object in the fine pattern and metal line forming method,
반도체 기판위에 제 1물질을 일정 두께로 증착하는 제 1 단계와,A first step of depositing a first material on the semiconductor substrate to a predetermined thickness;
상기 제 1물질 상부면 일부에 마스킹 물질로 이루어진 마스크를 형성하는 제 2 단계와,Forming a mask made of a masking material on a portion of an upper surface of the first material;
에칭방법으로 마스크가 형성되지 않은 상기 제 1물질을 제거하고, 상기 마스크 하부면의 제 1물질 일단도 에칭하여 마스크 밑으로 일정 깊이의 홈을 형성하는 제 3 단계와,A third step of removing the first material having no mask formed by an etching method and etching one end of the first material of the lower surface of the mask to form a groove having a predetermined depth under the mask;
상기 제 1물질을 상기 마스크면 상부와 기판 상부면에 재증착하여 상기 홈을 구멍으로 변환시키는 제 4 단계와,A fourth step of redepositing the first material on the mask surface and the upper surface of the substrate to convert the grooves into holes;
상기 마스크와 그 상부면에 재증착된 제1물질을 제거하는 제 5 단계와,A fifth step of removing the first material redeposited on the mask and the upper surface thereof;
상기 홈위에 기존의 반도체 리소그라피 및 메탈 증착법을 이용하여 제 2물질을 증착하는 제 6 단계와,A sixth step of depositing a second material on the groove by using a conventional semiconductor lithography and metal deposition method;
에칭방법을 이용하여 상기 제 2물질 양쪽 및 하부에 위치한 상기 제 1물질을 제거하는 제 7 단계로 이루어짐을 특징으로 한다.And a seventh step of removing the first material on both sides and the bottom of the second material by using an etching method.
이하, 본 발명의 바람직한 실시예를 첨부도면을 참조하여 상세히 설명하기로 한다. 하기 도면을 설명함에 있어서, 본 발명의 공정을 나타낼 때 사용되는 물질중 동일 물질에 대해서는 부호를 동일하게 사용하여 명확성을 추구하였다. 하기 설명 및 첨부 도면에서 각 공정에 따른 특정 도면의 특정 상세들이 본 발명의 보다 전반적인 이해를 제공하기 위해 나타나 있다. 이들 특정 상세들없이 본 발명이 실시될 수 있다는 것은 이 기술분야에서 통상의 지식을 가진 자에게 자명할 것이다. 한편 본 발명을 설명함에 있어 본 발명의 요지를 불명료하게 흐릴 수 있는 공지 기능 및 구성에 대한 상세한 설명은 생략하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, for the same material used in representing the process of the present invention, the same reference numerals are used for the clarity. In the following description and the annexed drawings, specific details of specific drawings in accordance with each process are presented to provide a more general understanding of the invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. Meanwhile, in describing the present invention, detailed descriptions of well-known functions and configurations that may obscure the gist of the present invention will be omitted.
도 1은 반도체 기판위에 SiNx와 SiO2와 같은 유전체를 일정 두께만큼 증착한 단계를 나타내는 도면이고, 도 2는 도 1에서 생성된 반도체 샘플 위에 메탈(metal)이나 포토리지스트(Photoresist)와 같은 마스킹 물질을 이용해서 임의의 크기의 마스크 패턴을 형성하는 단계를 나타내는 도면이며, 도 3은 유전체를 RIE와 같은 반도체 건식에칭 또는 습식에칭을 이용해 마스크 밑으로 에칭하는 단계를 나타내는도면이다.FIG. 1 is a diagram illustrating a step of depositing a dielectric material such as SiNx and SiO 2 on a semiconductor substrate by a predetermined thickness, and FIG. 2 is a masking material such as metal or photoresist on the semiconductor sample generated in FIG. 1. FIG. 3 is a view illustrating a step of forming a mask pattern having an arbitrary size using a semiconductor device, and FIG. 3 is a diagram illustrating a step of etching a dielectric under a mask using semiconductor dry etching or wet etching, such as RIE.
또한, 도 4는 이-빔 증착(e-beam evaperation )과 같은 유전체 증착방법을 이용하여 SiNx 또는 SiO2와 같은 유전체를 재증착하는 단계를 나타내는 도면이고, 도 5는 마스킹 물질로 사용된 메탈 또는 포토레지스터 및 그 위에 증착된 유전체를 제거하는 단계를 나타내는 도면이고, 도 6은 반도체 리소그라피 공정을 이용해 최종적으로 메탈라인을 형성한 단계를 나타내는 도면이며, 도 7은 건식 또는 습식 방법을 이용해 메탈 아래에 있는 유전체를 제거하는 단계를 나타내는 도면이다.FIG. 4 is a diagram illustrating a step of redepositing a dielectric such as SiNx or SiO 2 using a dielectric deposition method such as e-beam evaperation, and FIG. 5 is a metal or photo used as a masking material. FIG. 6 is a diagram illustrating a step of removing a resistor and a dielectric deposited thereon, and FIG. 6 is a diagram illustrating a process of finally forming a metal line using a semiconductor lithography process, and FIG. A diagram showing a step of removing a dielectric.
도 1을 참조하면, 도 1은 반도체 기판(10) 위에와와 같은 유전체(20)를 일정 두께만큼 반도체 기판(10)위에 증착한 후의 모습을 보여 주고 있다. 증착된 유전체(20)의 두께는 최종에 가서 형성되는 미세라인의 폭을 결정하는 변수가 되므로 미리 최종적으로 얻기 원하는 미세라인의 폭에 맞게 적당한 두께의 유전체(20)를 증착하여야 한다. 따라서 최종적으로는 유전체(20) 두께가 미세 라인 폭에 관계되어지므로 수직 방향의 차원(dimension)을 수평 방향의 차원(dimension)으로 전환함에 있어 유전체(20) 두께가 미세라인의 선폭을 제어하는 역할을 한다.Referring to FIG. 1, FIG. 1 illustrates a semiconductor substrate 10. Wow The dielectric 20 is deposited on the semiconductor substrate 10 by a predetermined thickness. Since the thickness of the deposited dielectric 20 becomes a variable for determining the width of the fine lines to be formed at the end, the dielectric 20 having a suitable thickness must be deposited according to the width of the desired fine lines in advance. Therefore, since the thickness of the dielectric 20 is finally related to the fine line width, the thickness of the dielectric 20 controls the line width of the fine line in converting the vertical dimension to the horizontal dimension. Do it.
도 2를 참조하면, 도 1의 단계에서 형성된 샘플에 메탈(metal)이나 포토레지스터(Photoresist)와 같은 마스킹 물질(30)을 상기 증착된 유전체(20) 상부의 일부면에 형성한다. 형성된 메탈(metal)이나 포토레지스트(photoresist)는 도 3의 공정인 에칭 공정에 있어서 마스킹 물질(30)로 사용된다. 마스킹 물질(30)의 특성으로서는 다음 단계인 유전체(20) 에칭 공정에서 마스킹 물질(30)이 에칭되지 않아야하므로 증착된 유전체(20)와 구별되는 선택적 에칭 특성이 있어야 한다.Referring to FIG. 2, a masking material 30 such as metal or photoresist is formed on a portion of the upper surface of the deposited dielectric 20 in the sample formed in the step of FIG. 1. The formed metal or photoresist is used as the masking material 30 in the etching process of FIG. 3. The masking material 30 should have selective etching characteristics that are distinct from the deposited dielectric 20 because the masking material 30 should not be etched in the next step of etching the dielectric 20.
도 3을 참조하면, 도 2에서 형성된 샘플에 리소그라피 작업으로 형성된 마스킹 물질(30)을 마스크로하여 RIE와 같은 반도체 건식에칭 또는 습식에칭을 이용해 마스크(30) 밑으로 에칭하여 홈(40)을 생성하는 방법을 보여주고 있다. 에칭시간과 에칭율에 따라서 마스킹(30) 물질 밑으로 에칭되어 홈(40)을 형성함에 있어 홈(40)의 깊이가 결정되어지고 또한, 이 마스킹 물질(30) 밑으로 에칭되어 파고드는 깊이는 유전체(20)의 두께와도 밀접한 관계가 있다. 따라서 마스킹 물질(30)밑으로 에칭되어 파고드는 깊이는 유전체(20) 두께, 에칭시간,에칭율의 함수관계를 가지고 결정되어지게 된다. 여기서 형성된 마스킹 물질(30) 밑으로 에칭되어 파고드는 홈의 깊이가 최종적으로 미세라인의 폭이 된다.Referring to FIG. 3, the groove 40 is formed by etching under the mask 30 using a semiconductor dry etching or wet etching method such as RIE, using the masking material 30 formed by lithography on the sample formed in FIG. 2 as a mask. It is showing how to do it. Depending on the etching time and the etching rate, the depth of the groove 40 is determined in forming the groove 40 by etching under the masking 30 material, and the depth of etching and digging under the masking material 30 is There is also a close relationship with the thickness of the dielectric 20. Therefore, the depth to be etched under the masking material 30 is determined as a function of dielectric 20 thickness, etching time, and etching rate. The depth of the grooves etched under the masking material 30 formed here is finally the width of the fine line.
도 4를 참조하면, 도 3에서 작업이 끝난 샘플을 이-빔 증착(e-beam evaperation)과 같은 유전체 증착(evaporation)방법을 이용하여또는와 같은 유전체(50)를 증착하는 방법을 보여주고 있다. 유전체 증착 방법의 특성상 제 3도에서 형성된 마스킹 물질(30) 아래로 에칭된 부분인 홈(40)에는 유전체(50)가 증착되지 못하고 도 4에서 볼 수 있듯이 구멍(40)을 형성하게 된다. 이 형성된 구멍(40)은 최종적으로 미세라인 선폭이 된다.Referring to FIG. 4, the sample finished in FIG. 3 may be subjected to dielectric evaporation such as e-beam evaperation. or A method of depositing a dielectric 50 such as is shown. Due to the characteristics of the dielectric deposition method, the grooves 40, which are portions etched under the masking material 30 formed in FIG. 3, are not deposited, and thus the holes 40 are formed as shown in FIG. 4. The formed holes 40 finally have a fine line line width.
도 5는 도 4에서 작업이 이루어진 샘플을 반도체 공정을 이용해 마스킹 물질(30)을 제거한 후의 모습을 보여주고 있다. 최종적으로 부도체인 유전체(20,50) 사이로 수천 옹스트롱이하의 미세라인(40)이 형성되게 된다. 이러한 미세라인(40)의 폭은 앞에서도 언급한 것과 같이 도 1에서 증착된 유전체(20)의 두께와 도 3에서 이어진 유전체(20) 에칭을 조절하여 쉽게 조절이 가능하며 필요에 따라서는 1000 옹스트롱 이하의 극미세 패턴 형성도 쉽게 이루어질 수 있다.FIG. 5 illustrates a state in which the masking material 30 is removed by using a semiconductor process for the sample made in FIG. 4. Finally, the microlines 40 of thousands of angstroms or less are formed between the insulators 20 and 50. As described above, the width of the fine line 40 can be easily adjusted by adjusting the thickness of the dielectric 20 deposited in FIG. 1 and the etching of the dielectric 20 continued from FIG. The formation of ultra fine patterns below strong can be easily achieved.
도 6은 도 5에서 이루어진 미세라인(40)에 반도체 공정을 이용해 메탈(metal)(60)이 증착된 후의 모습을 보여주고 있다. 도 5에서 형성된 미세라인(40)외에는 모두 유전체(20,50)로 이루어져 있기 때문에 전기적 절연 효과를 나타내게 된다. 따라서 형성된 메탈(metal)(60) 라인 중 미세라인(40) 안에 있는 메탈(metal)(60)만이 반도체 기판(10)에 접착되어서 전기적 도통효과를 나타내게 되므로, 실제 반도체 기판(10)위에 형성된 메탈(metal)(60)라인폭은 도 5에서 형성된 미세라인(40)폭이 된다.FIG. 6 shows a state after the metal 60 is deposited on the microline 40 of FIG. 5 using a semiconductor process. Since the fine lines 40 formed in FIG. 5 are all made of dielectrics 20 and 50, electrical insulation effects are exhibited. Therefore, only the metal 60 in the fine line 40 among the formed metal 60 lines is bonded to the semiconductor substrate 10 to exhibit an electrical conduction effect, so that the metal formed on the actual semiconductor substrate 10 is formed. The line width of the metal 60 becomes the width of the fine line 40 formed in FIG. 5.
도 7은 도 6에서 형성된 메탈(metal)(60)라인에 있어서 필요에 따라 메탈(metal)(60) 아래 부분의 유전체(20,50)를 건식 또는 습식 에칭방법을 이용해 제거한 후의 모습을 보여주고 있다. 필요에 따라서는 메탈(metal)(60) 아래 부분의 유전체(20,50) 일부를 남겨둔 채로 유전체(20,50)를 에칭할 수도 있다.FIG. 7 shows the state after removing the dielectrics 20 and 50 of the lower portion of the metal 60 by dry or wet etching, as necessary in the metal 60 line formed in FIG. have. If necessary, the dielectrics 20 and 50 may be etched while leaving portions of the dielectrics 20 and 50 below the metal 60.
상술한 바와 같이 본 발명은 기존의 반도체 공정을 이용하여 1000 옹스트롬 이하의 미세라인도 쉽게 형성시킬 수 있는 효과가 있다.As described above, the present invention has an effect of easily forming fine lines of 1000 angstroms or less using a conventional semiconductor process.
따라서 기존의 미세라인 형성시 드는 추가 비용을 줄일 수 있으며 FET(field effect transistor), HBT(hetero-bipolar transistor), HEMT(high electron mobility transistor)와 같은 전자소자에 응용하여 소자의 성능을 극대화할 수 있기 때문에, 결과적으로는 상기 소자들을 이용하는 시스템의 속도를 향상시킬 수 있게 되는 것이다.Therefore, it is possible to reduce the additional cost of forming a conventional fine line and maximize the performance of the device by applying it to electronic devices such as field effect transistor (FET), hetero-bipolar transistor (HBT), and high electron mobility transistor (HEMT). As a result, it is possible to improve the speed of the system using the elements.
Claims (9)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61206223A (en) * | 1985-03-08 | 1986-09-12 | Fujitsu Ltd | Formation of pattern |
| JPS6464220A (en) * | 1987-09-03 | 1989-03-10 | Sanyo Electric Co | Forming method for resist pattern |
| JPH02103921A (en) * | 1988-06-07 | 1990-04-17 | Mitsubishi Electric Corp | Pattern forming method and pattern forming mask |
| KR0155303B1 (en) * | 1994-12-21 | 1999-02-18 | 양승택 | Phase shift mask of adjusting transparency for forming t-gate |
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2000
- 2000-04-20 KR KR10-2000-0020911A patent/KR100380883B1/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61206223A (en) * | 1985-03-08 | 1986-09-12 | Fujitsu Ltd | Formation of pattern |
| JPS6464220A (en) * | 1987-09-03 | 1989-03-10 | Sanyo Electric Co | Forming method for resist pattern |
| JPH02103921A (en) * | 1988-06-07 | 1990-04-17 | Mitsubishi Electric Corp | Pattern forming method and pattern forming mask |
| KR0155303B1 (en) * | 1994-12-21 | 1999-02-18 | 양승택 | Phase shift mask of adjusting transparency for forming t-gate |
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