KR100382828B1 - Apparatus for transforming asynchronous transfer mode cell head - Google Patents

Abstract

The present invention discloses an Asynchronous Transfer Mode (ATM) cell header converter. This allows error handling in ATM cell header converters to address limitations on the range of available virtual path identifiers (VPIs) / virtual channel identifiers (VCIs) for ATM port controllers (APCs) in ATM switches. An additional part is installed.

Therefore, the ATM cell header converter provides MPHY, VPI, and VCI information of the cell in which an error occurs during ATM cell header conversion to the upper layer, supports both user network interface (UNI) / network node interface (NNI) modes, and utopia. The parity error and SOC (Start Of Cell) errors that may occur during the Level II interface can be counted and provided. Therefore, it is possible to improve the performance of the ATM cell header converter and further increase the reliability of the ATM switch.

Description

ATM cell header converter {APPARATUS FOR TRANSFORMING ASYNCHRONOUS TRANSFER MODE CELL HEAD}

The present invention relates to an Asynchronous Transfer Mode (ATM) cell header converter. More particularly, the present invention relates to an ATM cell header which improves ATM cell conversion performance and improves reliability of an ATM switch by handling errors occurring during ATM cell header conversion. It relates to an inverter.

In general, Asynchronous Transfer Mode (ATM) communication is layered into a physical layer, an ATM layer, an ATM adaptation layer (AAL), and a higher layer, wherein the AAL is AAL1, AAL2, AAL / 4 and It is divided into AAL5. Here, AA1 is a protocol suitable for real time fixed bit rate (CBR) service, AAL2 is a protocol suitable for real time variable bit rate (VBR) service, AAL / 4 is a protocol suitable for error-sensitive data transmission, and AAL5 is suitable for high speed transmission. Protocol.

This AAL is not enacted at the same time, but the protocols such as AAL / 4 and AAL5, which are technically somewhat consensus, are established first, and then the AAL1 and AAL2 protocols are gradually specified due to the increase in demand for real-time services and technological advancements. Is going. The AAL2 protocol was studied in ITU-T SG13 and proposed in Madrid in November 1996 as the I.363.2 standard. According to this proposal, AAL2 is specified to provide efficient transmission in applications of low speed and delay sensitive short packets, and techniques are required to specify this specification.

Meanwhile, as shown in FIG. 1, the general ATM switch 100 includes a physical layer unit 10 performing physical layer termination of an ATM cell, a switch network 20 in which switching of the ATM cell is actually performed, and an ATM. ATM layer unit for terminating the layer and adding routing information to the ATM cell to transfer to the switch network 20, and transferring the ATM cell received from the switch network 20 to the physical layer 10 ( 30).

In addition, an ATM port controller (APC) 31 is used for the ATM layer unit 30, and the APC unit 31 provides a 64K virtual channel. Multiple Physical Layer) information and a Virtual Path Identifier (VPI) / Virtual Channel Identifier (VCI) in a cell header are used as 16-bit addresses. At this time, in order to solve the range constraint of the VPI / VCI, an ATM cell header converter 33 is used in the ATM layer unit 30.

In the ATM switch 100 configured as described above, the physical layer unit 10 terminates the physical layer of the ATM cell received from the power station through an optical transceiver and uses the Utopia Level-II method. The APC unit 31 of the ATM layer unit 30 is transferred. At this time, the APC unit 31 serves as a master of the utopia level II. The APC unit 31 uses the VPI / VCI and the MPHY in the header of the ATM cell to make a 16-bit address to perform a 64K VC connection, wherein the total bits of the VPI, VCI, and MPHY are maximum. It should not exceed 16 bits, which limits the usage range of the VPI / VCI.

To solve this problem, an ATM cell header converter 33 is used for the ATM layer unit 30. That is, the cell transferred from the physical layer unit 10 is converted to the VPI / VCI of the cell by the ATM cell header conversion unit 33 of the ATM layer unit 30 is transferred to the APC unit 31. The APC unit 31 sends a cell to which connection information is added to the switch network 20, receives the switched cell from the switching network 20, and transmits the cell to the physical layer unit 10 in a utopian level II manner. Send. At this time, up to 28 bits can be used without any restriction on the transmitted range of the VPI / VCI, and the APC unit 31 also serves as a master of Utopia Level II. Finally, the physical layer unit 10 transmits the cell to the power station through the optical transceiver.

However, the conventional ATM cell header converter converts the header of an ATM cell by using a content addressable memory (CAM), wherein the VPI due to a bit error or a connection error by call processing software during cell transmission. If an error occurs during header conversion of an ATM cell due to an error of / VCI, no special action is taken. In this case, the ATM cell may be subject to discard in the APC unit, but it is not possible to determine whether the ATM cell is subject to discard due to a header conversion error of the ATM cell header converter. This inevitably affects the reliability of the entire ATM switch.

Accordingly, an object of the present invention is to provide an ATM cell header converting apparatus which prevents a deterioration in reliability of ATM cell header conversion even if an error occurs in the header conversion of an ATM cell.

Another object of the present invention is to provide an ATM cell header converter for improving the reliability of an ATM switch.

1 is a block diagram showing an ATM switch to which a general Asynchronous Transfer Mode (ATM) header converter is applied.

Figure 2 is a block diagram showing an ATM switch to which the ATM header converter according to the present invention is applied.

3 is a detailed block diagram illustrating an ATM cell header converter of FIG. 2;

4 is a format diagram of MQ data applied to an ATM header conversion device according to the present invention;

5 is a block diagram showing a header before conversion applied to an ATM header conversion device according to the present invention;

6 is a diagram illustrating a converted header when a VP connection is applied to an ATM header converting apparatus according to the present invention.

7 is a diagram illustrating a converted header when a VC connection is applied to an ATM header converting apparatus according to the present invention.

ATM cell header converter for achieving this purpose,

A utopian master receiver for utopian level II interface with the physical layer unit to receive an asynchronous transmission mode (ATM) cell from the physical layer unit;

A content addressable memory interface configured to interface with a content addressable memory configured to perform header conversion of an ATM cell delivered from the utopia master receiver; And an error processor configured to provide predetermined information of an ATM cell in which a header conversion error is generated, which is transmitted through the content addressable memory interface unit.

Preferably, the error processing unit may count and provide a parity error and a SOC (Start Of Cell) error generated by the Utopia master receiver.

Preferably, the error processing unit may provide information regarding whether the ATM cell is in a mode of a user network interface / network node interface controlled by the upper layer to the content addressable memory interface unit.

Preferably, when the header processing error occurs in the content addressable memory unit, the error processing unit may include a multiple physical layer, a virtual path identifier (VPI) and a virtual channel identifier (VCI) before the header conversion of the cell. Information can be provided higher.

The ATM cell header converting apparatus may further include a first-in first-out memory unit configured to store data of the header-converted ATM cell transferred from the content addressable memory interface unit;

A utopia slave receiver configured to receive a Utopia Level II interface with the ATM port controller for receiving data from the first-in, first-out memory unit and transmitting the data to the ATM port controller; And a central processing unit interface unit for interfacing with the central processing unit.

Hereinafter, an ATM cell header converter according to the present invention will be described in detail with reference to the accompanying drawings. The same code | symbol is attached | subjected to the part of the same structure and the same action as the conventional part.

2 is a block diagram illustrating an ATM switch to which an ATM cell header converter according to the present invention is applied, and FIG. 3 is a detailed block diagram illustrating an ATM cell header converter of FIG. 2.

Referring to FIG. 2, the ATM switch 200 of the present invention is largely composed of a physical layer unit 10, a switch network 20, and an ATM layer unit 40. In addition, the ATM layer unit 40 includes a content addressable memory (CAM) 50, an ATM cell header converter 60, and an APC unit 70. In addition, the ATM cell header converter 60 includes a Utopia Level-II Master Receiver (UMR) 61 and a Content Addressable Memory Interface (CAM IF) 62. , First In First Out Memory (FIFO) 63, Utopia Level-II Slaver Receiver (USR) 64, Error Processing Unit 65, Central Processing It consists of a Central Processing Unit Interface (CPU IF) 66.

Here, the utopian level II master receiver (UMR) 61 interfaces the ATM cell header converter 60 with the physical layer unit 10 to the utopian level II interface. The Utopia Level II Slave Receiver (USR) 64 interfaces the ATM cell header converter 60 with the APC 70 with a Utopia Level II interface. The FIFO section 63 is disposed between the UMR 61 and the USR 64. The CAM 50 and the CAM IF unit 62 are responsible for the actual cell header conversion. The error processor 65 provides VPI, VCI, and MPHY information of a cell in which the header conversion is not properly performed in the CAM unit 50 through the CPU IF unit 66, and the UMR unit 61. Parity Error (SO) and Start Of Cell (SOC) errors that occur in the PC are counted and provided to the upper level through the CPU IF unit 66, and the CAM IF unit 62 transmits an ATM cell to a user network interface (User). The function width of the ATM cell header conversion unit 60 is expanded by providing information on whether a network interface (UN) or a network node interface (NNI).

In addition, the CAM IF unit 62 includes a header extracting unit (Head-Ext) 621, a CAM-Con unit 622 and a Head-App unit 623, as shown in FIG. In addition, the head-Ext unit 621 includes an internal FIFO unit 624 that can store the remaining pay load other than the header extracted. The FIFO unit 624 receives 16-bit cell data and write enable (WE) signals that are written from the UMR unit 61 to the FIFO unit 63, and converts only the headers. It is responsible for the function of sending the data of the bit to the FIFO section 63 together with the WE signal.

The error processing unit 65, when a match successful error (MS-ERR) occurs in the CAM unit 50, from the Head-App unit 623 in the form of MQ (31: 0) of FIG. It receives the MS-ERR pulse signal and provides information of the MPHY, VPI, and VCI of the error cell through the CPU IF unit 66.

The operation of the ATM cell header converter configured as described above will be described in detail. First, in order to store a cell corresponding to each physical layer (PHY) in the UMR unit 61 to the FIFO unit 63, The data is sent to the Head-Ext unit 621 of the header converter 62. Here, the WE signal is allocated to each MPHY to support four MPHYs.

Subsequently, the Head-Ext unit 621 generates an MPHY from the WE signal, and extracts VPI, VCI, GFC, PTI and CLP from the 16-bit cell data. At this time, the UNI / NNI information is received from the error processor 65 to extract the 4-bit GFC and the 8-bit VPI in the UNI mode, and extract the 12-bit VPI in the NNI mode. The extracted MPHY, VPI, and VCI are converted into the MQ data format of FIG. 4 and transferred to the CAM-Con unit 622 together with a Start Match (SM) signal, and the MPHY, VPI, VCI, and GFC are also transmitted. , PTI and CLP are delivered to the head-app unit 623. At this time, an internal FIFO 624 is used to store the payload other than the header.

Thereafter, the CAM-Con unit 622 generates the LL, LHBSM, G, and KMODE requested by the CAM unit 50 from the SM signal and the MQ data transmitted from the Head-Ext unit 621 and the MQ data. The CAM unit 50 is transferred together, and the MQ data including the VPI and VCI converted by the CAM unit 50 and the MC, MS, and VPC are transferred to the Head-App unit 623.

Thereafter, the Head-App unit 623 uses the VPC information transmitted from the COM-Con unit 622 for the VP connection and otherwise for the VCI of the header-converted MQ data and the Head- Select one of the VCI of the header before the header transferred from the Ext unit 621, and the VPI converted by the CAM unit 50 together with the GFC, PTI and CLP delivered from the Head-Ext unit 621 After generating a new header with the remaining payload taken out from the internal FIFO unit 624, 16-bit data is created and transmitted to the FIFO unit 63 together with the WE signal. The header before the conversion is configured as shown in FIG. In addition, the header converted in the VP connection is configured as shown in FIG. 6, and the header converted in the VC connection is configured as shown in FIG. 7. Here, the GFC / VPI 4 bits are used as GFC in UNI mode and VPI in NNI mode, so they are selected and converted according to each mode.

Meanwhile, the WE signal transmitted from the UMR unit 61 is used to calculate a delay for header conversion in the CAM unit 50. When the MS-ERR is generated, the MPHY, VPI and the VHY transmitted from the Head-Ext unit 621 before the WE signal is disabled and converted by the CAM unit 50 together with the MS-ERR pulse signal. MQ data is generated by the VCI and transferred to the error processing unit 65.

Then, the error processing unit 65 counts the parity error (PRTY-ERR) and the SOC error (SOC-ERR) generated during the Utopia Level II interface provided by the UMR unit 61, and the CPU IF unit 66. ) To the upper level. In addition, UNI / NNI mode information controlled by the upper layer is provided to the Head-Ext unit 621 and the Head-App unit 623, and when a header conversion error occurs in the CAM unit 50, The Head-App unit 623 receives the MS-ERR pulse signal and the MQ-mismatch signal, and provides the CPU IF unit 66 with MPHY, VPI, and VCI before header conversion of the cell. Therefore, the performance of the ATM cell header converter of the present invention is improved.

As described above, the ATM cell header converting apparatus according to the present invention adds an error processing unit to the ATM cell header converting apparatus which solves the limitation of the range of available VPI / VCI used by the APC unit used in the ATM switch. MPHY, VPI, and VCI information of the cell where an error occurred during header conversion are provided at the top, and both UNI / NNI modes are supported, and parity errors and SOC errors that can occur at the Utopia Level II interface can be counted and provided by the error processing unit. have. Therefore, the present invention can improve the performance of the ATM cell header converter and further increase the reliability of the ATM switch.

On the other hand, the present invention is not limited to the contents described in the drawings and the upper description, and various forms of modification, modification, and addition are possible without departing from the spirit of the present invention to those skilled in the art. It is self-evident.

Claims (5)

A utopian master receiver for utopian level II interface with the physical layer unit to receive an asynchronous transmission mode (ATM) cell from the physical layer unit; A content addressable memory interface configured to interface with a content addressable memory configured to perform header conversion of an ATM cell delivered from the utopia master receiver; And an error processing unit which provides predetermined information of an ATM cell in which a header conversion error has occurred, transferred through the content addressable memory interface unit to a higher level. The apparatus of claim 1, wherein the error processing unit counts and provides a parity error and a start of cell (SOC) error generated by the utopian master receiver to a higher level. The AT cell of claim 1, wherein the error processing unit provides information about whether the ATM cell is in a mode of a user network interface / network node interface controlled by the upper layer, to the content addressable memory interface unit. Header Inverter. The method of claim 1, wherein when the header processing error occurs in the content addressable memory unit, the multiple physical layer, the virtual path identifier (VPI), and the virtual channel identifier before header conversion of the cell. The AT cell header converter, characterized by providing (VCI) information higher. The method of claim 1, A first-in, first-out memory unit for storing data of the header-converted ATM cell transferred from the content addressable memory interface unit; A utopia slave receiver configured to receive a Utopia Level II interface with the ATM port controller for receiving data from the first-in, first-out memory unit and transmitting the data to the ATM port controller; And a central processing unit interface unit for interfacing with the central processing unit.