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KR100399907B1 - Method for forming oxide layer of semiconductor device - Google Patents

Method for forming oxide layer of semiconductor device Download PDF

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KR100399907B1
KR100399907B1 KR1019960075209A KR19960075209A KR100399907B1 KR 100399907 B1 KR100399907 B1 KR 100399907B1 KR 1019960075209 A KR1019960075209 A KR 1019960075209A KR 19960075209 A KR19960075209 A KR 19960075209A KR 100399907 B1 KR100399907 B1 KR 100399907B1
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oxidation
temperature
minutes
semiconductor device
wafer
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KR19980055972A (en
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권오정
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE: A method for forming an oxide layer of a semiconductor device is provided to effectively restrain defects by controlling the flow rate of Cl gas for gettering of metallic impurity. CONSTITUTION: After loading a wafer to a reaction furnace(21), ramp-up processing is performed(22). Temperature stabilization processing is performed(23) and pre-oxidation processing is carried out(24). DCE(C2H2Cl2) oxidation processing is performed to add Cl gas for 5 minutes(25). Dry etching and N2 purging are performed for 33 minutes(26,27). Ramp-down processing is carried out(28) and the wafer is unloaded to the reaction furnace(29).

Description

반도체 소자의 산화막 형성 방법Oxide film formation method of semiconductor device

본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 건식 산화 공정시 금속 불순물(metallic impurity)의 게터링(getting)을 위하여 흘려주는 Cl의 양을 조절하여 디바이스의 효율을 향상시키는 반도체 소자의 산화막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming an oxide film of a semiconductor device, by improving the efficiency of a device by controlling the amount of Cl flowing for gettering of metallic impurity in a dry oxidation process. It is about.

반도체의 집적도가 증가함에 따라 디바이스의 수율 향상을 위해서는 디펙트(defect)가 매우 적은 산화 공정을 필요로 한다. 현재의 건식 산화 공정은 금속 불순물(metallic impurity)를 제거하기 위하여 Cl을 첨가하는 공정을 사용하고 있다. Cl은 산화 공정중 금속 불순물을 게터링하는 효과가 있는 것으로 알려져 있다. 그러나 실리콘 기판의 순도가 점점 좋아짐에 따라 일반적으로 사용하던 Cl의 양은 금속 불순물을 게터링할 수 있는 양보다 훨씬 많은 양이 첨가되고 있는 실정이다. 이에 따라 초과 Cl은 디펙트원으로 작용하게 되어 디바이스의 효율을 저하시키는 요인이 되고 있다.As the degree of integration of semiconductors increases, an improvement in device yield requires an oxidation process with very low defects. Current dry oxidation processes use a process of adding Cl to remove metallic impurity. Cl is known to have an effect of gettering metal impurities during the oxidation process. However, as the purity of the silicon substrate is improved, the amount of Cl generally used is much higher than the amount that can getter metal impurities. As a result, the excess Cl acts as a defect source and causes a decrease in the efficiency of the device.

따라서, 본 발명은 적절한 Cl을 첨가함으로써 산화막 형성시 발생되는 디펙트를 효과적으로 제거하여 디바이스의 효율을 향상시키는데 그 목적이 있다.Therefore, an object of the present invention is to improve the efficiency of the device by effectively removing the defects generated when the oxide film is formed by adding appropriate Cl.

상술한 목적을 달성하기 위한 본 발명은 반응로에 웨이퍼를 로딩시킨 후 산화 온도까지 상승시키는 단계와, 상기 산화 온도에서 온도 안정화 단계를 거쳐 준산화 공정을 수행하는 단계와, 상기 준산화 공정을 수행한 후 Cl을 첨가시키는 DCE산화 공정을 5분 가량 수행하는 단계와, 상기 DCE 산화 공정을 5분간 수행한 후 33분 가량의 건식 산화 공정, O2퍼지 및 N2퍼지 공정을 수행하는 단계와, 상기 N2퍼지 공정을 수행한 후 온도를 하강시키고 보트를 언로딩하여 웨이퍼를 반응로에서 꺼내는 단계로 이루어진 것을 특징으로 한다.The present invention for achieving the above object is the step of loading the wafer in the reactor and then raising to the oxidation temperature, performing a semi-oxidation process through the temperature stabilization step at the oxidation temperature, and performing the semi-oxidation process Performing a DCE oxidation process for 5 minutes after adding Cl, performing a DCE oxidation process for 5 minutes, and performing a dry oxidation process, an O 2 purge and an N 2 purge process for 33 minutes, and After performing the N 2 purge process, the temperature is lowered and unloading the boat, characterized in that consisting of the step of taking out the wafer from the reactor.

도 1은 종래의 건식 산화 방법에 의한 산화막 형성 방법을 설명하기 위해 도시한 반응로 산화 레시피도.1 is a reactor oxidation recipe diagram shown for explaining an oxide film forming method by a conventional dry oxidation method.

도 2는 종래의 방법에 의해 산화막 형성 공정을 진행한 경우의 디펙트 발생 경향을 도시한 그래프.2 is a graph showing a defect generation tendency when an oxide film forming step is performed by a conventional method.

도 3은 본 발명에 따른 건식 산화 공정에 의한 산화막 형성 방법을 설명하기 위해 도시한 반응로 산화 레시피도.Figure 3 is a reactor oxidation recipe diagram shown to explain the oxide film formation method by a dry oxidation process according to the present invention.

도 4는 본 발명에 따른 공정을 적용하였을 때의 디펙트 발생 경향을 도시한 그래프.4 is a graph showing the defect generation tendency when the process according to the present invention is applied.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

11, 12 : 로딩 단계 12, 22 : 램프 업 단계11, 12: loading step 12, 22: ramp up step

13, 23 : 안정화 단계 14, 24 : 전산화 단계13, 23: stabilization step 14, 24: computerization step

15, 25 : DCE 산화 단계 16, 26 : 건식 산화 단계15, 25: DCE oxidation stage 16, 26: dry oxidation stage

17, 27 : N2퍼지 단계 18, 28 : 램프 다운 단계17, 27: N 2 purge step 18, 28: ramp down step

19, 29 : 언로딩 단계19, 29: Unloading stage

본 발명에서는 건식 산화 공정시 산화 공정의 초기 단계에서 약간의 Cl을 사용함으로서 금속 불순물을 제거하면서 과도한 Cl 첨가에 의한 디펙트 유발을 방지하여 디펙트가 적은 건식 산화 공정을 개발한다.In the present invention, by using a small amount of Cl in the initial stage of the oxidation process in the dry oxidation process to prevent the defect caused by excessive addition of Cl while removing metal impurities, a dry oxidation process having less defects is developed.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 1은 종래의 건식 산화 방법에 의한 산화막 형성 방법을 설명하기 위해 도시한 반응로 산화 레시피도이다. 800℃의 일반적인 반응로에 웨이퍼를 로딩시킨 후 진공 퍼지 공정을 거쳐 반응로 내부를 오염으로부티 방지한다(11). 그리고 약 5℃/min의 온도 기울기로 산화 온도(900℃)까지 상승시킨다(12). 산화 온도가 되면 약 5분 정도의 온도 안정화 시간을 거치고(13) O2를 약 5분간 흘려주어 준산화(pre-oxidation) 공정을 수행한다(14). N2캐리어 가스(carrier gas)를 이용하여 Cl을 첨가시키는 DCE 산화(oxidation) 공정을 29분 정도 수행한다(15). Cl을 첨가하는 방법으로 DCE(C2H2Cl2)를 사용하는데, 일반적으로 상온 대기압에서 DCE는 액체 상태를 유지하게 된다. 이 DCE를 밀폐된 용기에 가두면 DCE의 증기압에 의해 일부는 기화되고 또 일부는 다시 액화되어 일정한 평형 상태를 유지하게 된다. 이때 캐리어 가스로 N2를 흘려주면 DCE 가스도 같이 흘러가게 된다. 이 DCE 가스가 고온의 반응로로 들어가면 Cl로 분해되어 산화 공정에 참가하게 된다. 이때 Cl은 금속 불순물을 제거하는 게터링 작용을 하게 되며, 산화 속도도 증가시켜 준다. 이후에 5분 가량의 건식 산화 공정(16)과 O2퍼지(purge) 및 N2퍼지(purge) 공정(17)을 거친후 3℃/min의 온도 기울기로 800℃의 언로딩(unloading) 온도로 낮춘 후 보트(boat)를 언로딩하여 웨이퍼를 꺼낸다(19).1 is a reactor oxidation recipe diagram shown for explaining an oxide film forming method by a conventional dry oxidation method. The wafer is loaded into a general reactor at 800 ° C. and then vacuum-purged to prevent the inside of the reactor from contamination. Then, the temperature is raised to an oxidation temperature (900 ° C.) at a temperature gradient of about 5 ° C./min (12). When the oxidation temperature reaches about 5 minutes of temperature stabilization time (13) and O 2 flow for about 5 minutes to perform a pre-oxidation process (14). DCE oxidation process of adding Cl using N 2 carrier gas is performed for about 29 minutes (15). As a method of adding Cl, DCE (C 2 H 2 Cl 2 ) is used. Generally, at room temperature and atmospheric pressure, DCE maintains a liquid state. When this DCE is confined in a closed container, the vapor pressure of the DCE causes some to vaporize and some to liquefy again to maintain a constant equilibrium. At this time, when N 2 is flowed to the carrier gas, DCE gas flows together. When the DCE gas enters the high temperature reactor, it is decomposed into Cl and participates in the oxidation process. At this time, Cl acts as a gettering action to remove metal impurities and increases the oxidation rate. After 5 minutes of dry oxidation (16), O 2 purge and N 2 purge process (17), the unloading temperature of 800 ℃ at a temperature gradient of 3 ℃ / min The wafer is lowered and the wafer is unloaded (19).

도 2는 기존의 방법에 의해 산화막 형성 공정을 진행한 경우의 디펙트 발생양상을 도시한 그래프이다. 0.16㎛ 이상의 레이저 카운터(laser counter) 장비를 이용하여 측정한 것이다. 전반적으로 50개 이상의 높은 디펙트 경향을 나타내고 있어 0.25㎛ 이상의 설계 규칙(design rule)을 갖는 반도체 소자의 개발에 커다란 영향을 주고 있음을 나타낸다.2 is a graph showing a defect generation pattern when the oxide film forming step is performed by a conventional method. Measured using a laser counter device of 0.16㎛ or more. Overall, there is a trend of more than 50 high defects, indicating a great influence on the development of semiconductor devices having design rules of 0.25 mu m or more.

도 3은 본 발명에 따른 건식 산화 공정에 의한 산화막 형성 방법을 설명하기 위해 도시한 반응로 산화 레시피도로서, 도 1과 유사하나 DCE 산화 시간을 약 5분으로 줄이고 건식 산화 시간을 33분 정도로 늘려 진행하는 것이 특징이다. 일반적으로 산화 공정 중에 흘려주는 DCE는 Cl로 분해되어 실리콘의 산화 속도를 증가시키고, Si 기판의 금속 불순물을 게터링하는 작용을 한다. 그러나 너무 많은 양의 Cl은 오히려 디펙트원으로 작용하게 된다. 반도체 소자의 제조에 사용되는 Si 기판, 즉 웨이퍼의 제조 기술은 점점 발전하여 집적 소자가 형성되는 웨이퍼 표면의 금속 불순물은 점점 감소되는 추세이다. 그러므로 기존의 공정을 그대로 적용하면과거의 금속 불순물이 많을 때는 적절한 Cl 양이라도 금속 불순물이 적은 최근의 발달된 기술로 제조된 웨이퍼에서는 과도한 양이 되게 된다. 이 잉여의 Cl은 디펙트로 관측되며, 반도체 소자의 수율을 저하시키는 원인이 된다.3 is a reactor oxidation recipe diagram illustrating a method of forming an oxide film by a dry oxidation process according to the present invention. Similar to FIG. 1, the DCE oxidation time is reduced to about 5 minutes and the dry oxidation time is increased to about 33 minutes. It is characterized by progress. In general, the DCE flowing during the oxidation process is decomposed into Cl to increase the oxidation rate of silicon and to getter the metal impurities of the Si substrate. But too much Cl will act as a defect source. The manufacturing technology of Si substrates, that is, wafers used in the manufacture of semiconductor devices has been gradually developed, and metal impurities on the surface of the wafer on which integrated devices are formed are gradually decreasing. Therefore, if the existing process is applied as it is, in the case of a large amount of metal impurities in the past, even an appropriate amount of Cl becomes an excessive amount in a wafer manufactured by the latest developed technology having less metal impurities. This excess Cl is observed as a defect and causes a decrease in the yield of the semiconductor element.

도 4는 본 발명에 따른 공정을 적용하였을 때의 디펙트 발생 경향을 도시한 그래프이다. 0.16㎛ 이상의 디펙트가 21개 이하로 양호한 결과를 보이고 있으며 도 2에 비해서도 상당히 적은 디펙트의 개수를 나타내는 것을 알 수 있다.4 is a graph showing a defect generation tendency when the process according to the present invention is applied. It can be seen that defects of 0.16 µm or more showed good results of 21 or less, and the number of defects was considerably smaller than that of FIG. 2.

이와 같은 적당한 양의 DCE를 사용하는 건식 산화 방법은 습식 공정에도 적용하여 디펙트 레벨을 낮출 수 있다.This dry oxidation method using an appropriate amount of DCE can also be applied to wet processes to lower the defect level.

상술한 바와 같이 본 발명에 의하면 Cl의 양을 적절히 조절하여 Cl에 의한 디펙트 유발을 억제함으로써 0.25㎛ 이하의 설계 규칙을 갖는 256M DRAM 이상의 고집적도 반도체 소자에서의 수율을 향상시킬 수 있으며, 또한 200mm의 웨이퍼를 기준으로하여 웨이퍼당 25개 이상의 디펙트 조절이 가능한 효과가 있다.As described above, according to the present invention, by controlling the amount of Cl appropriately to suppress the occurrence of defects by Cl, the yield in high-integration semiconductor devices of 256M DRAM or more having a design rule of 0.25 µm or less can be improved, and 200 mm can also be improved. 25 defects per wafer can be adjusted based on the wafer.

Claims (5)

반응로에 웨이퍼를 로딩시킨 후 산화 온도까지 상승시키는 단계와,Loading the wafer into the reactor and raising it to an oxidation temperature; 상기 산화 온도에서 온도 안정화 단계를 거쳐 준산화 공정을 수행하는 단계와,Performing a semi-oxidation process through a temperature stabilization step at the oxidation temperature; 상기 준산화 공정을 수행한 후 Cl을 첨가시키는 DCE 산화 공정을 5분 가량 수행하는 단계와,Performing the DCE oxidation process for adding about 5 minutes to add Cl after the semi-oxidation process; 상기 DCE 산화 공정을 5분간 수행한 후 33분 가량의 건식 산화 공정, O2퍼지 및 N2퍼지 공정을 수행하는 단계와,Performing the DCE oxidation process for 5 minutes and performing a dry oxidation process, an O 2 purge, and an N 2 purge process for about 33 minutes; 상기 N2퍼지 공정을 수행한 후 온도를 하강시키고 보트를 언로딩하여 웨이퍼를 반응로에서 꺼내는 단계로 이루어진 것을 특징으로 하는 반도체 소자의 산화막 형성 방법.After performing the N 2 purge process, the temperature is lowered and the boat is unloaded by removing the wafer from the reactor by the step of unloading the boat, characterized in that consisting of. 제 1 항에 있어서, 상기 산화 온도는 750 내지 1000℃인 것을 특징으로 하는 반도체 소자의 산화막 형성 방법.The method of claim 1, wherein the oxidation temperature is 750 to 1000 ℃. 제 1 항에 있어서, 상기 산화 온도까지의 온도 상승은 2 내지 10℃/분의 기울기로 상승시키는 것을 특징으로 하는 반도체 소자의 산화막 형성 방법.The method of forming an oxide film of a semiconductor device according to claim 1, wherein the temperature rise up to the oxidation temperature is increased by a slope of 2 to 10 deg. 제 1 항에 있어서, 상기 Cl의 양은 산소의 1 내지 5%인 것을 특징으로 하는 반도체 소자의 산화막 형성 방법.The method of forming an oxide film of a semiconductor device according to claim 1, wherein the amount of Cl is 1 to 5% of oxygen. 제 1 항에 있어서, 상기 산화 분위기는 O2및 O2+H2O중 어느 하나인 것을 특징으로 하는 반도체 소자의 산화막 형성 방법.The method of forming an oxide film of a semiconductor device according to claim 1, wherein the oxidizing atmosphere is any one of O 2 and O 2 + H 2 O.
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