KR100399973B1 - A delay monitor in register controlled delay locked loop and method for controlling delay line of the same - Google Patents

Abstract

TECHNICAL FIELD The present invention relates to semiconductor circuit technology, and more particularly, to a register control delay locked loop (DLL), and more particularly, to a delay monitor of a register control DLL. An object of the present invention is to provide a delay monitor of a register control delay lock loop and a delay line control method of a register control delay lock loop that can improve a phenomenon in which a clock passing through a delay line is disabled low. In the present invention, in implementing the delay monitor of the register control delay lock loop, only one clock path is generated by the output of the shift register. That is, the conventional 2-path turn-on method was changed to the 1-path turn-on method. In this case, compared to the conventional DLL, the pulse width of the clock passing through the delay line is reduced by the propagation delay (tPD) of the unit delay device. As a result, the DLL clock is disabled low through the delay line. Can be.

Description

A delay monitor in register controlled delay locked loop and method for controlling delay line of the same}

TECHNICAL FIELD The present invention relates to semiconductor circuit technology, and more particularly, to a register control delay locked loop (DLL), and more particularly, to a delay monitor of a register control DLL.

In general, a clock is used as a reference for timing operation in a system or a circuit, and may be used to ensure faster operation without an error. When a clock input from the outside is used internally, a time delay (clock skew) caused by an internal circuit occurs, and a DLL is used to compensate for this time delay so that the internal clock has the same phase as the external clock. have.

On the other hand, DLL has the advantage of being less affected by noise than PLL, which is widely used in synchronous semiconductor memory including DDR Double Data Rate Synchronous DRAM (SDRAM). Register controlled DLLs are the most commonly used.

1 is a block diagram of a register control DLL used in a general DDR SDRAM.

Referring to FIG. 1, a register control DLL used for a general DDR SDRAM includes a general register control DLL having an internal clock (fall_clk) synchronized to a falling edge of an external clock (clk) by using an inverting external clock (/ clk) as an input. A first clock buffer 11 for generating, a second clock buffer 12 for generating an internal clock rise_clk synchronized with the rising edge of the external clock clk using the external clock clk as an input; A clock divider 13 for outputting the divided clocks dly_in and ref by dividing the internal clock rise_clk synchronized to the rising edge of the external clock clk by 1 / n (where n is a natural number and typically n = 8). ), A first delay line 14 having an internal clock fall_clk synchronized to the falling edge of the external clock clk, and an internal clock rise_clk synchronized to the rising edge of the external clock clk. A third delay line 15 to be input and a third delay inputting the divided clock dly_in Drives the line 16, the shift register 17 for determining the delay amount of the first and second third delay lines 14, 15, and 16, and the output ifclk of the first delay line 14; The first DLL driver 20 for generating the DLL clock fclk_dll and the second DLL driver 21 for generating the DLL clock rclk_dll by driving the output irclk of the second delay line 15. And a delay model 22 configured to receive the output of the third delay line 16 as a feedback_dly and have the same delay condition as that of the actual clock path, and a feedback of the delay model 22. ) And a shift control for controlling the shift direction of the shift register 17 in response to a control signal ctrl output from the phase comparator 19 and a phase comparator 19 for comparing the phase of the divided clock ref. The shift controller 18 outputs the delay lock signal dll_lockb indicating that the signals SR, SL and delay lock have been made. Equipped.

The delay model 22 here includes a dummy clock buffer, a dummy output buffer and a dummy load, also called a replica circuit. The first, second, and third delay lines 14, 15, and 16, the shift register 17, and the shift controller 18 are collectively referred to as a delay monitor 10.

2 is a circuit diagram of a delay monitor according to the related art, and for convenience the shift controller 18 is not shown.

Referring to FIG. 2, the shift register 17 receives the shift control signals SR and SL and the reset signal reset, and has a plurality of registers reg1 having a positive output terminal Q and a negative output terminal Qb, respectively. -Reg8) is provided.

On the other hand, for the output of the shift register 17, a number of negative logic gates corresponding to each of the registers reg1 to reg8 are used, where n (where n is a natural number) is the negative logic gate of the n-1th register. The output Qb and the positive output Q of the n + 1th register are input.

In addition, the first delay line 14 is a negative logic gate which inputs the output of the internal clock fall_clK and the negative logic gate synchronized with the falling edge of the external clock clk, and the output and transfer of the negative logic gate. It consists of the delay chain which makes a unit unit the delay unit D which takes the output of a unit delay element as an input unit. The configuration of the second and third delay lines 15 and 16 is also the same as that of the first delay line 14 except for the input clock.

In the conventional delay monitor 10 configured as described above, there are two clock paths entering the delay line. That is, when the shift register 17 operates in response to the shift control signals SR and SL, and its output value changes in a specific register, two clock paths are turned on.

FIG. 3 illustrates a two-path turn-on method according to the related art, and shows a state in which a signal is changed in the sixth register reg6. In this case, the negative logic gate which takes the negative output Qb of the fourth register reg4 and the positive output Q of the sixth register reg6, the negative output Qb of the fifth register reg5, and The output of the negative logic gate, which takes the positive output Q of the seventh register reg7, becomes logic high, thereby turning on the clock path connected to the negative logic gate (see Fig. 2).

Such a conventional two-path turn-on method is effective to improve the glitch, but often causes a problem that the clock passing through the delay line is disabled low.

4 is a diagram illustrating a unit delay device constituting a delay line. The unit delay device includes a negative logic gate that receives an input signal IN and a supply power supply (QVDD, quiet Vdd), and an output thereof. It consists of an inverter which inverts. The unit delay element located at the first stage of the delay line receives a power supply as shown in the drawing, but the subsequent unit delay elements receive the output of the previous unit delay element.

FIG. 5 is a timing diagram of nodes A, B, and C of FIG. 2. When the conventional two-path turn-on method is used, the waveform of node C is a logical product of the waveform of node A and the waveform of node B. It's like that. That is, the clock passing through the node C overlaps the clocks of the node A and the node B so that the pulse width tW is increased by the propagation delay (tPD) of the unit delay element. 'TCK' in the figure represents a clock period.

However, in order to reduce jitter, the unit delay device (see FIG. 4) is designed to transmit the falling edge of the clock faster and the rising edge relatively slower than the falling edge. As a result, the clock passes through the unit delay element and the width of the low pulse becomes wider, which eventually disables the clock low. 6 is a diagram illustrating a process of changing a clock waveform passing through a delay line.

Let's explain the above problem quantitatively. If the clock period is tCK, the pulse width is tW, the falling edge propagation delay of the unit delay element is tPDF, and the rising edge propagation delay of the unit delay element is called tPDR, this clock is equal to (tPDR-tPDF) each time it passes the unit delay element. The pulse width is increased. Therefore, the clock is disabled low when it passes through (tCK-tW) / (tPDR-tPDF) unit delay elements.

Referring to FIG. 5 again, in the case of using the conventional 2-path turn-on delay monitor, it can be seen that the pulse width of the clock increases by the propagation delay (tPD), so that the value of (tCK-tW) increases accordingly. Will be reduced. This increases the likelihood that the clock will be disabled low, which limits the DLL's operating frequency range.

The present invention has been proposed to solve the problems of the prior art as described above, and the delay monitor and delay line control method of the register control delay locked loop which can improve the phenomenon that the clock passing through the delay line is low. The purpose is to provide.

1 is a block diagram of a register control DLL used in a typical DDR SDRAM.

2 is a circuit diagram of a delay monitor according to the prior art.

3 is an exemplary diagram of a two-path turn-on scheme according to the prior art.

4 is an exemplary diagram of a unit delay element constituting a delay line.

5 is a timing diagram of nodes A, B, and C of FIG. 2;

6 illustrates a process of changing a clock waveform through a delay line.

7 is a circuit diagram of a delay monitor according to an embodiment of the present invention.

8 is an illustration of a one-path turn-on scheme in accordance with the present invention.

* Explanation of symbols for the main parts of the drawings

14: first delay line

15: second delay line

16: third delay line

17: shift register

According to an aspect of the present invention for achieving the above technical problem, a delay monitor of a register control delay locked loop, comprising: a plurality of delay lines having an internal clock as an input, and having a series of unit delay elements; A shift register having a plurality of registers, the shift register determining a delay amount of the delay line by its output; Shift control means for controlling the shift register; And a plurality of output logic gates having the output of the nth register and the positive output of the n + 1th register as inputs.

In addition, the present invention provides a delay line control method of a delay monitor of a register control delay lock loop, wherein the negative output of the nth register and the positive output of the n + 1 register among a plurality of registers constituting the shift register are negative logically. A delay line control method of a delay monitor of a register control delay lock loop, which comprises turning on one clock path to a delay line by using a?

In the present invention, in implementing the delay monitor of the register control delay lock loop, only one clock path is generated by the output of the shift register. That is, the conventional 2-path turn-on method was changed to the 1-path turn-on method. In this case, compared to the conventional DLL, the pulse width of the clock passing through the delay line is reduced by the propagation delay (tPD) of the unit delay device. As a result, the DLL clock is disabled low through the delay line. Can be.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

7 is a diagram illustrating a circuit configuration of a delay monitor according to an embodiment of the present invention. For convenience, a shift controller is not illustrated.

Referring to FIG. 7, the shift register 17 receives the shift control signals SR and SL and the reset signal reset, and has a plurality of registers reg1 having a positive output terminal Q and a negative output terminal Qb, respectively. -Reg8) is provided.

On the other hand, for the output of the shift register 17, a number of negative logic gates corresponding to each of the registers reg1 to reg8 are used, where n (where n is a natural number) is the negative output of the nth register. Qb) and the positive output (Q) of the n + 1th register are input.

In addition, the first delay line 14 is a negative logic gate which inputs the output of the internal clock fall_clK and the negative logic gate synchronized with the falling edge of the external clock clk, and the output and transfer of the negative logic gate. It consists of the delay chain which makes a unit unit the delay unit D which takes the output of a unit delay element as an input unit. The configuration of the second and third delay lines 15 and 16 is also the same as that of the first delay line 14 except for the input clock.

In the delay monitor 10 according to the present embodiment configured as described above, there is only one clock path entering the delay line. That is, when the shift register 17 operates in response to the shift control signals SR and SL, and its output value changes in a specific register, one clock path is turned on.

8 is a diagram illustrating a one-path turn-on method according to the present invention, and shows a state in which a signal is changed in the sixth register (reg6). In this case, the output of the negative logic gate which takes the negative output Qb of the fifth register reg5 and the positive output Q of the sixth register reg6 becomes the logic high, and the clock connected to the negative logic gate The path is turned on (see FIG. 7).

Referring back to FIG. 1, the delay model 22 has information tAC on how quickly the DLL clock will float relative to the external clock. In addition, the delay monitor 10 has delay information tD which must be given to float the DLL clock by tAC with respect to the external clock. In the delay monitor 10, the external clock passes through the unit delay elements corresponding to tD and then outputs the DLL clock. In the present invention, one clock path entering the delay line is used to pass through the delay line while keeping the pulse width of the clock as it is. On the other hand, the register control DLL must initially have one path through which the comparison signal can pass. Therefore, to use this method, one of the inputs of the negative logic gate on the far left of the delay monitor 10 must be fixed low. When the nth negative logic gate is turned off and the n + 1th negative logic gate is turned on, the n + 1th negative logic gate should be turned on first and then the nth negative logic gate should be turned off to prevent glitches of the clock passing through the delay line. have.

The DLL employing the delay monitor of the present embodiment configured as described above can widen the operating frequency range of the DLL. The reason for this is as follows. tCK = tD + tAC. Here, tAC represents the data path side delay of the DDR SDRAM, and tD represents the delay that the clock must pass in the delay monitor. However, if one clock path to the delay line is set, the clock can be passed through more unit delay elements than the conventional DLL while maintaining the waveform without disabling the clock as low. That is, tCK becomes large because tD becomes large. That is, it can operate at a lower frequency than the conventional DLL. On the other hand, if the number of unit delay elements that the external clock must pass for the delay lock of the DLL (meaning that the DLL clock rises tAC ahead of the external clock) is n, n = (tCK-tW) ) / (tPDR-tPDF) is established, from which tCK = tW + n (tPDR-tPDF) is established. Therefore, reducing tW with one clock path entering the delay line reduces tCK, allowing the DLL to operate at higher frequencies. On the other hand, in order to prevent the problem that the clock passing through the delay line is low in the conventional DLL, a method of reducing the difference between tPDF and tPDR by adjusting the size of the unit delay element is used. This method increases the tPDF value, which increases jitter in the DLL. In the present embodiment described above, since the unit delay element is used without adjusting the size of the unit delay element, it is possible to prevent the jitter from increasing even during high frequency operation.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

For example, in the above embodiment, the register control DLL used for the DDR SDRAM has been described as an example. However, the register control DLL of the present invention can be applied to other synchronous semiconductor memories or other synchronous logic.

The above-described present invention has an effect of improving the phenomenon in which the DLL clock passing through the delay line is disabled by applying the 1-path turn-on method to the delay monitor, thereby expanding the operating frequency range of the DLL. have.

Claims (4)

In the delay monitor of the register control delay lock loop, A plurality of delay lines having an internal clock as inputs and having a series of unit delay elements; A shift register having a plurality of registers, the shift register determining a delay amount of the delay line by its output; Shift control means for controlling the shift register; And Multiple output logic gates that accept the negative output of the nth register and the positive output of the n + 1th register A delay monitor of a register control delay lock loop comprising: The method of claim 1, And the output logic gate is a negative logic gate. The method of claim 2, And the negative logic gate corresponding to the first register has a logic low as one input. In the delay line control method of the delay monitor of the register control delay lock loop, Register control delay lock, characterized in that one clock path is turned on in the delay line using a negative logic multiplied by the negative output of the nth register and the positive output of the n + 1 register among the plurality of registers constituting the shift register. Delay line control method of delay monitor of loop.