KR100390947B1 - Method of packaging a semiconductor device - Google Patents
Method of packaging a semiconductor device Download PDFInfo
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- KR100390947B1 KR100390947B1 KR10-2000-0085675A KR20000085675A KR100390947B1 KR 100390947 B1 KR100390947 B1 KR 100390947B1 KR 20000085675 A KR20000085675 A KR 20000085675A KR 100390947 B1 KR100390947 B1 KR 100390947B1
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- single package
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- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
- H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
- H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 반도체 소자의 패키지 방법에 관한 것으로서, 상부 단일 패키지와 하부 단일 패키지를 형성함과 아울러 각각의 단일 패키지의 외측 리드를 제거한 후, 솔더 볼 또는 솔더 패스트를 이용하여 각각의 단일 패키지의 내부에 형성된 리드프레임을 상호 전기적으로 접속하여 스택 패키지를 형성함으로써, 스택 패키지의 제조 공정을 단축함과 아울러 제조 시간을 단축하여 제조 비용을 감소시킬 수 있는 반도체 소자의 패키지 방법을 제시함에 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for packaging a semiconductor device, wherein the upper single package and the lower single package are formed and the outer lead of each single package is removed, and then solder balls or solder fasts are used to form the inside of each single package. By forming a stack package by electrically connecting the formed lead frames to each other, a method of packaging a semiconductor device capable of shortening the manufacturing process of the stack package and shortening the manufacturing time can reduce the manufacturing cost.
Description
본 발명은 반도체 소자의 패키지 방법에 관한 것으로서, 특히 상부 단일 패키지와 하부 단일 패키지를 형성함과 아울러 각각의 단일 패키지의 외측 리드를 제거한 후, 솔더 볼 또는 솔더 패스트를 이용하여 각각의 단일 패키지의 내부에 형성된 리드프레임을 상호 전기적으로 접속하여 스택 패키지를 형성함으로써, 스택 패키지의 제조 공정을 단축함과 아울러 제조 시간을 단축하여 제조 비용을 감소시킬 수 있는 반도체 소자의 패키지 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for packaging a semiconductor device, and more particularly, to form an upper single package and a lower single package, and to remove the outer lead of each single package, and then, using solder balls or solder fasts, the inside of each single package. The present invention relates to a method for packaging a semiconductor device capable of shortening the manufacturing process of the stack package and reducing the manufacturing cost by electrically connecting the lead frames formed thereon to form a stack package.
일반적인 스택 패키지(Stack package)구조(예를 들면, TSOP)의 제조 방법을 간략하게 설명하면 도 1(a) 내지 도 1(c)와 같다.A method of manufacturing a general stack package structure (eg, TSOP) is briefly described with reference to FIGS. 1A to 1C.
도 1(a)를 참조하면, 우선, 스택을 할 수 있도록 상부 TSOP용 패키지(1) 및 하부 TSOP 패키지(2)를 제작한다.Referring to FIG. 1A, first, an upper TSOP package 1 and a lower TSOP package 2 are manufactured to stack.
통상, 상부 TSOP용 패키지(1) 및 하부 TSOP 패키지(2)의 제조 방법은 도시되지 않은 리드프레임(lead frame)의 패드 표면에 도시되지 않은 반도체 칩을 부착시킨 후, 반도체 칩과 도시되지 않은 리드프레임의 각 내측리드를 와이어로 연결하는 와이어 본딩(wire bonding) 공정을 실시하게 된다. 이어서, 리드프레임 상/하부로 노출된 외측리드(3)에 대한 트리밍(trimming)공정을 실시하고 기판으로의 실장을 위하여 외측리드(3)를 절곡하는 포밍(forming)공정을 실시하여 패키지가 완성된다.In general, the manufacturing method of the upper TSOP package 1 and the lower TSOP package 2 is performed by attaching a semiconductor chip (not shown) to a pad surface of a lead frame (not shown), followed by a semiconductor chip and a lead (not shown). A wire bonding process of connecting each inner lead of the frame with a wire is performed. Subsequently, a trimming process is performed on the outer lead 3 exposed to the upper and lower lead frames, and a forming process of bending the outer lead 3 for mounting to the substrate is performed. do.
이렇게 제조된 하부 TSOP 패키지(2)의 배면에 상부 TSOP 패키지(1)를 안착하여 스택구조를 형성한다.The upper TSOP package 1 is seated on the rear surface of the lower TSOP package 2 thus manufactured to form a stack structure.
도 1(b)를 참조하면, 이후, 상부 TSOP 패키지(1) 상부에 접착력이 강한 테이프(4)가 접착된 후, 그 상부에 전도성이 강한 스틱(5)이 접착된다.Referring to FIG. 1 (b), after the adhesive tape 4 is adhered to the upper TSOP package 1, the conductive stick 5 is adhered to the upper portion thereof.
여기서, 도 2에 도시된 바와 같이 스틱(5)의 소정 부위에는 홀(6)이 형성되어 있어 그 홀(6)로 외측리드(3)가 끼워지게 된다.Here, as shown in FIG. 2, a hole 6 is formed in a predetermined portion of the stick 5 so that the outer lead 3 is fitted into the hole 6.
도 1(c)를 참조하면, 이후, 스틱(5)과 외측리드(3)가 전기적으로 접속되기 위해 솔더 패스트(solder paste; 7)를 이용한 포밍(forming)공정에 의해 스틱(5)의 홀(6)이 메꾸어진다.Referring to FIG. 1 (c), the holes of the stick 5 are formed by a forming process using solder paste 7 so that the stick 5 and the outer lead 3 are electrically connected to each other. (6) is filled up.
전술한 바와 같이, 종래 기술은 스택 패키지 방법은 스택 구조를 이루는 단일 칩의 리드를 외부로 노출시켜 서로 접속시킴으로써, 추가적인 포밍공정이 이루어져야 한다. 이로 인해, 공정 단계가 증가함과 아울러 공정시간이 증가되어 제조비용이 증가하는 문제가 도출된다.As described above, the conventional stack package method requires an additional forming process by exposing the leads of a single chip constituting the stack structure to the outside and connecting them to each other. As a result, the process step is increased and the process time is increased, leading to the problem of increased manufacturing costs.
따라서, 본 발명의 목적은 반도체 소자의 스택 패키지 제조공정을 개선하기 위한 반도체 소자의 패키지 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method for packaging a semiconductor device for improving the stack package manufacturing process of the semiconductor device.
본 발명의 또 다른 목적은 상부 단일 패키지와 하부 단일 패키지를 형성함과 아울러 각각의 단일 패키지의 외측 리드를 제거한 후, 솔더 볼 또는 솔더 패스트를 이용하여 각각의 단일 패키지의 내부에 형성된 리드프레임을 상호 전기적으로 접속하여 스택 패키지를 형성함으로써, 스택 패키지의 제조 공정을 단축함과 아울러 제조 시간을 단축하여 제조 비용을 감소시킬 수 있는 반도체 소자의 패키지 방법을 제공함에 있다.It is still another object of the present invention to form an upper single package and a lower single package as well as to remove the outer lead of each single package, and then to interconnect the lead frames formed inside each single package using solder balls or solder fasts. The present invention provides a method for packaging a semiconductor device that can reduce the manufacturing cost by shortening the manufacturing process of the stack package and shortening the manufacturing time by forming the stack package by electrically connecting the stacked package.
도 1(a) 내지 도 1(c)는 종래 기술에 따른 반도체 소자의 패키지 방법을 설명하기 위해 순서적으로 도시한 반도체 소자의 정면도.1 (a) to 1 (c) are front views of a semiconductor device sequentially shown for explaining a method of packaging a semiconductor device according to the prior art;
도 2는 도 1에 도시된 스틱을 확대하여 도시한 정면도 및 측면도.FIG. 2 is an enlarged front view and side view of the stick shown in FIG. 1. FIG.
도 3(a) 내지 도 3(c)는 본 발명의 제 1 실시예에 따른 반도체 소자의 패키지 방법을 설명하기 위해 순서적으로 도시한 반도체 소자의 단면도.3 (a) to 3 (c) are cross-sectional views sequentially illustrating the semiconductor device packaging method according to the first embodiment of the present invention.
도 4는 본 발명의 단일 패키지의 상부를 확대하여 도시한 평면도.Figure 4 is an enlarged plan view of the top of a single package of the present invention.
도 5는 본 발명의 단일 패키지의 하부를 확대하여 도시한 평면도.Figure 5 is an enlarged plan view of the bottom of a single package of the present invention.
도 6은 본 발명의 제 2 실시예에 따른 반도체 소자의 패키지 방법을 설명하기 위해 도시한 반도체 소자의 단면도.FIG. 6 is a cross-sectional view of a semiconductor device for explaining the method of packaging a semiconductor device according to the second embodiment of the present invention; FIG.
도 7은 본 발명의 제 3 실시예에 따른 반도체 소자의 패키지 방법을 설명하기 위해 도시한 반도체 소자의 단면도.FIG. 7 is a cross-sectional view of a semiconductor device for explaining the method of packaging a semiconductor device according to the third embodiment of the present invention; FIG.
도 8은 본 발명의 제 4 실시예에 따른 반도체 소자의 패키지 방법을 설명하기 위해 도시한 반도체 소자의 단면도.8 is a cross-sectional view of a semiconductor device for explaining the method of packaging a semiconductor device according to the fourth embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1 : 상부 TSOP 패키지 2 : 하부 TSOP 패키지1: upper TSOP package 2: lower TSOP package
3 : 외측 리드 4,23 : 테이프3: outer lead 4,23: tape
5 : 스틱 6 : 홀5: stick 6: hole
7,18,20 : 솔더 패스트7,18,20: Solder Fast
11 : 상부 단일 패키지 12 : 하부 단일 패키지11: upper single package 12: lower single package
13 : 반도체 칩 14 : 리드프레임13: semiconductor chip 14: lead frame
15 : 골드 도금층 16 : 골드 와이어15 gold plated layer 16 gold wire
17 : 엑폭시 몰드 컴파운드 19 : 스택 패키지17: epoxy mold compound 19: stack package
21 : 인쇄 회로 보드 22 : 솔더 볼21: printed circuit board 22: solder ball
본 발명은 소정의 상부 단일 패키지와 하부 단일 패키지를 형성하는 단계와; 상기 하부 단일 패키지의 리드 프레임 상부에 전기적인 접속을 위한 도전물로 이루어진 접착부재를 형성하는 단계와; 상기 접착부재 상부에 상기 하부 단일 패키지의 리드 프레임을 안착시키는 단계를 포함한다.The present invention includes forming a predetermined upper single package and a lower single package; Forming an adhesive member made of a conductive material for electrical connection on the upper lead frame of the lower single package; And mounting the lead frame of the lower single package on the adhesive member.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 3(a) 내지 도 3(c)는 본 발명의 일 실시예에 따른 반도체 소자의 패키지 방법을 설명하기 위해 순서적으로 도시한 반도체 소자의 단면도이다.3A to 3C are cross-sectional views of semiconductor devices sequentially illustrated to explain a method of packaging a semiconductor device according to an embodiment of the present invention.
도 3(a)를 참조하면, 도 4 및 도 5에 도시된 바와 같이, 상부 단일 패키지(11) 및 하부 단일 패키지(12)는 반도체 칩(13)과 리드프레임(14)을 골드 와이어(16)로 인터커넥션(interconnection)한 후, 엑포시 몰드 컴파운드(epoxy mold compound; 17)를 이용한 트랜스퍼 몰딩(transfer molding)에 의해 형성된다. 또한, 본딩(bonding)력을 높이기 위해 반도체 칩(13)과 인터커넥션되는 리드프레임(14) 상부에는 골드 도금층(15)이 형성된다.Referring to FIG. 3A, as shown in FIGS. 4 and 5, the upper single package 11 and the lower single package 12 connect the semiconductor chip 13 and the leadframe 14 to the gold wire 16. And then formed by transfer molding using an epoxy mold compound (17). In addition, a gold plating layer 15 is formed on the lead frame 14 interconnected with the semiconductor chip 13 to increase the bonding strength.
도 3(b)를 참조하면, 이후, 하부 단일 패키지(12)의 배면에 형성된 제 1 솔더 패스트(18) 상에 상부 단일 패키지(11)가 안착되어 제 1 솔더 패스트(18)에 의해 상부 단일 패키지(11)의 리드프레임(14)과 하부 단일 패키지(12)의 리드프레임(14)이 전기적으로 접속되어 스택 패키지(19)가 형성된다.Referring to FIG. 3 (b), the upper single package 11 is then seated on the first solder fast 18 formed on the rear surface of the lower single package 12, and the upper single package 11 is mounted by the first solder fast 18. The leadframe 14 of the package 11 and the leadframe 14 of the lower single package 12 are electrically connected to each other to form a stack package 19.
여기서, 도 6에 도시된 바와 같이, 상부 단일 패키지(11)의 리드프레임(14)과 하부 단일 패키지(12)의 리드프레임(14)을 전기적으로 접속하기 위해 솔더 볼(22)이 사용될 수 있다.Here, as shown in FIG. 6, the solder ball 22 may be used to electrically connect the leadframe 14 of the upper single package 11 and the leadframe 14 of the lower single package 12. .
또한, 도 8에 도시된 바와 같이, 제 1 솔더 패스트(18) 간에 형성된 빈공간에는 테이프(23) 또는 솔더 볼(22)이 증착되어 상부 단일 패키지(11)와 하부 단일패키지(12)간의 접착력을 증가시킴과 아울러 전체적인 스택 패키지(19)의 높이를 조절할 수 있다.In addition, as shown in FIG. 8, the tape 23 or the solder balls 22 are deposited in the empty spaces formed between the first solder fasts 18 so that the adhesive force between the upper single package 11 and the lower single package 12 is reduced. In addition to increasing the overall height of the stack package 19 can be adjusted.
도 3(c)를 참조하면, 이후, 제 2 솔더 패스트(20)에 의해 스택 패키지(19)와 인쇄 회로 보드(print circuit board; PCB, 20)가 접착된다.Referring to FIG. 3C, a stack package 19 and a printed circuit board (PCB) 20 are bonded to each other by the second solder fast 20.
여기서, 도 7에 도시된 바와 같이, 스택 패키지(19)와 인쇄 회로 보드(20)을 접속하기 위해 솔더 볼(22)이 사용될 수 있다.Here, as shown in FIG. 7, solder balls 22 may be used to connect the stack package 19 and the printed circuit board 20.
전술한 바와 같이, 본 발명은 상부 단일 패키지와 하부 단일 패키지를 형성함과 아울러 각각의 단일 패키지의 외측 리드를 제거한 후, 솔더 볼 또는 솔더 패스트를 이용하여 각각의 단일 패키지의 내부에 형성된 리드프레임을 상호 전기적으로 접속하여 스택 패키지를 형성한다.As described above, the present invention forms the upper single package and the lower single package, removes the outer lead of each single package, and then uses a solder ball or solder fast to form a lead frame formed inside each single package. They are electrically connected to each other to form a stack package.
상술한 바와 같이, 본 발명은 상부 단일 패키지와 하부 단일 패키지를 형성함과 아울러 각각의 단일 패키지의 외측 리드를 제거한 후, 솔더 볼 또는 솔더 패스트를 이용하여 각각의 단일 패키지의 내부에 형성된 리드프레임을 상호 전기적으로 접속하여 스택 패키지를 형성함으로써, 스택 패키지의 제조 공정을 단축함과 아울러 제조 시간을 단축하여 제조 비용을 감소시킬 수 있다.As described above, the present invention forms the upper single package and the lower single package, removes the outer lead of each single package, and then uses a solder ball or solder fast to form a lead frame formed inside each single package. By electrically connecting each other to form a stack package, the manufacturing process of the stack package can be shortened and the manufacturing time can be shortened to reduce the manufacturing cost.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0085675A KR100390947B1 (en) | 2000-12-29 | 2000-12-29 | Method of packaging a semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR10-2000-0085675A KR100390947B1 (en) | 2000-12-29 | 2000-12-29 | Method of packaging a semiconductor device |
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| KR20020056346A KR20020056346A (en) | 2002-07-10 |
| KR100390947B1 true KR100390947B1 (en) | 2003-07-10 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5744827A (en) * | 1995-11-28 | 1998-04-28 | Samsung Electronics Co., Ltd. | Three dimensional stack package device having exposed coupling lead portions and vertical interconnection elements |
| JP2000012771A (en) * | 1998-06-19 | 2000-01-14 | Nec Corp | Semiconductor device |
| JP2000031372A (en) * | 1998-06-30 | 2000-01-28 | Hyundai Electron Ind Co Ltd | Stacked package |
| KR20000043560A (en) * | 1998-12-29 | 2000-07-15 | 김영환 | Chip sized stack package and manufacturing method thereof |
| KR20010066269A (en) * | 1999-12-31 | 2001-07-11 | 마이클 디. 오브라이언 | semiconductor package and metod for fabricating the same |
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2000
- 2000-12-29 KR KR10-2000-0085675A patent/KR100390947B1/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5744827A (en) * | 1995-11-28 | 1998-04-28 | Samsung Electronics Co., Ltd. | Three dimensional stack package device having exposed coupling lead portions and vertical interconnection elements |
| JP2000012771A (en) * | 1998-06-19 | 2000-01-14 | Nec Corp | Semiconductor device |
| JP2000031372A (en) * | 1998-06-30 | 2000-01-28 | Hyundai Electron Ind Co Ltd | Stacked package |
| KR20000043560A (en) * | 1998-12-29 | 2000-07-15 | 김영환 | Chip sized stack package and manufacturing method thereof |
| KR20010066269A (en) * | 1999-12-31 | 2001-07-11 | 마이클 디. 오브라이언 | semiconductor package and metod for fabricating the same |
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