KR100408182B1 - Copper barrier layer for copper layer - Google Patents
Copper barrier layer for copper layer Download PDFInfo
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- KR100408182B1 KR100408182B1 KR10-2001-0008395A KR20010008395A KR100408182B1 KR 100408182 B1 KR100408182 B1 KR 100408182B1 KR 20010008395 A KR20010008395 A KR 20010008395A KR 100408182 B1 KR100408182 B1 KR 100408182B1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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Abstract
본 발명은 구리 배선을 사용하는 반도체 소자에서 비아홀 형성 공정의 간소화를 실현함과 동시에 반도체 소자의 신뢰성을 증진시킬 수 있도록 하기 위한 것으로, 이를 위하여 본 발명은, 구리 배선의 확산 장벽층으로 실리콘 질화막(SiN)을 사용하는 종래 방법과는 달리, 구리 배선의 확산 장벽층으로 텅스텐(W)을 사용함으로써 후속하는 비아홀 형성 과정에서의 공정 간소화를 실현할 수 있을 뿐만 아니라 비아홀 형성 과정 중에 발생 가능한 구리 배선의 산화 및 부식 현상을 근본적으로 차단함으로써 반도체 소자의 신뢰성을 증진시킬 수 있는 것이다.The present invention is to realize the simplification of the via hole forming process in a semiconductor device using a copper wiring and to improve the reliability of the semiconductor device. To this end, the present invention provides a silicon nitride film (A) as a diffusion barrier layer of a copper wiring. Unlike conventional methods using SiN), the use of tungsten (W) as the diffusion barrier layer of the copper wiring not only realizes the process simplification in the subsequent via hole formation, but also oxidizes the copper wiring that may occur during the via hole formation. And it is possible to improve the reliability of the semiconductor device by fundamentally blocking the corrosion phenomenon.
Description
본 발명은 반도체용 구리 배선에 관한 것으로, 더욱 상세하게는 반도체 칩의 고집적화 및 고신뢰화를 실현 가능한 구리 배선용 장벽층을 형성하는데 적합한 구리 배선용 장벽층 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a copper wiring for semiconductor, and more particularly, to a method for forming a barrier layer for copper wiring suitable for forming a barrier layer for copper wiring that can realize high integration and high reliability of a semiconductor chip.
잘 알려진 바와 같이, 알루미늄(Al) 및 그 합금 박막은, 높은 전기 전도도,건식 식각에 의한 패턴 형성의 우수성, 실리콘 산화막과의 우수한 접착성 및 저렴한 가격으로 인해서, 반도체 칩의 금속 배선으로 널리 사용되고 있다.As is well known, aluminum (Al) and its alloy thin films are widely used for metal wiring of semiconductor chips due to their high electrical conductivity, excellent pattern formation by dry etching, good adhesion to silicon oxide film, and low price. .
그러나, 반도체 칩의 집적도가 증가함에 따라서 금속 배선의 선폭이 감소되고 있는데, 그와 같은 선폭 감소는 알루미늄(Al)의 전기적 물질 이동(Electromigration)이나 스트레스 마이그레이션(stressmigration) 등을 심화시켜서 단선 유발 가능성을 증가시킨다. 그와 같이 고집적화 되어 가는 반도체 칩에서는 알루미늄(Al)을 금속 배선으로 사용할 경우 단선될 가능성이 커서, 반도체 칩의 신뢰성을 확보하기 어렵게 된다.However, as the degree of integration of semiconductor chips increases, the line width of metal wirings decreases. Such decrease in line width increases the electrical material migration and stress migration of aluminum (Al), thereby causing the possibility of disconnection. Increase. In such a highly integrated semiconductor chip, when aluminum (Al) is used as the metal wiring, the disconnection is likely to be large, making it difficult to secure the reliability of the semiconductor chip.
더욱이, 반도체 칩이 고집적화 되어감에 따라서 배선의 선폭이 감소됨과 아울러 배선간의 간격도 좁아지고 그로 인해 콘택홀 또는 비아홀의 크기가 점점 작아지게 됨으로써, 홀의 종횡비(aspect ratio)가 증가되고 있다. 그와 같이 홀의 종횡비가 증가되면, 홀 내에서 금속을 매립할 때 단차 피복성(step coverage)이 저하되므로, 국부적으로 금속 배선이 얇게 형성되고, 그와 같은 부분에서 알루미늄(Al) 배선의 단선 발생 확률은 더욱 커지게 된다.Furthermore, as semiconductor chips become more integrated, the line width of the wirings is reduced, and the spacing between the wirings is narrowed, and as a result, the size of the contact hole or via hole becomes smaller, thereby increasing the aspect ratio of the holes. As such, when the aspect ratio of the hole is increased, step coverage decreases when the metal is buried in the hole, so that a thin metal wiring is locally formed, and disconnection of the aluminum (Al) wiring occurs at such a portion. The probability is even greater.
따라서, 최근의 기술 발전 추이로 볼 때, 종래에 반도체 칩의 금속 배선 재료로 널리 사용되던 알루미늄(Al)을 대체할 금속 재료가 요구되고 있으며, 이러한 알루미늄(Al)을 대체할 금속재료로서 구리(Cu)가 고려되고 있다. 즉, 구리(Cu)의 경우 알루미늄(Al)에 비해서 비저항이 낮고 전기적 물질이동이나 스트레스 마이그레이션 특성이 우수하므로, 그와 같은 구리를 반도체 칩의 금속 배선으로 채용함으로써, 고집적화 및 고성능화 되어 가는 반도체 칩의 신뢰성을 증진시킬 것으로 기대되고 있다.Therefore, in view of recent technological developments, there is a demand for a metal material to replace aluminum (Al), which has been widely used as a metal wiring material of a semiconductor chip, and copper (C) as a metal material to replace such aluminum (Al). Cu) is under consideration. That is, copper (Cu) has a lower specific resistance than aluminum (Al) and has excellent electrical mass transfer and stress migration characteristics. It is expected to increase reliability.
한편, 반도체 기판 상에 회로 소자를 형성하면, 콘택홀을 형성하여 회로 소자의 전극 단자와 금속 배선(즉, 구리 배선)간을 전기적으로 접속시키고, 또한 비아홀을 형성하여 층 간에 형성된 금속 배선(즉, 구리 배선)간을 전기적으로 접속시킨다.On the other hand, when a circuit element is formed on a semiconductor substrate, a contact hole is formed to electrically connect between the electrode terminal of the circuit element and the metal wiring (i.e., copper wiring), and a metal wiring formed between the layers by forming a via hole (i.e., And copper wiring) are electrically connected.
보다 상세하게, 전기적으로 접속하고자 하는 전극 단자의 상부를 노출시키는 콘택홀 영역을 뚫어 금속 물질(즉, 구리 물질)로 매립함으로써 콘택홀을 형성하고, 콘텍홀의 상부에 구리 배선을 형성한다.In more detail, a contact hole is formed by filling a contact hole region exposing an upper portion of an electrode terminal to be electrically connected with a metal material (ie, a copper material), and a copper wiring is formed on the contact hole.
이때, 구리는 산화계 IMD(inter metal dielectric) 물질(BPSG, FSG 등)에 확산이 잘 일어난다는 문제가 있기 때문에 구리 배선을 형성한 후에 그 상부에 확산 장벽층을 형성해야만 하는데, 이러한 확산 장벽층으로는 실리콘 질화막(SiN)이 사용되고 있다. 즉, 구리가 IMD 층에 확산되면 이것들이 이동하여 회로 소자의 게이트 전극에까지 도달하게 됨으로써 소자 특성에 악영향을 미치게 된다. 따라서, 구리의 확산 장벽층을 형성하는 것은 필수적이라 할 수 있다.At this time, copper has a problem that diffusion occurs easily in an oxidized intermetal dielectric (IMD) material (BPSG, FSG, etc.). Therefore, after forming copper wiring, a diffusion barrier layer must be formed thereon. Silicon nitride film (SiN) is used. In other words, when copper diffuses into the IMD layer, they move and reach the gate electrode of the circuit element, which adversely affects device characteristics. Therefore, it can be said to form a diffusion barrier layer of copper.
한편, 층 간에 형성될 구리 배선간을 연결하기 위해서는 IMD 층을 선택적으로 제거하여 하부 구리 배선 상부를 노출시키는 비아홀 영역을 형성하고, 비아홀 영역에 구리 물질을 매립함으로써 비아홀을 형성하게 되는데, 이때 종래 방법에 따라 구리의 확산 장벽층으로 실리콘 질화막을 사용하는 경우 두 번의 식각 공정을 통해 비아홀 영역을 형성한다.On the other hand, in order to connect the copper interconnects to be formed between the layers, the IMD layer is selectively removed to form a via hole region exposing an upper portion of the lower copper interconnection, and a via hole is formed by filling a copper material in the via hole region. In the case of using a silicon nitride film as a copper diffusion barrier layer, a via hole region is formed through two etching processes.
즉, IMD 물질과 실리콘 질화막은 식각 선택비가 다르기 때문에 IMD 물질의식각에 적합한 공정 조건 하에서 1차 식각 공정을 수행하여 IMD 물질을 제거함으로써 실리콘 질화막(구리의 확산 장벽층)의 상부를 노출시키고, 이어서 실리콘 질화막의 식각에 적합한 공정 조건 하에서 2차 식각 공정을 수행하여 실리콘 질화막을 제거해 하부의 구리 배선을 노출시킴으로써 비아홀 영역을 형성하게 된다.That is, since the IMD material and the silicon nitride film have different etching selectivity, the upper part of the silicon nitride film (copper diffusion barrier layer) is exposed by performing a first etching process under a process condition suitable for etching the IMD material to remove the IMD material. The second etching process may be performed under a process condition suitable for etching the silicon nitride layer to remove the silicon nitride layer to expose the lower copper wiring to form a via hole region.
따라서, 종래 방법에 따라 구리의 확산 장벽층으로 실리콘 질화막을 사용하는 경우, 후속하는 비아홀 형성 공정에서, 한번의 식각 공정을 통해 비아홀 영역을 형성하지 못하고 두 번의 식각 공정을 수행해야만 하기 때문에 비아홀을 형성하는 공정이 불필요하게 복잡해지는 문제가 있다.Therefore, when the silicon nitride film is used as the diffusion barrier layer of copper according to the conventional method, in the subsequent via hole forming process, the via hole is formed because the via hole region cannot be formed through one etching process and two etching processes must be performed. There is a problem that the process to be unnecessarily complicated.
또한, 종래 방법에 따라 구리의 확산 장벽층으로 실리콘 질화막을 사용하는 경우, 비아홀 영역을 형성할 때 구리 배선을 노출시켜야 하기 때문에 이로 인해 구리 배선의 상부에 구리 산화막이 형성되고, 이러한 구리 산화막이 저항을 높이는 요인으로 작용하게 됨으로써 반도체 소자의 신뢰성을 떨어뜨리게 되는 문제점을 가질 뿐만 아니라 노출된 구리 배선에서 부식 현상이 야기됨으로써, 반도체 소자의 신뢰성을 더욱 저하시키는 문제점을 갖는다.In addition, when the silicon nitride film is used as the diffusion barrier layer of copper according to the conventional method, a copper oxide film is formed on top of the copper wiring because the copper wiring must be exposed when the via hole region is formed, which causes the copper oxide film to resist. By acting as a factor to increase the not only has a problem of lowering the reliability of the semiconductor device, but also causes a corrosion phenomenon in the exposed copper wiring, there is a problem that further lowers the reliability of the semiconductor device.
더욱이, 종래 방법에 따라 구리의 확산 장벽층으로 실리콘 질화막을 사용하는 경우, 유전율이 높아 반도체 소자의 동작 속도에 악영향을 미치는 단점을 갖는다.Moreover, when the silicon nitride film is used as the diffusion barrier layer of copper according to the conventional method, it has a disadvantage that the dielectric constant is high to adversely affect the operating speed of the semiconductor device.
본 발명은 상술한 종래 기술의 문제점을 해결하기 위한 것으로, 후속하는 비아홀 형성 공정의 간소화를 실현함과 동시에 반도체 소자의 신뢰성을 증진시킬 수있는 구리 배선용 장벽층 형성 방법을 제공하는 데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the prior art, and an object thereof is to provide a method for forming a barrier layer for copper wiring that can realize a subsequent via hole forming process and at the same time improve reliability of a semiconductor device. .
상기 목적을 달성하기 위하여 본 발명은, 내부에 다수의 전극을 갖는 회로 소자들이 내장된 반도체 기판 상에 구리 배선용의 장벽층을 형성하는 방법에 있어서, 상기 회로 소자를 매립하는 형태로 반도체 기판의 상부 전면에 걸쳐 산화막의 일부를 선택적으로 제거함으로써 하부 전극의 상부를 노출시키는 콘택홀 및 구리 배선 영역을 형성하는 과정; 상기 반도체 기판의 상부 전면에 걸쳐 소정 두께의 콘택 장벽 물질을 형성하는 과정; 상기 콘택홀 및 구리 배선 영역이 완전히 매립되는 형태로 상기 반도체 기판의 상부 전면에 걸쳐 구리 물질을 형성하는 과정; CMP 공정을 수행하여 상기 산화막의 상부에 형성된 구리 물질 및 콘택 장벽 물질을 제거함으로써, 콘택 장벽층과 콘택홀 및 구리 배선을 형성하는 과정; 및 선택적인 텅스텐 증착 공정을 수행하여 상기 구리 배선의 상부에 소정 두께의 텅스텐으로 된 확산 장벽층을 형성하는 과정으로 이루어진 구리 배선용 장벽층 형성 방법을 제공한다.In order to achieve the above object, the present invention is a method for forming a barrier layer for copper wiring on a semiconductor substrate having a circuit element having a plurality of electrodes therein, the upper portion of the semiconductor substrate in the form of embedding the circuit element Selectively removing a portion of the oxide film over the entire surface to form a contact hole and a copper wiring region exposing an upper portion of the lower electrode; Forming a contact barrier material of a predetermined thickness over the upper front surface of the semiconductor substrate; Forming a copper material over the entire upper surface of the semiconductor substrate in such a manner that the contact hole and the copper wiring region are completely filled; Forming a contact barrier layer, a contact hole and a copper wiring by performing a CMP process to remove the copper material and the contact barrier material formed on the oxide film; And forming a diffusion barrier layer of tungsten having a predetermined thickness on top of the copper wiring by performing a selective tungsten deposition process.
도 1의 (a) 내지 (f)는 본 발명의 바람직한 실시 예에 따라 회로 소자가 형성된 기판 상에 콘택홀과 구리 배선 및 구리 배선의 확산 장벽층을 형성하는 과정을 순차적으로 도시한 공정 순서도.1 (a) to (f) is a process flow diagram sequentially showing a process of forming a contact barrier, a copper wiring and a diffusion barrier layer of a copper wiring on a substrate on which a circuit element is formed according to a preferred embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of Symbols for Main Parts of Drawings>
100 : 반도체 기판 102a1, 102a2 : 게이트 전극100 semiconductor substrate 102a1, 102a2 gate electrode
102b1, 102b2 : 소오스 전극 102c1, 102c2 : 드레인 전극102b1, 102b2: source electrode 102c1, 102c2: drain electrode
104 : 구리 배선 및 콘택홀 영역 106 : 콘택 장벽층104: copper wiring and contact hole region 106: contact barrier layer
108 : 구리 배선 및 콘택홀 110 : 확산 장벽층108: copper wiring and contact hole 110: diffusion barrier layer
112 : 산화막 114 : 비아홀 영역112: oxide film 114: via hole region
본 발명의 상기 및 기타 목적과 여러 가지 장점은 이 기술분야에 숙련된 사람들에 의해 첨부된 도면을 참조하여 하기에 기술되는 본 발명의 바람직한 실시 예로부터 더욱 명확하게 될 것이다.The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.
이하 첨부된 도면을 참조하여 본 고안의 바람직한 실시 예에 대하여 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명의 핵심 기술사상은, 구리 배선의 확산 장벽층으로 실리콘질화막(SiN)을 사용하는 종래 방법과는 달리, 구리 배선의 확산 장벽층으로 텅스텐(W)을 사용함으로써 후속하는 비아홀 형성 과정에서의 공정 간소화를 실현하고, 비아홀 형성 과정 중에 발생 가능한 구리 배선의 산화 및 부식 현상을 근본적으로 차단함으로써 반도체 소자의 신뢰성을 증진시킨다는 것으로, 이러한 기술적 수단을 통해 본 발명에서 목적으로 하는 바를 쉽게 달성할 수 있다.The core idea of the present invention is that in the subsequent via hole formation process, by using tungsten (W) as the diffusion barrier layer of the copper wiring, unlike the conventional method using the silicon nitride film (SiN) as the diffusion barrier layer of the copper wiring. By realizing the process simplification and fundamentally blocking the oxidation and corrosion of the copper wiring which may occur during the via hole formation process, the reliability of the semiconductor device is improved. Through such technical means, the object of the present invention can be easily achieved. .
도 1의 (a) 내지 (f)는 본 발명의 바람직한 실시 예에 따라 회로 소자가 형성된 기판 상에 콘택홀과 구리 배선 및 구리 배선의 확산 장벽층을 형성하는 과정을 순차적으로 도시한 공정 순서도이다.1A to 1F are process flowcharts sequentially illustrating a process of forming a contact hole, a copper wiring, and a diffusion barrier layer of a copper wiring on a substrate on which a circuit element is formed according to a preferred embodiment of the present invention. .
도 1의 (a)를 참조하면, 게이트 전극(102a1, 102a2), 소오스 전극(102b1, 102b2) 및 드레인 전극(102c1, 102c2)을 갖는 회로 소자가 형성되고, 회로 소자를 매립하는 형태로 그 상부에 산화계 IMD 물질(BPSG, FSG 등)이 순차 적층된 반도체 기판(100)에 대해 마스크 공정(또는 포토리소그라피 공정) 및 식각 공정을 수행함으로써 목표로 하는 하부 전극(예를 들면, 드레인 전극(102b1, 102b2))의 상부를 노출시키는 구리 배선 및 콘택홀 영역(104)을 형성한다.Referring to FIG. 1A, a circuit element having the gate electrodes 102a1 and 102a2, the source electrodes 102b1 and 102b2, and the drain electrodes 102c1 and 102c2 is formed, and an upper portion thereof in a form of embedding the circuit elements. The target lower electrode (for example, the drain electrode 102b1, by performing a mask process (or photolithography process) and an etching process on the semiconductor substrate 100 on which oxidized IMD materials (BPSG, FSG, etc.) are sequentially stacked). A copper wiring and contact hole region 104 exposing the top of 102b2)) is formed.
이어서, 반도체 기판(100)에 반응성 스퍼터링에 의한 물리 기상 증착(PVD) 공정 또는 화학 기상 증착(CVD) 공정 등을 적용함으로써, 일 예로서 도 1의 (b)에 도시된 바와 같이, 구리 배선 및 콘택홀 영역(104)이 형성된 반도체 기판(100)의 상부 전면에 걸쳐 티타늄/질화 티타늄(Ti/TiN)으로 된 소정 두께의 콘택 장벽 물질(106')을 형성한다.Subsequently, by applying a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process by reactive sputtering to the semiconductor substrate 100, as an example, as shown in FIG. A contact barrier material 106 'having a predetermined thickness of titanium / titanium nitride (Ti / TiN) is formed over the upper front surface of the semiconductor substrate 100 on which the contact hole region 104 is formed.
다음에, 물리 기상 증착 또는 화학 기상 증착 공정을 순차 수행함으로써, 일예로서 도 1의 (c)에 도시된 바와 같이, 구리 배선 및 콘택홀 영역(104)이 완전히 매립되는 형태로 반도체 기판(100)의 전면에 구리 시드 층 및 구리 물질(108')을 형성한다. 즉, 본 발명에서는 한번의 증착 공정을 통해 콘택홀 영역과 구리 배선 영역에 구리 물질을 형성한다.Next, by sequentially performing a physical vapor deposition or chemical vapor deposition process, as shown in FIG. 1C, for example, the semiconductor substrate 100 in a form in which the copper wirings and the contact hole regions 104 are completely embedded. A copper seed layer and a copper material 108 'are formed on the front side of the. That is, in the present invention, a copper material is formed in the contact hole region and the copper wiring region through one deposition process.
그런 다음, 금속 물질에 대한 식각 선택비가 양호한 식각제를 사용하는 CMP 공정을 수행하여, 산화계 IMD 물질의 상부에 있는 구리 물질(108') 및 콘택 장벽 물질(106')을 제거함으로써, 구리 배선 및 콘택홀 영역에 콘택 장벽층(106)과 구리 배선 및 콘택홀(108)을 형성한다. 도 1의 (d)에서, 하부에 있는 폭이 좁은 부분이 콘택홀을 의미하고, 상부에 있는 폭이 넓은 부분이 구리 배선을 의미한다.Thereafter, a CMP process using an etchant having a good etching selectivity with respect to the metal material is performed to remove the copper material 108 'and the contact barrier material 106' on top of the oxidizing IMD material, thereby removing the copper wiring and The contact barrier layer 106 and the copper wiring and the contact hole 108 are formed in the contact hole region. In Figure 1 (d), the narrow portion at the bottom means the contact hole, the wide portion at the top means the copper wiring.
이때, 금속 계열인 구리 물질(108')과 콘택 장벽 물질(106')의 식각 선택비가 비금속 계열인 산화계 IMD 물질의 식각 선택비보다 좋기 때문에, 일 예로서 도 1의 (d)에 도시된 바와 같이, 구리 배선 영역에 매립된 구리 물질(108') 및 콘택 장벽 물질(106')이 더 많이 식각된다. 여기에서, 산화계 IMD 물질에 대한 상대적인 구리 배선의 낮음 정도는 대략 50 - 100Å 정도가 바람직하며, 이러한 낮음 정도의 범위는 CMP 공정 중에 공정 시간과 RPM을 제어함으로써 실현할 수 있다.At this time, since the etching selectivity of the metal-based copper material 108 'and the contact barrier material 106' is better than that of the non-metal-based oxidized IMD material, as shown in FIG. Likewise, more copper material 108 'and contact barrier material 106' embedded in the copper wiring region are etched. Here, the low degree of the copper wiring relative to the oxidized IMD material is preferably about 50-100 kPa, and this low range can be realized by controlling the process time and RPM during the CMP process.
다음에, 구리 배선 및 콘택홀(108)이 형성된 반도체 기판(100)에 대해 임의의 공정 조건, 예를 들면 온도 250 - 350℃(바람직하게는 300℃), 전체 압력 0.25 Torr 이하, H2 flow rate 75cc/min, WF6 flow rate 10cc/min의 공정 조건에서 선택적인 텅스텐 증착 공정을 수행함으로써, 일 예로서 도 1의 (e)에 도시된 바와 같이, 구리 배선의 상부에만 선택적으로 소정 두께, 예를 들면 100Å이하의 금속 계열인 텅스텐(W)으로 된 확산 장벽층(110)을 형성한다. 즉, 선택적인 텅스텐 증착 공정에서는 구리 배선의 상부에만 확산 장벽층(110)이 형성되고 IMD 물질에는 형성되지 않는다.Next, any process conditions for the semiconductor substrate 100 on which the copper wirings and the contact holes 108 are formed, for example, a temperature of 250 to 350 ° C. (preferably 300 ° C.), a total pressure of 0.25 Torr or less, and an H 2 flow rate By performing a selective tungsten deposition process at a process condition of 75 cc / min and a WF6 flow rate of 10 cc / min, as an example, as shown in FIG. For example, a diffusion barrier layer 110 made of tungsten (W), which is a metal series of 100 mW or less, is formed. That is, in the selective tungsten deposition process, the diffusion barrier layer 110 is formed only on the upper portion of the copper wiring and not on the IMD material.
따라서, 본 발명에서는 상술한 바와 같은 일련의 공정들을 통해 구리 배선 상에 금속 계열인 텅스텐으로 된 확산 장벽층(110)을 형성하며, 이후에는 반도체 기판(100)의 상부 전면에 걸쳐 산화계 IMD 물질을 증착한 후 구리 배선과 전기적으로 접속하는 비아홀(즉, 구리 물질로 매립되는 비아홀)을 형성하는 공정을 수행하게 될 것이다.Accordingly, in the present invention, a diffusion barrier layer 110 made of tungsten, which is a metal series, is formed on a copper wiring through a series of processes as described above, and then an oxidized IMD material is applied over the entire upper surface of the semiconductor substrate 100. After deposition, a process of forming a via hole (ie, a via hole filled with a copper material) to be electrically connected to the copper wiring will be performed.
즉, 구리 배선의 상부에 확산 장벽층(110)이 형성된 반도체 기판(100)의 전면에 걸쳐 산화계인 IMD 물질(112)을 증착한 후, 마스크 공정(또는 포토리소그라피 공정) 및 식각 공정을 수행하여 IMD 물질(112)을 선택적으로 제거함으로써, 일 예로서 도 1의 (f)에 도시된 바와 같이, 확산 장벽층(110)의 상부를 노출시키는 비아홀(114)을 형성한다. 이어서, 이후의 후속 공정들을 통해 층 간에 형성된 구리 배선간을 전기적으로 접속시키는 비아홀 형성 공정을 수행하게 된다.In other words, an oxide-based IMD material 112 is deposited over the entire surface of the semiconductor substrate 100 on which the diffusion barrier layer 110 is formed, and then a mask process (or photolithography process) and an etching process are performed. By selectively removing the IMD material 112, as an example, a via hole 114 exposing the top of the diffusion barrier layer 110 is formed, as shown in FIG. 1F. Subsequently, a via hole forming process of electrically connecting the copper interconnects formed between the layers may be performed through subsequent processes.
이때, 종래 방법에서는 확산 장벽층으로 실리콘 질화막을 사용하기 때문에 1차 식각 공정을 수행하여 IMD 물질을 제거한 후 공정 조건을 달리하는 2차 식각 공정을 통해 실리콘 질화막을 제거하여 하부의 구리 배선을 노출시키는 두 단계의 식각 공정을 통해 비아홀을 형성하였으나, 본 발명에서는 확산 장벽층으로 금속 계열인 텅스텐을 이용하기 때문에 확산 장벽층을 제거하는 식각 공정을 필요롤 하지 않아 단지 한번의 식각 공정을 통해 비아홀을 형성할 수 있다.In this case, in the conventional method, since the silicon nitride film is used as the diffusion barrier layer, the first copper etching process is performed to remove the IMD material, and then the silicon nitride film is removed through the second etching process having different process conditions to expose the lower copper wiring. Although the via hole is formed through the two-step etching process, in the present invention, since the tungsten, which is a metal-based metal, is used as the diffusion barrier layer, an etching process for removing the diffusion barrier layer is not required. Thus, the via hole is formed through only one etching process. can do.
따라서, 본 발명은, 종래 방법과 비교해 볼 때, 후속하는 비아홀 형성 공정에서의 간소화를 실현할 수 있다.Accordingly, the present invention can realize the simplification in the subsequent via hole forming step as compared with the conventional method.
또한, 확산 장벽층으로 실리콘 질화막을 사용하는 종래 방법에 따라 비아홀 영역을 형성을 위해 구리 배선을 노출시킬 때, 구리 배선의 상부에 구리 산화막이 형성되고, 이러한 구리 산화막이 저항을 높이는 요인으로 작용하게 되고, 또한 구리 배선이 부식되는 현상이 야기됨으로써, 반도체 소자의 신뢰성이 저하되는 문제점을 갖지만, 본 발명에서는 금속 계열인 텅스텐을 확산 장벽층으로 사용하기 때문에 비아홀 형성 시에 구리 배선을 노출시킬 필요가 없기 때문에 구리 배선의 저항 증가 및 부식 등을 근본적으로 차단할 수 있어, 반도체 소자의 신뢰성을 증진시킬 수 있다.In addition, when exposing the copper wiring to form the via hole region according to the conventional method of using a silicon nitride film as the diffusion barrier layer, a copper oxide film is formed on the upper portion of the copper wiring, and the copper oxide film acts as a factor to increase the resistance. In addition, the copper wiring is corroded, which causes a problem of lowering the reliability of the semiconductor device. However, in the present invention, since the metal-based tungsten is used as the diffusion barrier layer, it is necessary to expose the copper wiring during the formation of the via hole. Since it is possible to fundamentally block the increase in resistance and corrosion of the copper wiring, the reliability of the semiconductor device can be improved.
이상 설명한 바와 같이, 본 발명에 따르면, 구리 배선의 확산 장벽층으로 실리콘 질화막(SiN)을 사용하는 종래 방법과는 달리, 구리 배선의 확산 장벽층으로 텅스텐(W)을 사용함으로써 후속하는 비아홀 형성 과정에서의 공정 간소화를 실현할 수 있을 뿐만 아니라 비아홀 형성 과정 중에 발생 가능한 구리 배선의 산화 및 부식 현상을 근본적으로 차단함으로써 반도체 소자의 신뢰성을 증진시킬 수 있다.As described above, according to the present invention, unlike the conventional method using the silicon nitride film (SiN) as the diffusion barrier layer of the copper wiring, the subsequent via hole formation process by using tungsten (W) as the diffusion barrier layer of the copper wiring. In addition, the process simplification can be realized, and the reliability of the semiconductor device can be enhanced by fundamentally blocking the oxidation and corrosion of the copper wiring which may occur during the via hole formation process.
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