KR100414732B1 - Method for forming a metal line - Google Patents
Method for forming a metal line Download PDFInfo
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- KR100414732B1 KR100414732B1 KR10-2001-0037470A KR20010037470A KR100414732B1 KR 100414732 B1 KR100414732 B1 KR 100414732B1 KR 20010037470 A KR20010037470 A KR 20010037470A KR 100414732 B1 KR100414732 B1 KR 100414732B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 금속배선 형성 방법에 관한 것으로, 특히 하부 금속 배선용 제 1 금속층 상에 제 2 금속층 패턴(Pattern)과 플러그(Plug)를 형성한 후 상기 제 2 금속층 패턴과 플러그를 하드 마스크(Hard mask)층으로 사용하여 하부 금속 배선을 형성하므로 배선 끝 축소 현상을 방지하고, 상기 제 2 금속층 패턴과 플러그를 형성한 후 저 유전 상수 산화막의 단일층인 층간 절연막을 형성하므로 RC 지연을 방지하여 소자의 수율 및 신뢰성을 향상시키는 특징이 있다.The present invention relates to a method for forming a metal wiring, and in particular, after forming a second metal layer pattern and a plug on a first metal layer for lower metal wiring, a hard mask is formed on the second metal layer pattern and the plug. The lower metal wiring is used as a layer to prevent wire end shrinkage, and after forming the second metal layer pattern and the plug, an interlayer insulating film, which is a single layer of a low dielectric constant oxide film, is formed to prevent RC delay, thereby yielding device yield. And improved reliability.
Description
본 발명은 금속배선 형성 방법에 관한 것으로, 특히 하부 금속 배선용 제 1 금속층 상에 제 2 금속층 패턴(Pattern)과 플러그(Plug)를 형성한 후 상기 제 2 금속층 패턴과 플러그를 하드 마스크(Hard mask)층으로 사용하여 하부 금속 배선을 형성하므로 소자의 수율 및 신뢰성을 향상시키는 금속배선 형성 방법에 관한 것이다.The present invention relates to a method for forming a metal wiring, and in particular, after forming a second metal layer pattern and a plug on a first metal layer for lower metal wiring, a hard mask is formed on the second metal layer pattern and the plug. The present invention relates to a metal wiring forming method for improving the yield and reliability of a device since the lower metal wiring is formed as a layer.
현재 반도체 칩(Chip) 제조 공정 중에서 다층 금속 배선 형성 시, RC 지연을 최소화시키기 위해 저 유전 상수 산화막을 사용하고 있다.Currently, when forming a multi-layer metal wiring in a semiconductor chip manufacturing process, a low dielectric constant oxide film is used to minimize the RC delay.
종래의 금속배선 형성 방법은 도 1a에서와 같이, 금속배선 콘택홀(도시하지 않음)을 갖는 절연 기판(11) 상에 제 1 Ti/TiN층(13), 알루미늄(Al)층(15), 제 2 Ti/TiN층(17) 및 제 1 감광막(18)을 순차적으로 형성한다.In the conventional method of forming metal wirings, as shown in FIG. 1A, the first Ti / TiN layer 13, the aluminum (Al) layer 15, and the like are formed on an insulating substrate 11 having metal wiring contact holes (not shown). The second Ti / TiN layer 17 and the first photosensitive film 18 are sequentially formed.
그리고, 상기 제 1 감광막(18)을 제 1 금속배선이 형성될 부위에만 남도록 선택 노광 및 현상한다.Then, the first photosensitive film 18 is selectively exposed and developed so that only the portion where the first metal wiring is to be formed remains.
여기서, 상기 제 1 감광막(18)의 노광 공정 시 고 에너지를 사용하기 때문에 상기 제 1 감광막(18) 패턴(Pattern)의 측면 부위가 축소된다.Here, since high energy is used in the exposure process of the first photoresist layer 18, the side portion of the pattern of the first photoresist layer 18 is reduced.
도 1b에서와 같이, 상기 선택적으로 노광 및 현상된 제 1 감광막(18)을 마스크로 상기 제 2 Ti/TiN층(17), 상기 알루미늄층(15) 및 제 1 Ti/TiN층(13)을 선택 식각하여 Ti/TiN/Al/Ti/TiN 적층 구조의 제 1 금속배선을 형성한 다음, 상기 제 1 감광막(18)을 제거한다.As shown in FIG. 1B, the second Ti / TiN layer 17, the aluminum layer 15, and the first Ti / TiN layer 13 may be formed using the selectively exposed and developed first photosensitive film 18 as a mask. Selectively etching to form a first metal wiring of the Ti / TiN / Al / Ti / TiN laminated structure, and then the first photosensitive film 18 is removed.
여기서, 상기 제 1 금속배선 형성 공정 시 상기 측면 부위가 축소된 제 1 감광막(18)을 마스크로 사용하기 때문에 상기 제 1 금속배선의 끝이 축소되는 배선 끝 축소 현상(A)이 발생된다.In this case, since the first photosensitive film 18 having the reduced side surface portion is used as a mask in the first metal wire forming process, a wire end reduction phenomenon A in which the end of the first metal wire is reduced occurs.
도 1c에서와 같이, 상기 제 1 금속배선을 포함한 절연 기판(11) 상에 저 유전 상수 산화막(19)을 회전 도포 방식으로 형성한다.As shown in FIG. 1C, a low dielectric constant oxide film 19 is formed on the insulating substrate 11 including the first metal wiring by a spin coating method.
그리고, 상기 저 유전 상수 산화막(19) 상에 산화막(21)을 형성하고, 화학적 기계 연마 방법을 사용하여 상기 산화막(21)을 평탄화한다.An oxide film 21 is formed on the low dielectric constant oxide film 19, and the oxide film 21 is planarized using a chemical mechanical polishing method.
여기서, 상기 저 유전 상수 산화막(19)을 회전 도포 방식으로 형성하기 때문에 상기 저 유전 상수 산화막(19)의 점착성으로 상기 각 제 1 금속배선 상에 동일한 두께로 형성되지 않는다. 즉, 상기 제 1 금속배선의 넓이 또는 밀도에 따라 다르게 형성되되, 상기 제 1 금속배선의 면적이 큰 경우가 작은 경우보다 두껍게 형성되고, 상기 제 1 금속배선의 밀도가 높은 지역이 낮은 지역보다 두껍게 형성된다.Here, since the low dielectric constant oxide film 19 is formed by a rotary coating method, the low dielectric constant oxide film 19 is not formed to the same thickness on each of the first metal wires due to the adhesion of the low dielectric constant oxide film 19. That is, it is formed differently according to the width or density of the first metal wiring, but the case where the area of the first metal wiring is large is formed thicker than the smaller one, and the region where the density of the first metal wiring is high is thicker than the low region. Is formed.
또한, 상기 저 유전 상수 산화막(19)은 산화막(21)보다 기계적, 화학적으로 약한 구조를 가진다.In addition, the low dielectric constant oxide film 19 has a structure mechanically and chemically weaker than the oxide film 21.
도 1d에서와 같이, 상기 평탄화된 산화막(21) 상에 제 2 감광막(23)을 도포하고, 상기 제 2 감광막(23)을 제 1 금속배선 상측의 비아홀이 형성될 부위에만 제거되도록 선택 노광 및 현상한다.As shown in FIG. 1D, the second photoresist layer 23 is coated on the planarized oxide layer 21, and the second photoresist layer 23 is selectively exposed so as to be removed only at a portion where the via hole above the first metal line is to be formed. Develop.
그리고, 상기 선택적으로 노광 및 현상된 제 2 감광막(23)을 마스크로 상기 산화막(21)과 저 유전 상수 산화막(19)을 선택 식각하여 비아홀(24)을 형성한다.The via hole 24 is formed by selectively etching the oxide film 21 and the low dielectric constant oxide film 19 using the selectively exposed and developed second photosensitive film 23 as a mask.
여기서 상기 비아홀(24) 형성 공정 시, 상기 저 유전 상수 산화막(19)의 비아홀(24)에 측면이 동그랗게 파이는 보우잉(Bowing) 현상(B)이 발생되거나, 상기 제 1 금속배선 측면 부위에 상기 저 유전 상수 산화막(19)이 깊고 날카롭게 패이는 현상(F)이 발생된다.Here, in the forming process of the via hole 24, a bowing phenomenon (B) in which a side is rounded in the via hole 24 of the low dielectric constant oxide film 19 is generated, or at the side of the first metal wiring side. A phenomenon (F) in which the low dielectric constant oxide film 19 is deep and sharply slit occurs.
상기 보우잉 현상(B)과 날카롭게 패이는 현상(F)은 상기 저 유전 상수 산화막(19)이 산화막(21)보다 식각 속도가 빠르기 때문에 발생된다.The bowing phenomenon (B) and the sharpening phenomenon (F) occur because the low dielectric constant oxide film 19 has a higher etching rate than the oxide film 21.
즉, 상기 비아홀(24) 형성을 위한 건식각 공정은 상기 비아홀(24)의 방향과 동일한 방향으로 즉 수직한 방향으로 진행되지만 산란에 의해 상기 비아홀(24)의 측면을 식각하기도 하기 때문에, 식각 속도가 빠른 저 유전 상수 산화막(19)이 산화막(21)보다 측면 방향으로 더 빨리 식각되어 보우잉 현상(B)이 발생되고, 또한 상기 비아홀(24)을 형성하기 위해 사용되는 과도 식각 공정 시 상기 저 유전 상수 산화막(19)이 산화막(21)보다 식각 속도가 빠르기 때문에 날카롭게 패이는 현상(F)이 발생된다.That is, the dry etching process for forming the via hole 24 proceeds in the same direction as the direction of the via hole 24, that is, in the vertical direction, but also etches the side surface of the via hole 24 by scattering, so that the etching speed is increased. The low dielectric constant oxide film 19 is faster in the lateral direction than the oxide film 21 to cause the bowing phenomenon (B), and the low dielectric constant oxide film 19 is also used in the transient etching process used to form the via hole 24. Since the dielectric constant oxide film 19 has a higher etching rate than the oxide film 21, a phenomenon (F) that sharply digs occurs.
도 1e에서와 같이, 상기 제 2 감광막(23)을 제거하고, 상기 비아홀을 포함한 전면에 제 3 Ti/TiN층(25)을 형성한다.As shown in FIG. 1E, the second photoresist layer 23 is removed, and a third Ti / TiN layer 25 is formed on the entire surface including the via hole.
여기서 상기 제 3 Ti/TiN층(25)의 형성 공정 시, 상기 보우잉 현상(B)이 발생된 부위에는 상기 제 3 Ti/TiN층(25)의 증착 불량(D)이 발생된다.Here, in the process of forming the third Ti / TiN layer 25, a deposition failure D of the third Ti / TiN layer 25 is generated at a portion where the bowing phenomenon B occurs.
도 1f에서와 같이, 상기 제 3 Ti/TiN층(25) 상에 제 2 금속배선층인 텅스텐(W)층을 형성하고, 화학적 기계 연마 방법에 의해 평탄화하여 플러그(27)를 형성한다.As shown in FIG. 1F, a tungsten (W) layer, which is a second metal wiring layer, is formed on the third Ti / TiN layer 25, and the plug 27 is formed by planarization by a chemical mechanical polishing method.
여기서, 상기 제 3 Ti/TiN층(25)이 비아홀 측벽을 따라 형성되어야만 상기 텅스텐층이 비아홀(24)을 매립하기 때문에, 상기 제 3 Ti/TiN층(25)의 증착 불량(D) 발생으로 상기 텅스텐층은 상기 비아홀(24)을 매립하지 못한 부위(H)가 발생한다.Here, since the tungsten layer fills the via hole 24 only when the third Ti / TiN layer 25 is formed along the sidewalls of the via hole, the deposition defect D of the third Ti / TiN layer 25 may occur. The tungsten layer may generate a portion H where the via hole 24 is not buried.
그리고, 상기 저 유전 상수 산화막(19)이 날카롭게 패이는 현상(F)이 발생된 부위에도 상기 텅스텐층이 증착되지 않을 수도 있다.The tungsten layer may not be deposited even at a portion where the phenomenon (F) in which the low dielectric constant oxide film 19 is sharply cut.
종래의 금속배선 형성 방법은 저 유전 상수 산화막과 산화막 적층 구조의 층간 절연막을 형성하고 비아홀을 형성하는 공정에 있어서, 다음과 같은 이유에 의해 소자의 수율 및 신뢰성이 저하되는 문제점이 있었다.The conventional metal wiring forming method has a problem in that the yield and reliability of the device are deteriorated in the process of forming an interlayer insulating film having a low dielectric constant oxide film and an oxide film stacked structure and forming a via hole.
첫째, 측면이 축소된 감광막 패턴을 마스크로 하부 금속 배선을 형성하기 때문에 발생된 배선 끝 축소 현상에 의해 하부 금속 배선과 플러그 사이의 전기적, 기계적 결합이 불안정하다.First, since the lower metal wiring is formed using the photosensitive film pattern having the reduced side surface, electrical and mechanical coupling between the lower metal wiring and the plug is unstable due to the wiring end reduction phenomenon.
둘째, 상기 저 유전 상수 산화막과 산화막 사이에 서로 상이한 증착 조건에 의해 물리적인 스트레스(Stress)를 받아 깨어짐이 발생된다.Second, cracking occurs due to physical stress caused by different deposition conditions between the low dielectric constant oxide film and the oxide film.
셋째, 상기 산화막에 의해 하부 금속 배선 사이의 캐패시턴스가 증가하여 하부 금속 배선에서 RC 지연 현상이 발생된다.Third, the capacitance between the lower metal lines is increased by the oxide film, so that an RC delay phenomenon occurs in the lower metal lines.
넷째, 상기 저 유전 상수 산화막의 점착성으로 그 증착 두께가 동일하지 않기 때문에 상기 비아홀 형성을 위한 저 유전 상수 산화막과 산화막의 건식각 공정 시 식각 조건에 대한 최적화가 어려워 보우잉 현상과 상기 저 유전 상수 산화막이 날카롭게 패이는 현상이 발생하므로 후속 공정에 있어서 Ti/TiN층의 증착 불량이 발생하고 배선 형성용 금속층으로부터 상기 비아홀의 매립 공정이 불량하게 진행된다.Fourth, since the deposition thickness is not the same due to the adhesion of the low dielectric constant oxide film, it is difficult to optimize the etching conditions during the dry etching process of the low dielectric constant oxide film and the oxide film for forming the via hole, so the bowing phenomenon and the low dielectric constant oxide film Since a sharp dent occurs, deposition failure of the Ti / TiN layer occurs in a subsequent step, and the via hole filling process proceeds poorly from the metal layer for wiring formation.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 하부 금속 배선용제 1 금속층 상에 제 2 금속층 패턴과 플러그를 형성한 후 상기 제 2 금속층 패턴과 플러그를 하드 마스크층으로 사용하여 하부 금속 배선을 형성하므로 배선 끝 축소 현상을 방지하고, 상기 제 2 금속층 패턴과 플러그를 형성한 후 저 유전 상수 산화막의 단일층인 층간 절연막을 형성하여 RC 지연을 방지하는 금속배선 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and after forming the second metal layer pattern and the plug on the lower metal wiring solvent 1 metal layer, the lower metal wiring is formed using the second metal layer pattern and the plug as a hard mask layer. Accordingly, an object of the present invention is to provide a method for forming a metal wiring, which prevents a wire end shrinkage phenomenon and prevents an RC delay by forming an interlayer insulating film, which is a single layer of a low dielectric constant oxide film, after forming the second metal layer pattern and the plug.
도 1a내지 도 1f는 종래 기술에 따른 금속배선 형성 방법을 나타낸 공정 단면도.1A to 1F are cross-sectional views illustrating a method of forming metal wirings according to the prior art.
도 2a내지 도 2g는 본 발명의 실시 예에 따른 금속배선 형성 방법을 나타낸 공정 단면도.2A to 2G are cross-sectional views illustrating a method of forming metal wirings according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11, 31 : 절연 기판 13, 33 : 제 1 Ti/TiN층11, 31: insulation substrate 13, 33: first Ti / TiN layer
15, 35 : 알루미늄층 17,37 : 제 2 Ti/TiN층15, 35: aluminum layer 17, 37: second Ti / TiN layer
18, 41 : 제 1 감광막 19, 53 : 저 유전 상수 산화막18, 41: first photosensitive film 19, 53: low dielectric constant oxide film
21, 43 : 산화막 23, 45 : 제 2 감광막21, 43: oxide film 23, 45: second photosensitive film
24, 47 : 비아홀 25, 49 : 제 3 Ti/TiN층24, 47: Via hole 25, 49: 3rd Ti / TiN layer
27, 51 : 플러그27, 51: plug
본 발명의 금속배선 형성 방법은 금속배선과 금속배선 콘택이 형성될 부위가 정의된 기판을 마련하는 단계, 상기 기판 상에 금속배선용 도전층과 제 2 도전층을 순차적으로 형성하는 단계, 상기 제 2 도전층을 금속배선이 형성될 부위에만 남도록 선택 식각하는 단계, 전면에 절연막을 형성하는 단계, 상기 금속배선 콘택이 형성될 부위의 절연막을 선택 식각하여 비아홀을 형성하는 단계, 상기 비아홀을 매립하는 플러그를 형성하는 단계, 상기 산화막을 전면 식각하여 상기 플러그 양측에 산화막 스페이서를 형성하는 단계, 상기 제 2 도전층과 산화막 스페이서를 마스크로 상기 금속배선용 도전층을 선택 식각하여 금속배선을 형성하는 단계 및 상부 구조물 상에 저 유전 상수 절연막을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.In the method of forming a metal wiring according to the present invention, the method includes: providing a substrate in which metal wiring and a region in which a metal wiring contact is to be formed are defined, sequentially forming a conductive layer for metal wiring and a second conductive layer on the substrate; Selectively etching the conductive layer so as to remain only in the portion where the metal wiring is to be formed, forming an insulating layer on the front surface, forming a via hole by selectively etching the insulating layer in the portion where the metal wiring contact is to be formed, and a plug filling the via hole Forming an oxide layer on both sides of the plug by etching the oxide layer on the entire surface, and selectively etching the conductive layer for metal wiring using the second conductive layer and the oxide spacer as a mask to form a metal wiring; and And forming a low dielectric constant insulating film on the structure.
상기와 같은 본 발명에 따른 금속배선 형성 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings a preferred embodiment of the metal wiring forming method according to the present invention as follows.
도 2a내지 도 2g는 본 발명의 실시 예에 따른 금속배선 형성 방법을 나타낸 공정 단면도이다.2A to 2G are cross-sectional views illustrating a method of forming metal wirings according to an embodiment of the present invention.
본 발명의 실시 예에 따른 금속배선 형성 방법은 도 2a에서와 같이, 금속배선 콘택홀(도시하지 않음)을 갖는 절연 기판(31) 상에 제 1 Ti/TiN층(33), 도전배선용 금속층인 알루미늄층(35), 제 2 Ti/TiN층(37), 하드마스크용 도전층인 제 1 텅스텐층(39) 및 제 1 감광막(41)을 순차적으로 형성한다.According to an embodiment of the present invention, the method for forming a metal wiring is a first Ti / TiN layer 33 and a metal layer for conductive wiring on an insulating substrate 31 having a metal wiring contact hole (not shown), as shown in FIG. 2A. An aluminum layer 35, a second Ti / TiN layer 37, a first tungsten layer 39 and a first photosensitive film 41, which are conductive layers for a hard mask, are sequentially formed.
그 후, 상기 제 1 감광막(41)을 제 1 금속배선이 형성될 부위에만 남도록 선택 노광 및 현상한다.Thereafter, the first photosensitive film 41 is selectively exposed and developed so that only the portion where the first metal wiring is to be formed remains.
여기서, 상기 제 1 텅스텐층(39)의 형성으로 상기 제 1 감광막(41)을 종래의 도전배선 식각용 마스크인 감광막 보다 얇게 도포하여 상기 제 1 감광막(41) 패턴의 측면 부위가 축소되는 현상을 방지한다.Here, the first tungsten layer (39) is formed by applying the first photoresist layer (41) thinner than the photoresist layer, which is a mask for etching conductive wiring, thereby reducing the side portion of the first photoresist layer (41) pattern. prevent.
도 2b에서와 같이, 상기 선택적으로 노광 및 현상된 제 1 감광막(41)을 마스크로 SF6를 활성화시킨 플라즈마를 사용하여 상기 제 1 텅스텐층(39)을 선택 식각한 다음, 상기 제 1 감광막(41)을 제거한다.상기 제1 텅스텐층(39)을 구리층으로 형성할 수도 있다.As shown in FIG. 2B, the first tungsten layer 39 is selectively etched using a plasma in which SF 6 is activated using the selectively exposed and developed first photoresist layer 41 as a mask, and then the first photoresist layer ( 41). The first tungsten layer 39 may be formed of a copper layer.
여기서, 상기 SF6를 활성화시킨 플라즈마에 대해 상기 제 2 Ti/TiN층(37)의 식각 속도가 낮기 때문에, 상기 제 1 텅스텐층(39)의 식각 공정 시 상기 제 2 Ti/TiN층(37)이 훼손되지 않는다.Here, since the etching rate of the second Ti / TiN layer 37 is low with respect to the plasma activating the SF 6 , the second Ti / TiN layer 37 during the etching process of the first tungsten layer 39. This is not compromised.
그리고, 상기 제 1 텅스텐층(39)을 포함한 전면에 산화막(43)을 형성하고, 화학적 기계 연마 방법을 사용하여 상기 산화막(43)을 평탄화한다.An oxide film 43 is formed on the entire surface including the first tungsten layer 39, and the oxide film 43 is planarized using a chemical mechanical polishing method.
도 2c에서와 같이, 상기 평탄화된 산화막(43) 상에 제 2 감광막(45)을 도포하고, 상기 제 2 감광막(45)을 비아홀이 형성될 부위에만 제거되도록 선택 노광 및 현상한다.As shown in FIG. 2C, a second photosensitive film 45 is coated on the planarized oxide film 43, and the second photosensitive film 45 is selectively exposed and developed to be removed only at a portion where a via hole is to be formed.
그리고, 상기 선택적으로 노광 및 현상된 제 2 감광막(45)을 마스크로 CxFy계열의 기체를 활성화시킨 플라즈마를 사용하여 상기 산화막(43)을 선택 식각하여 비아홀(47)을 형성한다.In addition, the via layer 47 is formed by selectively etching the oxide layer 43 using a plasma of activating a C x F y- based gas using the selectively exposed and developed second photoresist layer 45 as a mask.
여기서 상기 비아홀(47) 형성 공정 시, 상기 산화막(43)보다 상기 제 1 텅스텐층(39)과 제 2 Ti/TiN층(37)의 식각 속도가 낮기 때문에 과도 식각 공정을 진행하여도 종래와 같이 절연막이 날카롭게 패이는 현상이 발생되지 않는다. 또한, 저 유전 상수 산화막의 식각 공정이 없어 보우잉 현상도 발생되지 않는다.Here, since the etching rate of the first tungsten layer 39 and the second Ti / TiN layer 37 is lower than that of the oxide layer 43 in the process of forming the via hole 47, even if the excessive etching process is performed, as in the prior art. No sharpening of the insulating film occurs. In addition, there is no etching process of the low dielectric constant oxide film, so no bowing phenomenon occurs.
도 2d에서와 같이, 상기 제 2 감광막(45)을 제거하고, 상기 비아홀(47)을 포함한 전면에 제 3 Ti/TiN층(49)을 형성한다.As shown in FIG. 2D, the second photoresist layer 45 is removed and a third Ti / TiN layer 49 is formed on the entire surface including the via hole 47.
그리고, 상기 제 3 Ti/TiN층(49) 상에 제 2 금속배선층인 제 2 텅스텐(W)층을 형성하고, 화학적 기계 연마 방법에 의해 평탄화하여 플러그(51)를 형성한다.A second tungsten (W) layer, which is a second metal wiring layer, is formed on the third Ti / TiN layer 49, and the plug 51 is formed by planarization by a chemical mechanical polishing method.
도 2e에서와 같이, 상기 산화막(43)을 에치백(Etch back)하여 상기 플러그(51) 양측에 상기 산화막(43)으로 이루어진 스페이서(Spacer)(부호화 하지 않음)를 형성한다.As shown in FIG. 2E, the oxide layer 43 is etched back to form a spacer (not encoded) including the oxide layer 43 on both sides of the plug 51.
도 2f에서와 같이, 상기 제 1 텅스텐층(39)과 스페이서를 마스크로 Cl2+BCl3를 활성화시킨 플라즈마를 사용하여 상기 제 2 Ti/TiN층(37), 상기 알루미늄층(35) 및 제 1 Ti/TiN층(33)을 선택 식각하여 Ti/TiN/Al/Ti/TiN/W 적층 구조의 금속배선을 형성한다.As shown in FIG. 2F, the second Ti / TiN layer 37, the aluminum layer 35, and the first layer are formed using a plasma in which Cl 2 + BCl 3 is activated using the first tungsten layer 39 and a spacer as a mask. 1 Ti / TiN layer 33 is selectively etched to form a metal wiring having a Ti / TiN / Al / Ti / TiN / W stacked structure.
도 2g에서와 같이, 상기 금속배선을 포함한 전면에 저 유전 상수 산화막(53)을 회전 도포 방식으로 형성한다.As shown in Figure 2g, a low dielectric constant oxide film 53 is formed on the entire surface including the metal wiring by a rotation coating method.
그리고, 상기 플러그(51)를 식각 방지막으로 하는 화학적 기계 연마 방법에 의해 상기 저 유전 상수 산화막(53)을 전면 식각하여 평탄화한다.The low dielectric constant oxide film 53 is etched and planarized by a chemical mechanical polishing method using the plug 51 as an etch stop film.
여기서, 상기 저 유전 상수 산화막(53) 속에 포함되는 용매의 비율을 높여 점착성을 낮추고 유동성을 높여서 상기 저 유전 상수 산화막(53)을 형성한다.Here, the ratio of the solvent contained in the low dielectric constant oxide film 53 is increased to lower the adhesiveness and the fluidity is increased to form the low dielectric constant oxide film 53.
본 발명의 금속배선 형성 방법은 하부 금속 배선용 제 1 금속층 상에 제 2 금속층 패턴과 플러그를 형성한 후 상기 제 2 금속층 패턴과 플러그를 하드 마스크층으로 사용하여 하부 금속 배선을 형성하므로 배선 끝 축소 현상을 방지하고, 상기 제 2 금속층 패턴과 플러그를 형성한 후 저 유전 상수 산화막의 단일층인 층간 절연막을 형성하므로 RC 지연을 방지하여 소자의 수율 및 신뢰성을 향상시키는 효과가 있다.In the method for forming a metal wiring according to the present invention, since the second metal layer pattern and the plug are formed on the first metal layer for the lower metal wiring, the bottom metal wiring is formed by using the second metal layer pattern and the plug as a hard mask layer. After the formation of the second metal layer pattern and the plug, the interlayer insulating film, which is a single layer of the low dielectric constant oxide film, is formed, thereby preventing the RC delay, thereby improving the yield and reliability of the device.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960035800A (en) * | 1995-03-04 | 1996-10-28 | 김주용 | Contact formation method of semiconductor device |
| JPH10223854A (en) * | 1997-02-05 | 1998-08-21 | Hitachi Ltd | Method for manufacturing semiconductor integrated circuit device |
| JP2000082707A (en) * | 1998-09-04 | 2000-03-21 | Sony Corp | Manufacture of semiconductor device |
| KR20010051368A (en) * | 1999-11-02 | 2001-06-25 | 포만 제프리 엘 | Post metalization chem-mech polishing dielectric etch |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960035800A (en) * | 1995-03-04 | 1996-10-28 | 김주용 | Contact formation method of semiconductor device |
| JPH10223854A (en) * | 1997-02-05 | 1998-08-21 | Hitachi Ltd | Method for manufacturing semiconductor integrated circuit device |
| JP2000082707A (en) * | 1998-09-04 | 2000-03-21 | Sony Corp | Manufacture of semiconductor device |
| KR20010051368A (en) * | 1999-11-02 | 2001-06-25 | 포만 제프리 엘 | Post metalization chem-mech polishing dielectric etch |
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