KR100415095B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR100415095B1 KR100415095B1 KR1019960057814A KR19960057814A KR100415095B1 KR 100415095 B1 KR100415095 B1 KR 100415095B1 KR 1019960057814 A KR1019960057814 A KR 1019960057814A KR 19960057814 A KR19960057814 A KR 19960057814A KR 100415095 B1 KR100415095 B1 KR 100415095B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53219—Aluminium alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
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Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 금속 배선의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving the reliability of metal wiring.
일반적으로 알루미늄은 금속 배선 재료로서 양호한 특성을 가지고 있기 때문에 현재의 배선 공정시 가장 널리 사용되는 있는 금속이다. 즉, 알루미늄은 스퍼터링 방식으로 매우 쉽게 증착할 수 있을 뿐만 아니라, 전기 전도도가 우수하고, 실리콘 기판에 대한 높은 호환성과 가공의 용이성 및 하부층과의 양호한 접착성을 갖는다.In general, aluminum is the most widely used metal in current wiring processes because of its good properties as a metal wiring material. That is, aluminum can not only be deposited very easily by sputtering, but also has excellent electrical conductivity, high compatibility with silicon substrates, ease of processing, and good adhesion with underlying layers.
상기한 알루미늄을 이용한 금속 배선의 형성은 도시되지는 않았지만, 실리콘 기판 상에 절연막을 형성하고, 그 상부에 알루미늄막을 증착한 다음, 포토리소그라피 및 식각공정으로 알루미늄막을 패터닝하여 금속 배선층을 형성한다.Although the formation of the metal wiring using aluminum is not shown, an insulating film is formed on the silicon substrate, an aluminum film is deposited on the silicon substrate, and the aluminum film is patterned by photolithography and etching to form a metal wiring layer.
그러나, 상기한 알류미늄막을 이용한 금속 배선의 형성시 다음과 같은 문제가 발생한다.However, the following problem occurs when forming the metal wiring using the aluminum film described above.
첫째, 실리콘 기판이 고온에서 어닐링 될 때, 알루미늄에서의 실리콘의 높은 용해도와 확산계수 때문에 실리콘이 알루미늄막 속으로 확산되어 들어가는 알루미늄 스파이킹(spiking)이 발생한다. 또한, 확산된 실리콘 원자들은 냉각시 재결정층을 생성시켜 오믹 콘택(ohmic contact)을 형성하는데, 이러한 재결정층이 국부적으로 심하게 형성되면, PN 접합이 파괴되어 소자가 퇴화된다. 한편, 상기 알루미늄 스파이킹은 대부분 콘택홀의 가장자리나 결합 부위에서 발생되고, 알루미늄의 그레인 크기, 기판의 결정방향 및 콘택 부위에 연결되는 알루미늄의 양 등에 의해 좌우된다.First, when the silicon substrate is annealed at a high temperature, aluminum spiking occurs in which silicon diffuses into the aluminum film due to the high solubility and diffusion coefficient of silicon in aluminum. In addition, the diffused silicon atoms form a recrystallized layer upon cooling to form an ohmic contact. If such a recrystallized layer is locally severely formed, the PN junction is broken and the device degrades. On the other hand, the aluminum spiking occurs mostly at the edge of the contact hole or the bonding site, and depends on the grain size of the aluminum, the crystal direction of the substrate and the amount of aluminum connected to the contact site.
둘째, 실리콘 기판의 열팽창 계수는 3.3 ppm/℃이고, 알루미늄의 열팽창 계수는 23.6ppm/℃이기 때문에, 실리콘 기판과 증착된 알루미늄막 사이의 큰 열팽창 계수의 차이로 인하여 힐록(hillock) 현상이 발생한다. 이러한, 힐록은 약 400 내지 450℃의 얼로이 공정에서 발생되며, 튀어나오는 높이는 2㎛ 또는 그 이상이 되어 나중에 감광막을 이용한 마스크 패턴의 형성시, 감광막에 핀홀(pinhole)을 생성시켜, 결국 숏트를 일으킨다.Second, since the coefficient of thermal expansion of the silicon substrate is 3.3 ppm / 占 폚 and the coefficient of thermal expansion of aluminum is 23.6 ppm / 占 폚, the hillock phenomenon occurs due to the large difference in the coefficient of thermal expansion between the silicon substrate and the deposited aluminum film. . Such a hillock is generated in an alloy process of about 400 to 450 ° C., and the protruding height is 2 μm or more, and later, when the mask pattern is formed using the photoresist film, pinholes are formed in the photoresist film, thereby forming a short. Cause
셋째, 알루미늄 배선에 전류가 흐를 때 전도체 내에서 원자가 이동하는 전자이동(electromigration)이 발생한다. 그런데, 어떤 재료 내에서의 전자 또는 정공의 흐름은 운동량의 교환에 의하여 전도체내의 정지 상태에 있는 원자들에게 힘이 작용하여, 만일 원자가 적합한 위치에 있다면, 이 힘은 그 원자가 움직이기에 충분할 정도로 크다. 상기 알루미늄의 경우, 적합한 위치란 전자 또는 정공의 흐름으로부터 아래로 흐르는 베이컨트(vacant) 격자 위치이다. 이러한 위치는 격자내 또는 결정립의 표면에서 발견될 수 있는데, 전자이동의 결과 전극의 전위가 낮은 쪽은 보이드가 발생하고, 국부적인 전류 밀도가 증대하게 되어 단선이 발생된다.Third, electromigration occurs in which atoms move in the conductor when current flows through the aluminum wiring. By the way, the flow of electrons or holes in a material exerts a force on the atoms at rest in the conductor by the exchange of momentum, so that if the atom is in the proper position, the force is large enough for the atom to move. . In the case of aluminum, a suitable position is a vacant lattice position flowing down from the flow of electrons or holes. This position can be found in the lattice or on the surface of the grain. As a result of the electron transfer, the lower the potential of the electrode is voided, the local current density is increased, the disconnection occurs.
따라서, 상기한 문제점을 해결하기 위하여 종래에는 알루미늄막 대신에 Al+1%Si+0.5%Cu의 조성을 갖는 알루미늄 합금막을 사용하였다. 즉, 여기서 Si은 스파이킹 문제와 힐록 현상을 극복하기 위하여 첨가되고, Cu는 전자이동을 줄이기 위하여 첨가된다.Therefore, in order to solve the above problem, an aluminum alloy film having a composition of Al + 1% Si + 0.5% Cu is used instead of the aluminum film. That is, Si is added to overcome the spiking problem and hillock phenomenon, and Cu is added to reduce the electron transfer.
그러나, 반도체 장치의 급격한 집적도의 향상으로 인하여, 금속배선을 통하여 흐르는 단위 전류 밀도가 증가하여 표면에 대한 알루미늄 배선의 신뢰성이 큰문제로 대두되었다. 즉, 상기한 알루미늄 합금막을 이용한 금속 배선은 얕은 접합부에 대한 접촉의 신뢰성, 힐록으로 인한 배선간 단락, 전자 이동 또는 응력 이동으로 인한 배선 절단 등의 기존 문제점을 그대로 내포하고 있다.However, due to the rapid improvement in the degree of integration of the semiconductor device, the unit current density flowing through the metal wiring increases, and the reliability of the aluminum wiring on the surface has emerged as a big problem. That is, the metal wiring using the aluminum alloy film includes existing problems such as reliability of contact with a shallow joint, short circuit between wires due to hillock, and wire breakage due to electron movement or stress movement.
또한, 접촉의 신뢰성 문제를 해결하기 위하여 종래의 또다른 방법으로 실리콘 기판과 알루미늄막 배선 사이에 TiN과 같은 장벽 금속막을 삽입시키고 있으나, 이러한 TiN막이 알루미늄막에 의해 덮혀질 때 알루미늄의 그레인 크기가 감소하고전자 이동에 대한 저항을 감소시키는 문제가 발생하였다.In addition, in order to solve the problem of contact reliability, another conventional method inserts a barrier metal film such as TiN between the silicon substrate and the aluminum film wiring, but the grain size of the aluminum is reduced when the TiN film is covered by the aluminum film. There has been a problem of reducing the resistance to high electron transfer.
이에, 본 발명은 상기 종래 문제점을 해결하기 위하여 창출된 것으로서, Ti막 및 TiN막에 의한 장벽 금속막과, Al+1%Si+0.5%Cu 합금막, TiN막, Al+0.5%Cu 합금막을 이용하여 금속 배선의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems, and includes a barrier metal film made of a Ti film and a TiN film, an Al + 1% Si + 0.5% Cu alloy film, a TiN film, and an Al + 0.5% Cu alloy film. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can improve the reliability of the metal wiring.
도 1은 본 발명의 실시예에 따른 반도체 소자의 금속 배선의 제조 방법을 설명하기 위한 공정단면도.1 is a cross-sectional view for explaining a method for manufacturing a metal wiring of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1 : 실리콘 기판 2 : 절연막1 silicon substrate 2 insulating film
3 : 장벽 금속막 4,8 : Al + 1%Si + 0.5%Cu의 합금막3: barrier metal film 4,8: alloy film of Al + 1% Si + 0.5% Cu
5,7,9 : TiN막 6 : Al+0.5%Cu5,7,9 TiN film 6: Al + 0.5% Cu
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조 방법은 절연막이 형성된 반도체 기판 상에 장벽 금속막을 형성하는 단계; 장벽 금속막 상에 Al을 포함하고 Si과 Cu가 첨가된 제 1 합금막을 형성하는 단계; 제 1 합금막 상에 제 1 TiN막을 형성하는 단계; 제 1 TiN막 상에 상기 제 1 합금막에서 Si이 첨가되지 않은 제 2 합금막을 형성하는 동시에 상기 제 1TiN막과 상기 제 2합금막 사이의 계면에 제 1Ti-Al 화합물이 형성되는 단계; 제 2 합금막 상에 제 2 TiN막을 형성하는 단계; 제 2 TiN막 상에 Al을 포함하고 Si과 Cu가 첨가된 제 3 합금막을 형성하는 동시에 상기 제 2iN막과 상기 제 3합금막 사이의 계면에 제 2Ti-Al 화합물이 형성되는 단계; 제 3 합금막 상에 제 3 TiN막을 형성하는 단계;및 결과물을 식각하여 금속배선층을 형성하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a barrier metal film on a semiconductor substrate on which an insulating film is formed; Forming a first alloy film containing Al and adding Si and Cu on the barrier metal film; Forming a first TiN film on the first alloy film; Forming a second alloy film without Si added in the first alloy film on the first TiN film and simultaneously forming a first Ti-Al compound at an interface between the first TiN film and the second alloy film; Forming a second TiN film on the second alloy film; Forming a third alloy film containing Al and adding Si and Cu on the second TiN film and simultaneously forming a second Ti-Al compound at an interface between the second iN film and the third alloy film; Forming a third TiN film on the third alloy film; and etching the resultant to form a metal wiring layer.
이때, 상기 제 1 합금막은 Al + 1%Si + 0.5%Cu 합금막이고, 상기 제 2 합금막은 Al + 0.5%Cu 합금막이고, 상기 제 3 합금막은 Al + 1%Si + 0.5%Cu 합금막인 것을 특징으로 한다.At this time, the first alloy film is Al + 1% Si + 0.5% Cu alloy film, the second alloy film is Al + 0.5% Cu alloy film, the third alloy film is Al + 1% Si + 0.5% Cu alloy film It is characterized by that.
상기 구성으로 된 본 발명에 의하면, Al+0.5%Cu의 합금막 상부 및 하부에Al+1%Si+0.5%Cu의 합금막을 각각 형성함으로써, Al+0.5%Cu의 합금막의 표면이 쉽게 산화되는 것을 방지할 수 있다. 또한, 금속 배선층의 최상부층을 TiN막으로 형성하여 힐록의 발생을 방지할 수 있다.According to the present invention having the above structure, the Al + 1% Si + 0.5% Cu alloy film is formed on the upper and lower Al + 0.5% Cu alloy film, respectively, so that the surface of the Al + 0.5% Cu alloy film is easily oxidized. Can be prevented. In addition, the top layer of the metal wiring layer may be formed of a TiN film to prevent the occurrence of hillock.
[실시예]EXAMPLE
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 1은 본 발명의 실시예에 따른 반도체 소자의 금속 배선 구조를 나타낸 단면도이다.1 is a cross-sectional view illustrating a metal wiring structure of a semiconductor device according to an embodiment of the present invention.
도 1에 도시된 바와 같이, 실리콘 기판(1) 상에 절연막(2)을 형성한다. 이때, 도시되진 않았지만 실리콘 기판(1)은 필드 산화막, 게이트, 소오스/드레인 영역을 포함하고, 절연막(2)은 소정의 콘택홀을 구비한다.As shown in FIG. 1, the insulating film 2 is formed on the silicon substrate 1. At this time, although not shown, the silicon substrate 1 includes a field oxide film, a gate, and a source / drain region, and the insulating film 2 has a predetermined contact hole.
먼저, 절연막(2) 상에 약 200 내지 400Å 두께의 제 1 Ti막과, 약 500 내지1,000Å의 제 1 TiN막 및, 약 200 내지 400Å의 제 2 Ti막의 다층막으로 구성된 장벽 금속막(3)을 스퍼터링 방식으로 형성한다. 이때, 제 1 및 제 2 Ti막은 약 0.2내지 0.5kW의 전력과 1x 10-2Torr 이하의 압력에서 Ar 개스 분위기에서 각각 형성하고, 제 1 TiN막은 약 300 내지 400℃의 온도로 기판(1)을 가열하면서 약 0.2 내지 0.5kW의 전력과 1x 10-2Torr 이하의 압력에서 Ar : N2= 1 : 1의 비율을 갖는 혼합 개스 내에서 증착한다.First, a barrier metal film 3 composed of a multilayer film of a first Ti film having a thickness of about 200 to 400 GPa, a first TiN film of about 500 to 1,000 GPa, and a second Ti film of about 200 to 400 GPa on the insulating film 2. Is formed by sputtering. At this time, the first and second Ti films are respectively formed in an Ar gas atmosphere at a power of about 0.2 to 0.5 kW and a pressure of 1 × 10 −2 Torr or less, and the first TiN film is formed at a temperature of about 300 to 400 ° C. Is deposited in a mixed gas having a ratio of Ar: N 2 = 1: 1 at a power of about 0.2 to 0.5 kW and a pressure of 1 × 10 −2 Torr or less while heating.
이어서, 장벽 금속막(3) 상에 약 1,000 내지 1,500Å의 두께로 Al+1%Si+0.5%Cu의 제 1 합금막(4)을 약 100 내지 200Å의 저온에서 약 5 내지 10kW의 전력과 1x 10-2Torr 이하의 압력을 유지하면서 형성한다. 이때, 장벽 금속막(3)과 제 1합금막(4) 사이의 계면에 Ti-Al 화합물이 형성되는데, 이 화합물로 인하여 금속 배선이 기계적으로 거의 변형되지 않기 때문에 응력 이동에 대한 높은 저항성을 갖게 된다.Subsequently, the first alloy film 4 of Al + 1% Si + 0.5% Cu on the barrier metal film 3 with a thickness of about 1,000 to 1,500 kW was applied at a low temperature of about 100 to 200 kW and a power of about 5 to 10 kW. Form while maintaining a pressure of 1x 10 -2 Torr or less. At this time, a Ti-Al compound is formed at the interface between the barrier metal film 3 and the first alloy film 4, and since the metal wiring is hardly deformed mechanically due to the compound, it has high resistance to stress transfer. do.
그리고 나서, 제 1 합금막(4) 상에 약 200 내지 400Å의 두께로 제 2 TiN막(5)을 형성하고, 그 상부에 약 3,000 내지 5,000Å의 두께로 Al+0.5%Cu의 제 2 합금막(6)을 350 내지 500℃의 온도에서 약 5 내지 10kW의 전력과 1x 10-2Torr 이하의 압력을 유지하면서 형성한다. 이때, 제 2 TiN막(5)과 제 2 합금막(6) 사이의 계면에 Ti-Al 화합물이 형성되고, 특히 제 2 합금막(6)은 전자 이동에 대한 높은 저항성을 지닐 뿐만 아니라, Si 원자가 첨가되지 않았기 때문에 저항이 낮아지게 된다.Then, a second TiN film 5 is formed on the first alloy film 4 at a thickness of about 200 to 400 kPa, and a second alloy of Al + 0.5% Cu at a thickness of about 3,000 to 5,000 kPa thereon. The film 6 is formed at a temperature of 350 to 500 ° C. while maintaining a power of about 5 to 10 kW and a pressure of 1 × 10 −2 Torr or less. At this time, a Ti-Al compound is formed at the interface between the second TiN film 5 and the second alloy film 6, and in particular, the second alloy film 6 not only has high resistance to electron transfer, but also Si The resistance is lowered because no atoms are added.
그 후, 제 2 합금막(6) 상에 약 200 내지 400Å의 두께로 제 3 TiN막(7)을 형성하고, 그 상부에 약 1,000 내지 1,500Å 두께의 Al+1%Si+0.5%Cu의 제 3 합금막(8)과, 약 200 내지 400Å 두께의 제 4 TiN막(9)을 순차적으로 형성한다. 여기서, 제 3 합금막(8)은 상기 제 1 합금막(4)과 마찬가지로 약 100 내지 200℃의 저온에서 약 5 내지 10kW의 전력과 1x 10-2Torr 이하의 압력을 유지하면서 형성한다.Thereafter, a third TiN film 7 was formed on the second alloy film 6 to a thickness of about 200 to 400 mW, and on the top thereof, an Al + 1% Si + 0.5% Cu of about 1,000 to 1,500 mW thick. The third alloy film 8 and the fourth TiN film 9 having a thickness of about 200 to 400 GPa are sequentially formed. Here, like the first alloy film 4, the third alloy film 8 is formed at a low temperature of about 100 to 200 ° C. while maintaining a power of about 5 to 10 kW and a pressure of 1 × 10 −2 Torr or less.
이어서, 도시되지는 않았지만, 포토리소그라피 및 식각 공정으로 절연막(2)상부의 금속층들을 패터닝하여 금속 배선층을 형성한다.Subsequently, although not shown, metal layers on the insulating film 2 are patterned by photolithography and etching to form a metal wiring layer.
상기 실시예에 의하면, Al+0.5%Cu의 합금막 상부 및 하부에 Al+1%Si+0.5%Cu의 합금막을 각각 형성함으로써, Al+0.5%Cu의 합금막의 표면이 쉽게 산화되는 것을 방지할 수 있다. 또한, 금속 배선층의 최상부층을 TiN막으로 형성하여 힐록의 발생을 방지함으로써, 전자이동 및 응력 이동에 대하여 높은 저항을 가지면서 얕은 콘택부에 대한 신뢰성이 있는 콘택을 형성할 수 있다. 따라서, 소자의 배선 신뢰성을 향상시킬 수 있게 된다.According to the above embodiment, the Al + 1% Si + 0.5% Cu alloy films are formed on the upper and lower Al + 0.5% Cu alloy films, respectively, to prevent the surface of the Al + 0.5% Cu alloy film from easily oxidizing. Can be. In addition, by forming the uppermost layer of the metal wiring layer with a TiN film to prevent the occurrence of hillock, it is possible to form a reliable contact to the shallow contact portion while having high resistance to electron movement and stress movement. Therefore, the wiring reliability of the element can be improved.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
이상 설명한 바와 같이 본 발명에 의하면, 금속 배선의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조방법을 실현할 수 있게 된다.As described above, according to the present invention, it is possible to realize a method for manufacturing a semiconductor element which can improve the reliability of metal wiring.
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| JPH08236707A (en) * | 1994-12-29 | 1996-09-13 | At & T Ipm Corp | Multi-layer Al alloy structure for metal conductors |
| KR100305208B1 (en) * | 1994-09-27 | 2001-12-01 | 박종섭 | Method for forming metal line of semiconductor device |
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| JPH08236707A (en) * | 1994-12-29 | 1996-09-13 | At & T Ipm Corp | Multi-layer Al alloy structure for metal conductors |
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