KR100446275B1 - Power factor correction circuit and method for correcting power factor, especially using an adder instead of a multiplier - Google Patents

Abstract

PURPOSE: A power factor correction circuit and a method for correcting the power factor are provided to reduce the manufacturing cost by performing the power factor using the adder without a conventional multiplier. CONSTITUTION: A power factor correction circuit(101) includes an error amplifier(111), a pulse width comparator(113), an adder(115), an oscillator(117) and a flip-flop(119). The power factor correction circuit(101) is connected to the boost converter(103). The oscillator generates the inverse saw tooth wave and the clock signal. The adder adds the inverse saw tooth wave and the input voltage inputted from outside. The error amplifier compares the feedback voltage inputted from outside with the reference voltage to generate the error voltage. And, the flip-flop controls the on/off of the power switch in response to the clock signal and the output of the comparator.

Description

Power factor correction circuit and power factor correction method

The present invention relates to a power factor correction circuit and a power factor correction method, and more particularly, to a power factor correction circuit and a power factor correction method for a boost converter.

The power factor correction circuit, which was originally developed, compensates for the power factor using three pieces of information: input voltage, input current and output voltage. The power factor correction circuit using the above three informations has not only applied to a complicated application circuit and a factor of increasing the cost of the product but also a result of lowering reliability. Therefore, the power factor correction circuit of the new control method is designed to perform power factor correction using only two pieces of information among the three pieces of information. A conventional power factor correction circuit using a multiplier is shown in FIG.

Referring to FIG. 1, a conventional power factor correction circuit 1 includes a multiplier 13, an error amplifier 11, a current sense comparator 15, a zero current detector 17, and a leading edge blanking unit. 19, an AND gate 21, an RS flip-flop 27, a timer 25, and an OR gate 29 are provided. A boost converter 3 is connected to the power factor correction circuit 1.

The error amplifier 11 compares the feedback voltage Vfb with the output voltage Vo of the boost converter 3 divided by the resistors 31 and 33 and the reference voltage Vref. It outputs as an output voltage Vm2.

The multiplier 13 multiplies the line voltage V1 generated at the input of the boost converter 3 by the voltage divided by the resistors 35 and 37 and the output voltage Vm2 of the error amplifier 11. This is then amplified by the gain of the multiplier 13 and then generated as an output voltage Vm0.

The current sense comparator 15 senses the current flowing in the source of the power device 5, for example the N-channel field effect transistor 5, used in the boost converter 3. That is, the current flowing through the source of the N-channel field effect transistor is generated as a voltage by the resistor 39. The current sensing comparator 15 compares the voltage generated across the resistor 39 with the output voltage Vm0 of the multiplier 13, and the voltage generated across the resistor 39 is equal to the multiplier 13. When the output voltage Vm0 is higher than the output voltage Vm0, the logic high level signal is generated. When the voltage generated across the resistor 39 is lower than the output voltage Vm0 of the multiplier 13, the logic low. Generates a level signal. A zener diode 41 is connected to the output terminal of the multiplier 13 to limit the output of the multiplier 13 from exceeding a predetermined voltage.

The zero current detector 17 detects a current flowing through the inductor 7 used in the boost converter 3 through the resistor 43.

The leading edge blanking unit 19 receives the output of the zero current detector 17 as an input and transmits the output to the AND gate 21. The leading edge blanking unit 19 removes noise generated in the N-channel field effect transistor 5.

The AND gate 21 performs an AND operation on the output of the leading edge blanking unit 19 and the output of the current sense comparator 15, and outputs the output to the set terminal S of the RS flip-flop 27. To pass.

An inverter 23 is connected to the output terminal of the zero current comparator 17 to invert the output of the zero current comparator 17 and transmit the inverted output to the reset terminal R of the RS flip-flop 27.

)은 다음 표 1과 같다.The RS flip-flop 27 takes an output of the AND gate 21 and an output of the inverter 23 as an input and outputs the

) Is shown in Table 1 below.

input Print R S

L L

L H L H L H H H Heartless

)의 값은 상기 RS 플립플롭(27)의 리셋 단자(R)에 인가되는 신호만 논리 하이(H)이면 논리 하이(H)가 되고, 상기 RS 플립플롭(27)의 셋 단자(S)에 인가되는 신호만 논리 하이(H)이면 논리 로우(L)가 된다. 즉, 상기 앤드 게이트(21)의 출력이 논리 하이(H)이고 상기 인버터(23)의 출력이 논리 로우(L)이면 상기 RS 플립플롭(27)의 출력(

)은 논리 로우(L)가 되고, 상기 앤드 게이트(21)의 출력이 논리 로우(L)이고 상기 인버터(23)의 출력이 논리 하이(H)이면 상기 RS 플립플롭(27)의 출력(

)은 논리 하이(H)가 된다.As shown in Table 1, the output of the RS flip-flop 27 (

) Is a logic high (H) if only the signal applied to the reset terminal (R) of the RS flip-flop (27) is a logic high (H), the set terminal (S) of the RS flip-flop 27 If only the applied signal is logic high (H), it becomes a logic low (L). That is, when the output of the AND gate 21 is logic high (H) and the output of the inverter 23 is logic low (L), the output of the RS flip-flop 27 (

) Becomes a logic low (L), the output of the RS flip-flop (27) if the output of the AND gate 21 is a logic low (L) and the output of the inverter 23 is a logic high (H).

) Becomes logic high (H).

The timer 25 is connected between the output terminal of the inverter 23 and the output terminal of the RS flip-flop 27.

The NOR gate 29 logically combines the output of the zero current detector 17 and the output of the RS flip-flop 27.

The N-channel field effect transistor 5 is turned on when the output of the noah gate 29 is logic high. The N-channel field effect transistor 5 is turned on when the output of the noah gate 29 is logic low. ) Is turned off. Depending on whether the N-channel field effect transistor 5 is turned on or off, the output voltage of the boost converter 3 decreases or increases.

As described above, the conventional power factor correction circuit 1 uses only two pieces of information of an input voltage, that is, a line voltage Vl and an output voltage, that is, a feedback voltage Vfb, and passes the two pieces of information through the multiplier 13. By controlling the power factor of the boost converter (3). When the multiplier 13 is used in the power factor correction circuit 1, the input voltage range and the gain of the multiplier 13 are closely related to each other, and when the designer makes a mistake in the design of the multiplier 13, the boost converter ( 3) the operating range is greatly limited.

Accordingly, an object of the present invention is to provide a power factor correction circuit using two magnetic information but not using a multiplier.

Another object of the present invention is to provide a power factor correction method suitable for the power factor correction circuit.

1 is a circuit diagram of a conventional Power Factor Correction circuit and a boost converter connected thereto.

2 is a circuit diagram of a power factor correction circuit and a boost converter connected thereto according to a preferred embodiment of the present invention.

3 is a diagram illustrating a simulation result of the power factor correction circuit shown in FIG. 2.

4 is a waveform diagram showing a simulation result of an input voltage and an input current of the boost converter shown in FIG. 2;

5 is a flowchart illustrating a power factor correction method according to the present invention.

To achieve the above technical problem, the present invention relates to a power switch, an oscillator for generating a reverse sawtooth signal and a clock signal, an adder for adding the reverse sawtooth signal and an input voltage input from the outside, and a feedback voltage input from the outside. An error amplifier for generating an error voltage compared to a voltage, a comparator for comparing the output of the adder and the error voltage, and a flip-flop for controlling the on / off of the power switch in response to the output of the clock signal and the comparator. Provided is a power factor correction circuit.

Advantageously, said power switch is an N-channel field effect transistor, said comparator is a pulse width modulation comparator, and said flip-flop is an RS flip-flop.

Also preferably, the error amplifier includes a capacitor between the inverting input terminal and the output terminal so that the voltage generated at the output terminal is changed linearly.

In accordance with another aspect of the present invention, there is provided a power factor correction method of a power factor correction circuit for controlling on and off of a power switch, the method comprising: generating a reverse sawtooth wave signal and a clock signal, an input voltage input from an external source, and the reverse An external signal detection step of adding the sawtooth signals to generate a sum signal, comparing a feedback voltage fed back from the outside with a reference voltage, and generating the result as an error voltage; comparing the sum signal with the error voltage and comparing the result A comparison step occurring as a signal and turning on the power switch if the clock signal is logic high and the comparison signal is logic low, and turning off the power switch if the clock signal is logic low and the comparison signal is logic high Provided is a power factor correction method having a latch step.

According to the present invention, the power factor correction circuit has a simple circuit and reduces manufacturing costs.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of a power factor correction circuit and a boost converter connected thereto according to a preferred embodiment of the present invention. 2, a power factor correction circuit 101 according to a preferred embodiment of the present invention includes an error amplifier 111, a pulse width modulation comparator 113, an adder 115, an oscillator 117, and a flip-flop 119. It is provided. A boost converter 103 is connected to the power factor correction circuit 101.

The boost converter 103 includes an input unit 141, first and second resistors 135 and 137, an inductor 107, a power switch 105, an output unit 143, a load 145, and a third and a third source. 4 resistors 131 and 133. The first resistor 135 and the second resistor 137 are connected to each other through the node N1, and the third resistor 131 and the fourth resistor 133 are connected to each other through the node N2. have. An N-channel field effect transistor is used as the power switch 105.

The error amplifier 111 compares the voltage generated at the node N2 with the reference voltage Vref and outputs the result as the error voltage Ve. That is, when the voltage generated at the node N2 is higher than the reference voltage Vref, the error voltage Ve decreases to a logic low level, and the voltage generated at the node N2 is the reference voltage Vref. If lower than), the error voltage Ve increases to a logic high level. The voltage generated at the node N2 is input to the inverting terminal (−) of the error amplifier 111, and the reference voltage Vref is input to the non-inverting terminal (+) of the error amplifier 111. A compensation capacitor 121 is connected between the inverting terminal (-) of the error amplifier 111 and the output terminal of the error amplifier 111, thereby integrating the voltage generated at the node N2 to thereby integrate the error amplifier 111. The error voltage Ve changes linearly by passing it to the output terminal. The voltage generated at the node N2 is a voltage in which the voltage Vo across the load 145 is divided by the ratio of the third and fourth resistors 131 and 133.

The oscillator 117 generates a reverse sawtooth wave signal Vs having a constant period and a clock signal CK having a constant period.

The adder 115 inputs the voltage generated at the node N1 and the reverse sawtooth wave signal Vs output from the oscillator 117, and the voltage generated at the node N1 and the reverse sawtooth wave signal ( Sum Vs) together. The voltage generated at the node N1 is a voltage in which the line voltage V1 output from the input unit is divided by the ratio of the first resistor 135 and the second resistor 137. The adder 115 may be replaced with a subtractor.

The pulse width modulation comparator 113 compares the output of the adder 115 and the error voltage Ve that is the output of the error amplifier 111 with each other and outputs the result as a logic high or logic low level signal. That is, when the output of the adder 115 has a higher voltage level than the error voltage Ve, the pulse width modulation comparator 113 outputs a logic high level signal, and the output of the adder 115 is If the voltage level is lower than the error voltage Ve, the pulse width modulation comparator 113 outputs a signal having a logic low level. The output of the adder 115 is applied to the non-inverting terminal (+) of the pulse width modulation comparator 113, and the error voltage Ve is applied to the inverting terminal (-) of the pulse width modulation comparator 113. do.

The flip-flop 119 is configured as an RS flip-flop. The RS flip-flop 119 inputs a clock signal CK and an output of the pulse width modulation comparator 113 among the output signals of the oscillator 117 and outputs the result of the N-channel field effect transistor 105. Pass to the gate of. The truth value of the RS flip-flop is shown in Table 2 below.

input Print R S Q (n) L L Q (n-1) L H H H L L H H Heartless

As shown in Table 2, when the value of the output Q of the RS flip-flop 119 is a logic high H, only a signal applied to the set terminal S of the RS flip-flop 119 is logic high (H). If only the signal applied to the reset terminal (R) of the RS flip-flop 119 is a logic high (H), the logic low (L). That is, when the clock signal CK is a logic high H and the output of the pulse width modulation comparator 113 is a logic low L, the output Q of the RS flip-flop 119 is a logic high H. When the clock signal CK is a logic low L and the output of the pulse width modulation comparator 113 is a logic high H, the output Q of the RS flip-flop 119 is a logic low L. )

If the output of the RS flip-flop 119 is logic high (H), the N-channel field effect transistor 105 is turned on, and if the output of the RS flip-flop 119 is logic low (L), the N-channel field effect Transistor 105 is turned off.

FIG. 3 is a diagram illustrating a simulation result of the power factor correction circuit 101 shown in FIG. 2. Referring to FIG. 3, when the line voltage V1 increases, the output signal 51 of the adder 115 increases. The error voltage Ve which is an output signal of the error amplifier 111 swings between an upper limit voltage Ve and a lower limit voltage Vel. When the voltage level of the output signal 51 of the adder 115 increases, the duty ratio of the switching frequency of the boost converter 103 increases, and the voltage of the output signal 51 of the adder 115 increases. As the level decreases, the duty ratio of the switching frequency also decreases. The fertilization rate is represented by Equation 1 below.

T denotes a period of one cycle of the switching frequency, and t1 and t2 denote turn-on times of the N-channel field effect transistor 105. When the output of the adder 115 is higher than the upper limit voltage Ve of the error voltage Ve, the switching frequency becomes logic high for t1, and the output of the adder 115 is the lower limit of the error voltage Ve. When higher than the voltage Vel, the switching frequency goes to logic high for t2. Therefore, when the error voltage Ve increases to the upper limit voltage Ve when the voltage level of the output signal 51 of the adder 115 increases, the ratio of the switching frequency decreases and the adder 115 decreases. When the voltage level of the output signal 53 increases, the error rate Ve decreases to the lower limit voltage Vel.

∼

)만큼 낮게 설정되어있다.In FIG. 3, for convenience of understanding, the switching frequency is higher than the actual value (

To

Is set as low as

The operation of the power factor correction circuit 101 according to the preferred embodiment of the present invention shown in FIG. 2 will be described with reference to FIG. 3.

First, the case where the line voltage V1 increases will be described. When the line voltage V1 increases, the voltage of the node N2 increases. When the voltage of the node N1 increases, the voltage level of the output signal of the adder 115 increases as shown in FIG. 3. The output signal of the adder 115 is a sum of the voltage of the node N1 and the inverse sawtooth wave signal Vs generated from the oscillator 117. When the voltage level of the output signal of the adder 115 increases, the output signal of the pulse width modulation comparator 113 becomes logic high. At this time, the error voltage Ve of the error amplifier 111_ remains constant. If the output of the pulse width modulation comparator 113 is logic high, the output of the RS flip-flop 119 is logic low. If the output of the RS flip-flop 119 is a logic low, the N-channel field effect transistor 105 is turned off, thereby increasing the voltage generated at the node N2. When the generated voltage increases, the error voltage Ve decreases to the lower limit voltage Vel shown in Fig. 3. In contrast, when the line voltage Ve decreases, the error voltage Ve is shown in FIG. Since the increase in the upper limit voltage (Veh), the ratio of the boost converter 103 is kept constant.

Next, the case where the load 145 becomes large will be described. As the load 145 increases, the voltage of the node N2 increases. When the voltage of the node N2 increases, the error voltage Ve decreases to the lower limit voltage Ve shown in FIG. 3. When the error voltage Ve decreases, the output signal of the pulse width modulation comparator 113 becomes logic high. At this time, the output signal of the adder 115 is maintained at a constant voltage level. Since the output of the pulse width modulation comparator 113 is logic high, the output of the RS flip-flop 119 is logic low, and the N-channel field effect transistor 105 is turned off. Therefore, since the rate of application of the switching frequency is reduced, a lot of power is transferred from the input unit 141 to the output unit 143 so that the load 145 is supplied with as much power as it is increased.

On the contrary, when the load 145 becomes small, the voltage of the node N2 decreases, and thus the error voltage Ve increases to the upper limit voltage Ve shown in FIG. 3. The output of the pulse width modulation comparator 113 then becomes logic low. Whenever the clock signal CK is activated to logic high while the output of the pulse width modulation comparator 113 is logic low, the RS flip-flop 119 is set to set the N-channel field effect transistor ( Turn on 105). Therefore, the rate increases, so that less power is supplied from the input unit 141 to the output unit 143 so that the load 145 is supplied with less power.

As described above, the power factor correction circuit 101 shown in FIG. 2 uses only two pieces of information of the line voltage V1, that is, the input voltage and the output voltage Vo, without using the current flowing through the N-channel field effect transistor 105. Performs power factor correction.

FIG. 4 is a waveform diagram illustrating a simulation result of the input voltage Vi and the input current of the boost converter 103 shown in FIG. 2. Referring to FIG. 4, the input voltage Vi and the input current 71 are in phase with each other, and the input current 71 follows the input voltage Vi. Accordingly, it can be seen that the power factor correction circuit 101 according to the preferred embodiment of the present invention normally performs power factor correction.

5 is a flowchart illustrating a power factor correction method according to the present invention. Referring to FIG. 5, a power factor correction method of a power factor correction circuit for controlling on / off of a power switch may include generating an inverse sawtooth wave signal and a clock signal 201, an external signal detection step 211, a comparison step 221, and the like. A latch step 231 is provided.

In step 201 of generating the reverse sawtooth wave signal and the clock signal, the reverse sawtooth wave signal and the clock signal are generated.

In the external signal detecting step 211, a sum signal obtained by adding an input voltage input from the outside and the reverse sawtooth wave signal is generated, and a feedback voltage fed back from the outside is compared with a reference voltage having a predetermined voltage and compared therewith Is generated as the error voltage. That is, when the voltage level of the sum signal is higher than the reference voltage, the error voltage becomes logic low, and when the voltage level of the sum signal is lower than the reference voltage, the error voltage becomes logic high.

In the comparing step 221, the sum signal and the error voltage are compared and the result is generated as a comparison signal. That is, when the voltage level of the sum signal is higher than the error voltage, the comparison voltage becomes logic high, and when the voltage level of the sum signal is lower than the error voltage, the comparison signal becomes logic low.

In the latch step 231, the power switch is turned on when the clock signal is logic high and the comparison signal is logic low, and the power switch is turned off when the clock signal is logic low and the comparison signal is logic high.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

As described above, the power factor correction circuit according to the present invention performs power factor correction using an adder (115 in FIG. 2) without using a multiplier (13 in FIG. 1), thereby simplifying the circuit configuration and reducing the manufacturing cost.

Claims (6)

Power switch; An oscillator for generating an inverse sawtooth signal and a clock signal; An adder for adding the reverse sawtooth wave signal and an input voltage input from the outside; An error amplifier generating an error voltage by comparing a feedback voltage input from an external device with a reference voltage; A comparator for comparing the output of the adder and the error voltage; And And a flip-flop for controlling the on / off of the power switch in response to the clock signal and the output of the comparator. The power factor correction circuit of claim 1, wherein the power switch is an N-channel field effect transistor. 2. The power factor correction circuit of claim 1, wherein the comparator is a pulse width modulation comparator. The power factor correction circuit of claim 1, wherein the flip-flop is an RS flip-flop. The power factor correction circuit of claim 1, wherein the error amplifier includes a capacitor between an inverting input terminal and an output terminal to linearly change a voltage generated at the output terminal. A power factor correction method of a power factor correction circuit for controlling on and off of a power switch, Generating an inverse sawtooth wave signal and a clock signal; An external signal detection step of generating a sum signal by adding the input voltage input from the outside and the reverse sawtooth signal, comparing the feedback voltage fed back from the outside with a reference voltage, and generating the result as an error voltage; A comparison step of comparing the sum signal with the error voltage and generating a result as a comparison signal; And And a latch step of turning on the power switch if the clock signal is logic high and the comparison signal is logic low, and turning off the power switch if the clock signal is logic low and the comparison signal is logic high. Power factor compensation method.

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