KR100440077B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR100440077B1 KR100440077B1 KR10-1999-0061867A KR19990061867A KR100440077B1 KR 100440077 B1 KR100440077 B1 KR 100440077B1 KR 19990061867 A KR19990061867 A KR 19990061867A KR 100440077 B1 KR100440077 B1 KR 100440077B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
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- Condensed Matter Physics & Semiconductors (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
본 발명은 플러그(Plug)층 형성용인 다결정 실리콘층을 워드 라인(Word Line) 네가티브(Negative) 감광막을 마스크로 식각한 후, 워드 라인 상부 부위의 질화막을 에치-스톱퍼(Etch-stopper)로 층간 절연막인 산화막과 상기 다결정 실리콘층을 평탄화 시켜 플러그층을 형성하므로 소자의 수율을 향상시키기 위한 반도체 소자의 제조 방법에 관한 것이다.According to the present invention, a polycrystalline silicon layer for forming a plug layer is etched with a word line negative photoresist film as a mask, and then an nitride layer of an upper portion of the word line is etched with an etch-stopper. Since the plug layer is formed by planarizing the phosphor oxide film and the polycrystalline silicon layer, the present invention relates to a method of manufacturing a semiconductor device for improving the yield of the device.
본 발명의 반도체 소자의 제조 방법은 평탄화된 층간 절연막상에 형성한 플러그층 형성용인 다결정 실리콘층을 층간 절연막을 에치-스톱퍼로 제 1 차 평탄화 시키고 워드 라인 네가티브 감광막을 마스크로 제 2 차 식각한 후, 워드 라인 상부 부위의 하드 마스크층을 에치-스톱퍼로 제 3 차 평탄화 시켜 플러그층을 형성하므로, 상기 하드 마스크층이 손상되지 않고 플러그층간의 절연이 이루어지지 않아 발생되는 전기적 쇼트를 방지하여 소자의 수율을 향상시키는 특징이 있다.In the method of manufacturing a semiconductor device of the present invention, the polycrystalline silicon layer for forming a plug layer formed on the planarized interlayer insulating film is first planarized using an etch-stopper, and the second line is etched using a word line negative photoresist film as a mask. Since the hard mask layer of the upper portion of the word line is thirdly planarized with an etch-stopper to form a plug layer, the hard mask layer is not damaged and insulation between the plug layers is not formed to prevent electrical shorts. There is a characteristic to improve the yield.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 워드 라인(Word Line) 네가티브(Negative) 감광막을 사용하여 워드 라인 상측 부위의 플러그(Plug)형성용 도전층을 미리 식각하므로 소자의 수율을 향상시키는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, by using a word line negative photosensitive film to etch a conductive layer for forming a plug in an upper portion of a word line in advance to improve the yield of the device. A method for manufacturing a semiconductor device.
도 1은 일반적인 워드라인 및 T-타입 활성영역을 나타낸 레이아웃도이고, 도 2a 내지 도 2f는 도 1의 Ⅰ∼Ⅰ선상의 종래 기술에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도이다.1 is a layout diagram illustrating a general word line and a T-type active region, and FIGS. 2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art on lines I to I of FIG. 1.
비트 라인(Bit Line) 콘택과 스토리지 노드(Storage Node) 콘택을 형성할 때, 원형의 콘택홀은 리소그래피(Lithography) 공정의 미스얼라인먼트(Misalignment)로 인하여 콘택 영역의 확보에 문제가 있으므로 디자인 룰(Deign Rule)이 좁아짐에 따라 소자 제조에 한계가 있다.When forming a bit line contact and a storage node contact, the circular contact hole has a problem in securing the contact area due to misalignment of the lithography process. As the rule becomes narrower, there is a limit in device fabrication.
상기 문제점을 극복하기 위하여 도 1에서와 같이, 서로 격리되며 일 방향으로 배열된 다수개의 워드 라인(W)들과 상기 두 개의 워드 라인(W) 하측 부위 마다 일 방향으로 배열되어 위치한 다수개의 T-타입(type) 활성영역(T)이 형성된 상태에서 그 상측에 T-타입 플러그 색(Plug Sac) 마스크로 층간 절연막을 식각한 후 다결정 실리콘층을 증착하고 평탄화 하여 플러그층을 형성하는 기술이 제안되었다.In order to overcome the above problem, as shown in FIG. 1, a plurality of word lines W separated from each other and arranged in one direction and a plurality of T-s arranged in one direction for each lower portion of the two word lines W are disposed. A technique for forming a plug layer by etching an interlayer insulating film with a T-type Plug Sac mask on top of a type active region T and then depositing and planarizing a polycrystalline silicon layer has been proposed. .
상기 기술을 사용할 경우 비트 라인 콘택홀과 스토리지 노드 콘택홀을 동시에 형성할 수 있는 넓은 영역을 이용함으로써 리소그래피 공정 및 식각 공정에서 보다 넓은 마진(Magin)을 확보할 수 있다.In the above technique, a wider margin for forming a bit line contact hole and a storage node contact hole at the same time enables a wider margin in a lithography process and an etching process.
상기 T-타입 플러그 색 대신에 I-타입 플러그 색 마스크를 사용할 수 있다.An I-type plug color mask may be used instead of the T-type plug color.
종래의 반도체 소자의 제조 방법은 도 2a에서와 같이 디램(DRAM) 셀(Cell)의 비트 라인 및 스토리지 노드 전극의 플러그층 형성 방법으로, 불순물 영역을 포함한 반도체 기판(11)상에 게이트 산화막(12)이 내재되며 상부 부위에 하드 마스크(Hard Mask)로 제 1 질화막(13)이 그리고 양측에 제 2 질화막 측벽(14)이 형성된 워드 라인(W)들을 형성한다.A conventional method of manufacturing a semiconductor device is a method of forming a plug layer of a DRAM cell and a bit line of a storage node electrode, as shown in FIG. 2A. The gate oxide film 12 is formed on a semiconductor substrate 11 including impurity regions. ) And the word lines W having the first nitride layer 13 formed on the upper portion and the second nitride layer sidewall 14 formed on both sides.
도 2b에서와 같이, 상기 워드 라인(W)들을 포함한 전면에 층간 절연막으로 산화막(16)을 형성한 다음, 상기 산화막(16)을 평탄화 시킨다.As shown in FIG. 2B, the oxide layer 16 is formed of an interlayer insulating layer on the entire surface including the word lines W, and then the oxide layer 16 is planarized.
도 2c에서와 같이, 상기 산화막(16)상에 감광막(37)을 도포한 후, 상기 감광막(17)을 T-타입(T-type)의 콘택 플러그용 자기정렬 콘택(self aling contact: SAC)인 플러그 색이 형성될 부위만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 2C, after the photosensitive film 37 is coated on the oxide film 16, the photosensitive film 17 is self-aligned contact (SAC) for a T-type contact plug. It is selectively exposed and developed so that only the site where the in plug color is to be formed is removed.
도 2d에서와 같이, 상기 선택적으로 노광 및 현상된 감광막(17)을 마스크로 상기 산화막(16)을 식각하여 플러그 색(18)을 형성한 후, 상기 감광막(17)을 제거한다.As shown in FIG. 2D, the oxide 16 is etched using the selectively exposed and developed photosensitive film 17 as a mask to form a plug color 18, and then the photosensitive film 17 is removed.
도 2e에서와 같이, 상기 플러그 색(18)을 포함한 전면에 플러그층 형성용 다결정 실리콘층(19)을 형성한다.As shown in FIG. 2E, a polycrystalline silicon layer 19 for forming a plug layer is formed on the entire surface including the plug color 18.
도 2f에서와 같이, 상기 제 1 질화막(33)을 에치-스톱퍼(Etch-stopper)로 하여 상기 산화막(17)과 다결정 실리콘층(19)을 평탄화 시켜 다수개의 플러그층(19a)을 형성한다.As illustrated in FIG. 2F, a plurality of plug layers 19a are formed by planarizing the oxide layer 17 and the polycrystalline silicon layer 19 by using the first nitride layer 33 as an etch-stopper.
종래의 반도체 소자의 제조 방법은 플러그층 형성용인 다결정 실리콘층을 형성한 후, 워드 라인 상부 부위의 질화막을 에치-스톱퍼로 층간 절연막인 산화막과 상기 다결정 실리콘층을 평탄화 시켜 플러그층을 형성할 때, 상기 산화막의 두께가지역에 따라 1000 ∼ 2000Å의 차이가 발생하기 때문에 평탄화 공정시 다음과 같은 이유로 소자의 오동작이 발생되는 문제점이 있었다.In the conventional method of manufacturing a semiconductor device, when the polycrystalline silicon layer for plug layer formation is formed, the nitride layer of the upper portion of the word line is etched to form a plug layer by planarizing the oxide film, which is an interlayer insulating film, and the polycrystalline silicon layer. Since the thickness of the oxide film is different from 1000 to 2000Å according to the region, there is a problem that the device malfunctions during the planarization process due to the following reasons.
첫째, 산화막의 두께가 가장 두꺼운 곳을 기준으로 평탄화 공정을 진행하는 경우에는 산화막의 두께가 얇은 부위에는 워드 라인 상부 부위의 질화막이 과다하게 손상된다.First, when the planarization process is performed based on the thickest portion of the oxide film, the nitride film of the upper portion of the word line is excessively damaged in the thin portion of the oxide film.
둘째, 산화막의 두께가 가장 얇은 곳을 기준으로 평탄화 공정을 진행하는 경우에는 산화막의 두께가 두꺼운 부위에는 플러그층간의 절연이 이루어지지 않아 전기적 쇼트(Short)가 발생된다.Second, in the case where the planarization process is performed based on the thickness of the oxide film having the thinnest thickness, electrical short is generated because insulation between the plug layers is not performed at the portion where the oxide film is thick.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 플러그층 형성용인 다결정 실리콘층을 워드 라인 네가티브 감광막을 마스크로 식각한 후, 워드 라인 상부 부위의 질화막을 에치-스톱퍼로 층간 절연막인 산화막과 상기 다결정 실리콘층을 평탄화 시켜 플러그층을 형성하므로 소자의 수율을 향상시키는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and after etching the word line negative photoresist with a polycrystalline silicon layer for plug layer formation as a mask, the nitride film of the upper portion of the word line is etch-stopper and the oxide film and the polycrystalline interlayer insulating film. It is an object of the present invention to provide a method for manufacturing a semiconductor device which improves the yield of devices since the plug layer is formed by planarizing the silicon layer.
도 1은 일반적인 워드라인 및 T-타입 활성영역을 나타낸 레이아웃도1 is a layout diagram showing a general word line and a T-type active region;
도 2a 내지 도 2f는 도 1의 Ⅰ∼Ⅰ선상의 종래 기술에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art on line I to I in FIG. 1.
도 3a 내지 도 3h는 도 1의 Ⅰ∼Ⅰ선상의 본 발명의 실시 예에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도3A to 3H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention along the lines I to I of FIG.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
31: 반도체 기판 32: 게이트 산화막31 semiconductor substrate 32 gate oxide film
33: 제 1 질화막 34: 제 2 질화막 측벽33: first nitride film 34: second nitride film sidewall
36: 제 2 산화막 37: 제 1 감광막36: second oxide film 37: first photosensitive film
38: 플러그 색 39: 다결정 실리콘층38: plug color 39: polycrystalline silicon layer
39a: 플러그층 40: 제 2 감광막39a: plug layer 40: second photosensitive film
본 발명의 반도체 소자의 제조 방법은 다수개의 플러그층들이 형성될 부위가 정의된 기판을 마련하는 단계, 양측과 상부에 각각 제 1 절연막 측벽과 제 2 절연막이 형성된 다수개의 워드 라인들을 상기 기판상에 형성하는 단계, 상기 워드 라인들을 포함한 전면에 상기 제 1, 제 2 절연막과 식각 선택비를 갖는 제 3 절연막을 형성하는 단계, 상기 플러그층들이 형성될 부위의 기판이 노출되도록 제 3 절연막을 선택적으로 식각하는 단계, 전면에 플러그 형성용 도전층을 형성하는 단계,상기 제 3 절연막을 에치-스톱퍼로 하여 상기 도전층을 평탄화 시키는 단계, 상기 제 2 절연막을 에치-스톱퍼로 상기 워드 라인 상측의 도전층을 식각하는 단계 및 상기 제 1 절연막을 에치-스톱퍼로 상기 제 3 절연막과 도전층을 평탄화 시켜 다수개의 플러그층들을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.In the method of manufacturing a semiconductor device of the present invention, the method includes: providing a substrate having a portion where a plurality of plug layers are to be formed, and a plurality of word lines having first and second insulating film sidewalls and a second insulating film formed on both sides and on the substrate, respectively. Forming a third insulating film having an etch selectivity with the first and second insulating films on the entire surface including the word lines, and selectively forming a third insulating film to expose a substrate at a portion where the plug layers are to be formed. Etching, forming a plug forming conductive layer on the entire surface, planarizing the conductive layer using the third insulating film as an etch stopper, and forming a conductive layer on the word line with the second insulating film as an etch stopper. Etching and forming a plurality of plug layers by planarizing the third insulating layer and the conductive layer using an etch-stopper of the first insulating layer. Characterized by comprising a step.
상기와 같은 본 발명에 따른 반도체 소자의 제조 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings a preferred embodiment of the method for manufacturing a semiconductor device according to the present invention as follows.
본 발명의 실시 예에 따른 반도체 소자의 제조 방법은 도 3a에서와 같이 DRAM 셀의 비트 라인 및 스토리지 노드 전극의 플러그층 형성 방법으로, 불순물 영역을 포함한 반도체 기판(31)상에 게이트 산화막(32)이 내재되며 상부 부위에 하드 마스크로 제 1 질화막(33)이 그리고 양측에 제 2 질화막 측벽(34)이 형성된 워드 라인(W)들을 형성한다.A method of fabricating a semiconductor device according to an exemplary embodiment of the inventive concept is a method of forming a plug layer of a bit line and a storage node electrode of a DRAM cell, as shown in FIG. 3A. The gate oxide layer 32 is formed on a semiconductor substrate 31 including an impurity region. Word lines (W) formed by the first nitride film 33 and the second nitride film sidewalls 34 on both sides thereof are formed.
여기서, 상기 제 1 질화막(33)과 제 2 질화막 측벽(34)을 SiN이나 SiON 또는Si-RICH SiON으로 형성한다.Here, the first nitride film 33 and the second nitride film sidewall 34 are formed of SiN, SiON, or Si-RICH SiON.
그리고, 후공정에서 플러그 색 형성을 위한 산화막 식각시 발생되는 소자분리산화막(도시하지 않음)의 손상을 방지하기 위해 상기 워드 라인(W)들을 포함한 전면에 200Å 이하의 얇은 두께를 갖으며 SiN, SiON, Al2O3, Ta2O5, SiOCH 및 SiCH중 하나를 사용한 질화막을 형성할 수 있다.In addition, in order to prevent damage to the device isolation oxide film (not shown) generated during the etching of the oxide film for forming the plug color in the subsequent process, the front surface including the word lines (W) has a thin thickness of 200 Å or less and has a thickness of SiN and SiON. A nitride film using one of Al 2 O 3, Ta 2 O 5, SiOCH, and SiCH can be formed.
도 3b에서와 같이, 상기 워드 라인(W)들을 포함한 전면에 층간 절연막으로서 두께가 두꺼운 산화막(36)을 형성한 다음, 상기 산화막(36)을 평탄화 시킨다.As shown in FIG. 3B, a thick oxide film 36 is formed as an interlayer insulating film on the entire surface including the word lines W, and then the oxide film 36 is planarized.
여기서, 상기 산화막(36)을 피에스지(Phospho Silicate Glass:PSG), 비피에스지(Boron Phosphrus Silicate Glass:BPSG), 에치디피(High Density Plasma:HDP), 유에스지(Undoped Silicate Glass:USG) 및 에이피엘(Advanced Planaraization Layer:APL)중 하나로 형성할 수 있다.Here, the oxide layer 36 may include PSG (Phospho Silicate Glass: PSG), BPS (Boron Phosphrus Silicate Glass: BPSG), Echidpi (High Density Plasma: HDP), Undoped Silicate Glass (USG), and API. It can be formed as one of the Advanced Planaraization Layer (APL).
또한, 상기 산화막(36)을 CMP(Chemical Mechanical Polishing) 또는 에치 백(Etch Back)공정으로 평탄화 시킨다.In addition, the oxide layer 36 is planarized by a chemical mechanical polishing (CMP) or an etch back process.
그리고, 상기 산화막(36)을 상에 제 1 감광막(37)을 도포하고, 상기 제 1 감광막(37)을 T-타입의 플러그 색이 형성될 부위만 제거되도록 선택적으로 노광 및 현상한다.Then, a first photosensitive film 37 is coated on the oxide film 36, and the first photosensitive film 37 is selectively exposed and developed to remove only a portion where a T-type plug color is to be formed.
도 3c에서와 같이, 상기 선택적으로 노광 및 현상된 제 1 감광막(37)을 마스크로 상기 산화막(36)을 식각하여 T-타입의 플러그 색(38)을 형성한 후, 상기 제 1 감광막(37)을 제거한다.As shown in FIG. 3C, the oxide film 36 is etched using the selectively exposed and developed first photoresist layer 37 to form a T-type plug color 38, and then the first photoresist layer 37 is formed. ).
여기서, 상기 산화막(37)을 질화막에 대한 고선택비를 갖도록 C2F6, C2F4, C3F6, C3F8, C4F6, C4F8, C5F8, C5F10과, C2HF5 등 다량의 폴리머(Polymer)를 유발하는 과탄소 함유 가스를 사용하여 식각한다.In this case, the oxide film 37 uses a percarbon-containing gas that causes a large amount of polymer such as C2F6, C2F4, C3F6, C3F8, C4F6, C4F8, C5F8, C5F10, and C2HF5 to have a high selectivity to the nitride film. To etch.
그리고, 상기 산화막(37)을 상기 과탄소 함유 가스와 식각 멈춤 문제를 해결하고 식각 공정 윈도우(Window)를 증가 시켜 재현성 있는 식각 공정을 확보하기 위하여 CxHyFz계의 CHF3, CH2F2, CH3F, CH2, CH4, C2H4과, H2 등의 수소를 포함하는 가스가 혼합된 가스를 사용하여 식각한다.In addition, in order to solve the problem of stopping the etching of the oxide film 37 with the gas containing carbon and to increase the etching process window, the CxHyFz-based CHF3, CH2F2, CH3F, CH2, CH4, Etching is performed using a gas in which C2H4 and a gas containing hydrogen such as H2 are mixed.
또한, 상기 산화막(37)을 플라즈마 안정 및 스퍼터링(Sputtering) 효과를 증가 시켜 식각 멈춤 문제를 해결하기 위하여 He, Ne, Ar과, Ze 등의 불활성 가스가혼합된 가스를 사용하여 식각한다.In addition, in order to solve the etch stop problem by increasing the plasma stabilization and sputtering effects, the oxide film 37 is etched using a mixture of inert gas such as He, Ne, Ar, and Ze.
도 3d에서와 같이, 상기 플러그 색(38)을 포함한 전면에 플러그층 형성용 다결정 실리콘층(39)을 형성한다.As shown in FIG. 3D, a polycrystalline silicon layer 39 for forming a plug layer is formed on the entire surface including the plug color 38.
여기서, 상기 다결정 실리콘층(39)을 텅스텐(W), Ti/TiN, 셀렉티브(Selective) Si-에픽택셜 그로스(Eptiaxial Growth) 및 셀렉티브 텅스텐중 하나로 형성할 수 있다.The polycrystalline silicon layer 39 may be formed of one of tungsten (W), Ti / TiN, selective Si-epitaxial growth, and selective tungsten.
도 3e에서와 같이, 상기 산화막(36)을 에치-스톱퍼로 하여 상기 다결정 실리콘층(39)을 평탄화 시킨다.As shown in FIG. 3E, the polycrystalline silicon layer 39 is planarized by using the oxide film 36 as an etch stopper.
여기서, 상기 다결정 실리콘층(39)을 CMP 또는 에치 백 공정으로 평탄화 시킨다.Here, the polycrystalline silicon layer 39 is planarized by a CMP or etch back process.
도 3f에서와 같이, 상기 평탄화된 다결정 실리콘(39)과 산화막(37)상에 네가티브(Negative)인 제 2 감광막(40)을 형성한다.As shown in FIG. 3F, a negative second photosensitive film 40 is formed on the planarized polycrystalline silicon 39 and the oxide film 37.
그리고, 상기 워드 라인(W) 상측 부위의 제 2 감광막(40)이 제거되도록 상기 워드 라인(W) 형성시 사용한 마스크에 의해 상기 제 2 감광막(40)을 선택적으로 노광 및 현상한다.The second photosensitive film 40 is selectively exposed and developed by a mask used to form the word line W so that the second photosensitive film 40 on the upper portion of the word line W is removed.
도 3g에서와 같이, 상기 선택적으로 노광 및 현상된 제 2 감광막(40)을 마스크로 상기 다결정 실리콘층(39)을 선택적으로 식각하여 다수개의 플러그층(39a)을 형성하고, 상기 제 2 감광막(40)을 제거한다.As shown in FIG. 3G, the polycrystalline silicon layer 39 is selectively etched using the selectively exposed and developed second photosensitive film 40 as a mask to form a plurality of plug layers 39a, and the second photosensitive film ( Remove 40).
여기서, 상기 다결정 실리콘층(39)을 로딩(Loading) 효과에 의한 식각율 감소를 방지하고 주변 영역을 덮어 식각율을 유지하기 위해 상기 제 2 감광막(40)과탑 일렉트로드 네가티브(Top Electrode Negative) 감광막을 마스크로 식각하여 다수개의 플러그층(39a)을 형성할 수 있다.Here, the second photoresist film 40 and the top electrode negative photoresist film may be used to prevent the reduction of the etch rate due to the loading effect of the polycrystalline silicon layer 39 and to maintain the etch rate by covering the peripheral area. May be etched with a mask to form a plurality of plug layers 39a.
또한, 상기 제 2 감광막(40)을 주변 영역까지 덮을 수 있도록 노광 및 현상한 다음, 상기 제 2 감광막(40)을 마스크로 상기 다결정 실리콘층(39)을 선택적으로 식각하여 다수개의 플러그층(39a)을 형성할 수 있다.In addition, after exposing and developing the second photoresist film 40 to cover the peripheral region, the plurality of plug layers 39a may be selectively etched using the second photoresist film 40 as a mask. ) Can be formed.
도 3h에서와 같이, 상기 제 1 질화막(33)을 에치-스톱퍼로 하여 상기 산화막(37)과 다결정 실리콘층(39)을 평탄화 시킨다.As shown in FIG. 3H, the oxide film 37 and the polycrystalline silicon layer 39 are planarized by using the first nitride film 33 as an etch stopper.
여기서, 상기 산화막(37)과 다결정 실리콘층(39)을 CMP 또는 에치 백 공정으로 평탄화 시킨다.Here, the oxide film 37 and the polycrystalline silicon layer 39 are planarized by a CMP or etch back process.
본 발명의 반도체 소자의 제조 방법은 평탄화된 층간 절연막상에 형성한 플러그층 형성용인 다결정 실리콘층을 층간 절연막을 에치-스톱퍼로 제 1 차 평탄화 시키고 워드 라인 네가티브 감광막을 마스크로 제 2 차 식각한 후, 워드 라인 상부 부위의 하드 마스크층을 에치-스톱퍼로 제 3 차 평탄화 시켜 플러그층을 형성하므로, 상기 하드 마스크층이 손상되지 않고 플러그층간의 절연이 이루어지지 않아 발생되는 전기적 쇼트를 방지하여 소자의 수율을 향상시키는 효과가 있다.In the method of manufacturing a semiconductor device of the present invention, the polycrystalline silicon layer for forming a plug layer formed on the planarized interlayer insulating film is first planarized using an etch-stopper, and the second line is etched using a word line negative photoresist film as a mask. Since the hard mask layer of the upper portion of the word line is thirdly planarized with an etch-stopper to form a plug layer, the hard mask layer is not damaged and insulation between the plug layers is not formed to prevent electrical shorts. There is an effect of improving the yield.
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| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |