KR100443351B1 - Method of forming contact hole for semiconductor device - Google Patents
Method of forming contact hole for semiconductor device Download PDFInfo
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- KR100443351B1 KR100443351B1 KR10-2001-0088108A KR20010088108A KR100443351B1 KR 100443351 B1 KR100443351 B1 KR 100443351B1 KR 20010088108 A KR20010088108 A KR 20010088108A KR 100443351 B1 KR100443351 B1 KR 100443351B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
본 발명은 콘택홀 형성을 위한 식각시 식각 마스크로서 텅스텐막의 하드 마스크를 적용하여 콘택홀 손상 및 브리지 현상 등을 방지할 수 있는 반도체 소자의 콘택홀 형성방법을 제공한다. 본 발명의 일 측면에 따르면, 층간절연막이 형성된 반도체 기판 상에 텅스텐막을 형성하는 단계; 상기 텅스텐막을 식각하여 상기 층간절연막의 일부를 노출시키는 하드 마스크를 형성하는 단계; 및 상기 하드 마스크를 식각 마스크로하여 상기 노출된 층간절연막을 식각하여 상기 기판의 일부를 노출시키는 콘택홀을 형성하는 단계를 포함하되, 5 내지 10mTorr의 압력과 500 내지 1000W의 소오스 전력 및 50 내지 100W의 바이어스 전력을 이용하여 상기 텅스텐막의 식각을 수행하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법이 제공된다.The present invention provides a method for forming a contact hole in a semiconductor device capable of preventing contact hole damage and bridge phenomenon by applying a hard mask of a tungsten film as an etching mask for etching a contact hole. According to an aspect of the invention, the step of forming a tungsten film on a semiconductor substrate formed with an interlayer insulating film; Etching the tungsten film to form a hard mask exposing a portion of the interlayer insulating film; And forming a contact hole exposing a part of the substrate by etching the exposed interlayer insulating layer using the hard mask as an etch mask, wherein a pressure of 5 to 10 mTorr and a source power of 500 to 1000 W and 50 to 100 W are formed. Provided is a method of forming a contact hole in a semiconductor device, wherein the tungsten film is etched using a bias power of.
Description
본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것으로, 특히 텅스텐막의 하드 마스크를 적용한 반도체 소자의 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming contact holes in semiconductor devices, and more particularly, to a method for forming contact holes in semiconductor devices to which a hard mask of a tungsten film is applied.
일반적으로, 하부 도전층과 상부 도전층을 전기적으로 연결하기 위한 배선을 형성하기 위하여, 하부 도전층과 상부 도전층 사이에 개재된 절연막에 콘택홀을 형성한다.In general, to form a wiring for electrically connecting the lower conductive layer and the upper conductive layer, a contact hole is formed in the insulating film interposed between the lower conductive layer and the upper conductive layer.
도 1a 내지 도 1d는 종래의 반도체 소자의 콘택홀 형성방법을 설명하기 위한 단면도이다.1A to 1D are cross-sectional views illustrating a method for forming a contact hole in a conventional semiconductor device.
도 1a를 참조하면, 층간절연막(11)이 형성된 반도체 기판(10) 상에 이후 포토리소그라피 공정시 반사를 방지하기 위한 반사방지막으로서 저부아크(Bottom Anti Reflective Coating; BARC)막(12)을 형성하고, 그 상부에 포토레지스트막(13)을 도포한다. 그 다음, 공지된 포토리소그라피 공정으로 포토레지스트막(13)을 패터닝하여, 도 1b에 도시된 바와 같이, BARC막(12)을 일부 노출시키는 포토레지스트 패턴(13A)을 형성한다.Referring to FIG. 1A, a bottom anti-reflective coating (BARC) film 12 is formed on the semiconductor substrate 10 having the interlayer insulating film 11 formed thereon as an anti-reflection film for preventing reflection in a subsequent photolithography process. The photoresist film 13 is applied on the top. Then, the photoresist film 13 is patterned by a known photolithography process to form a photoresist pattern 13A that partially exposes the BARC film 12, as shown in FIG. 1B.
도 1c를 참조하면, 포토레지스트 패턴(13A)을 식각 마스크로하여 노출된 BARC막(12)을 식각하여 하부의 층간절연막(11)을 노출시킨 후, 다시 노출된 층간절연막(11)을 식각하여, 도 1d에 도시된 바와 같이, 기판(10)의 일부를 노출시키는 콘택홀(14)을 형성한다.Referring to FIG. 1C, the exposed BARC film 12 is etched using the photoresist pattern 13A as an etching mask to expose the lower interlayer insulating film 11, and then the exposed interlayer insulating film 11 is etched again. As shown in FIG. 1D, a contact hole 14 exposing a part of the substrate 10 is formed.
상술한 바와 같이, 종래에는 콘택홀 형성을 위한 식각시 식각 마스크로서 포토레지스트 패턴을 사용하였다. 그러나, 반도체 소자의 고집적화에 따라 콘택홀의 크기는 점점 더 미세해지고 층간절연막의 높이는 더 높아져서 콘택홀의 깊이가 증가하기 때문에, 종래에서와 같이 포토레지스트 패턴을 이용하여 콘택홀 식각을 수행하는 경우, 포토레지스트 마진(margin)이 부족하여 콘택홀(14)의 상부(100)가 손상되는 문제가 발생한다. 또한, 이러한 콘택홀 손상이 심한 경우에는 후속 배선 형성 후 인접 배선과의 브리지 현상이 유발됨으로써, 결국 소자의 신뢰성을 저하시키게 된다.As described above, a photoresist pattern is conventionally used as an etching mask during etching for forming contact holes. However, as the integration of semiconductor devices increases, the size of the contact hole becomes smaller and the height of the interlayer insulating layer becomes higher, resulting in an increase in the depth of the contact hole. Thus, when performing contact hole etching using a photoresist pattern as in the prior art, There is a problem that the upper portion 100 of the contact hole 14 is damaged due to lack of margin. In addition, in the case where such contact hole damage is severe, a bridge phenomenon with adjacent wirings is caused after the formation of subsequent wirings, thereby reducing the reliability of the device.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 콘택홀 형성을 위한 식각시 식각 마스크로서 텅스텐막의 하드 마스크를 적용하여 콘택홀 손상 및 브리지 현상 등을 방지할 수 있는 반도체 소자의 콘택홀 형성방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the problems of the prior art as described above, by applying a hard mask of a tungsten film as an etching mask for forming a contact hole, a semiconductor device capable of preventing contact hole damage and bridge phenomenon, etc. Its purpose is to provide a method for forming a contact hole.
도 1a 내지 도 1d는 종래의 반도체 소아의 콘택홀 형성방법을 설명하기 위한 단면도.1A to 1D are cross-sectional views illustrating a conventional method for forming a contact hole in a semiconductor child.
도 2a 내지 도 2g는 본 발명의 실시예에 따른 반도체 소자의 콘택홀 형성방법을 설명하기 위한 단면도.2A to 2G are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.
※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing
20 : 반도체 기판 21 : 층간절연막20 semiconductor substrate 21 interlayer insulating film
22 : 텅스텐막 22A : 하드 마스크22: tungsten film 22A: hard mask
23 : BARC막 24 : 포토레지스트막23: BARC film 24: photoresist film
24A : 포토레지스트 패턴 25 : 콘택홀24A: Photoresist Pattern 25: Contact Hole
26 : 플러그26: plug
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 층간절연막이 형성된 반도체 기판 상에 텅스텐막을 형성하는 단계; 상기 텅스텐막을 식각하여 상기 층간절연막의 일부를 노출시키는 하드 마스크를 형성하는 단계; 및 상기 하드 마스크를 식각 마스크로하여 상기 노출된 층간절연막을 식각하여 상기 기판의 일부를 노출시키는 콘택홀을 형성하는 단계를 포함하되, 5 내지 10mTorr의 압력과 500 내지 1000W의 소오스 전력 및 50 내지 100W의 바이어스 전력을 이용하여 상기 텅스텐막의 식각을 수행하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법이 제공된다.According to an aspect of the present invention for achieving the above technical problem, forming a tungsten film on a semiconductor substrate on which an interlayer insulating film is formed; Etching the tungsten film to form a hard mask exposing a portion of the interlayer insulating film; And forming a contact hole exposing a part of the substrate by etching the exposed interlayer insulating layer using the hard mask as an etch mask, wherein a pressure of 5 to 10 mTorr and a source power of 500 to 1000 W and 50 to 100 W are formed. Provided is a method of forming a contact hole in a semiconductor device, wherein the tungsten film is etched using a bias power of.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
도 2a 내지 도 2g는 본 발명의 실시예에 따른 반도체 소자의 콘택홀 형성방법을 설명하기 위한 단면도이다.2A to 2G are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 층간절연막(21)이 형성된 반도체 기판(20) 상에 이후 하드 마스크로서 사용되는 텅스텐막(22)을 형성한다. 그 다음, 도 2b에 도시된 바와 같이, 텅스텐막(22) 상부에 이후 포토리소그라피 공정시 반사를 방지하기 위한 반사방지막으로서 BARC막(23)을 형성하고, 그 상부에 포토레지스트막(24)을 도포한다. 그 후, 공지된 포토리소그라피 공정으로 포토레지스트막(24)을 패터닝하여, 도 2c에 도시된 바와 같이, BARC막(23)을 일부 노출시키는 포토레지스트 패턴(24A)을 형성한다.Referring to FIG. 2A, a tungsten film 22, which is later used as a hard mask, is formed on the semiconductor substrate 20 on which the interlayer insulating film 21 is formed. Next, as shown in FIG. 2B, a BARC film 23 is formed on the tungsten film 22 as an antireflection film for preventing reflection in a subsequent photolithography process, and a photoresist film 24 is formed thereon. Apply. Thereafter, the photoresist film 24 is patterned by a known photolithography process to form a photoresist pattern 24A that partially exposes the BARC film 23, as shown in FIG. 2C.
도 2d를 참조하면, 포토레지스트 패턴(24A)을 식각 마스크로하여 노출된 BARC막(23)을 식각하여 하부의 텅스텐막(22)을 노출시킨다. 그 다음, 도 2e에 도시된 바와 같이, 포토레지스트 패턴(24A)을 식각 마스크로하여 텅스텐막(23)을 식각하여 층간절연막(21)을 일부 노출시키는 하드 마스크(23A)를 형성한다. 여기서, 텅스텐막의 식각은 DPS(Decoupled Plasma Source) 장비를 이용하여, 5 내지10mTorr의 압력과 500 내지 1000W의 소오스 전력(source power) 및 50 내지 100W의 바이어스 전력(bias power) 하에서 수행한다. 또한, 식각 개스로서는 SF6/N2 개스를 이용한다. 이때, 식각개스인 SF6 : N2의 비율은 약 3 : 1 정도로 조절한다.Referring to FIG. 2D, the exposed BARC film 23 is etched using the photoresist pattern 24A as an etching mask to expose the lower tungsten film 22. Next, as shown in FIG. 2E, the tungsten film 23 is etched using the photoresist pattern 24A as an etching mask to form a hard mask 23A that partially exposes the interlayer insulating film 21. Here, the etching of the tungsten film is performed under a pressure of 5 to 10 mTorr, a source power of 500 to 1000 W, and a bias power of 50 to 100 W using a Decoupled Plasma Source (DPS) device. In addition, SF6 / N2 gas is used as an etching gas. At this time, the ratio of the etching gas SF6: N2 is adjusted to about 3: 1.
도 2f를 참조하면, 공지된 방법으로 포토레지스트 패턴(24A) 및 BARC막(23)을 제거한다. 그 다음, 하드 마스크(23A)를 식각 마스크로하여 노출된 층간절연막(22)을 식각하여, 기판(20)의 일부를 노출시키는 콘택홀(25)을 형성한다. 여기서, 콘택홀(25) 형성을 위한 식각은 SCCM(Super Conductive Coupled Module) 장비를 이용하여, 10 내지 30mTorr의 압력과, 1500 내지 2000W의 최상부전력(top power) 및 1000 내지 2000W의 저부전력(bottom power) 하에서 수행한다.2F, the photoresist pattern 24A and the BARC film 23 are removed by a known method. Next, the exposed interlayer insulating film 22 is etched using the hard mask 23A as an etching mask to form a contact hole 25 exposing a portion of the substrate 20. Here, etching for forming the contact hole 25 is performed using a Super Conductive Coupled Module (SCCM) device, a pressure of 10 to 30 mTorr, a top power of 1500 to 2000 W, and a bottom power of 1000 to 2000 W. under power).
바람직하게, 예컨대, 콘택홀(25)이 배선용인 경우에는, 압력은 20 내지 30mTorr의 범위로 조절하고, 최상부전력 및 저부전력은 각각 1500 내지 2000W 및 1500 내지 2000W의 범위로 조절하며, 식각 개스로서 CH3/C4F8/O2/CH2F2/Ar를 이용하되, CH3 : C4F8 : O2 : CH2F2 : Ar의 비율은 4:1:2:1:50 이상으로 조절한다.Preferably, for example, when the contact hole 25 is for wiring, the pressure is adjusted in the range of 20 to 30 mTorr, the top power and the bottom power are adjusted in the range of 1500 to 2000W and 1500 to 2000W, respectively, as an etching gas. CH3 / C4F8 / O2 / CH2F2 / Ar is used, and the ratio of CH3: C4F8: O2: CH2F2: Ar is adjusted to 4: 1: 2: 1: 50 or more.
또한, 콘택홀(25)이 캐패시터의 스토리지 노드용인 경우에는, 압력은 10 내지 20mTorr의 범위로 조절하고, 최상부전력 및 저부전력은 각각 1500 내지 2000W 및 1000 내지 1500W로 조절하며, 식각 개스로서 C4F8/O2/Ar 이나 C5F8/O2/Ar을 이용하여 수행한다. 이때, C4F8 : O2 : Ar 의 비율은 2:1:50 이상으로 조절하고, C5F8: O2 : Ar 의 비율도 2:1:50 이상으로 조절한다.In addition, when the contact hole 25 is for a storage node of the capacitor, the pressure is adjusted in the range of 10 to 20 mTorr, the top power and the bottom power are adjusted to 1500 to 2000W and 1000 to 1500W, respectively, and C4F8 / as an etching gas. This is done using O2 / Ar or C5F8 / O2 / Ar. At this time, the ratio of C4F8: O2: Ar is adjusted to 2: 1: 50 or more, and the ratio of C5F8: O2: Ar is adjusted to 2: 1: 50 or more.
그 후, 콘택홀(25)에 매립되도록 플러그용 도전막을 증착한 후, 상기 도전막과 하드 마스크(26)를 층간절연막(21)의 표면이 노출되도록 전면식각하여, 도 2g에도시된 바와 같이, 콘택홀(25)에 매립되어 기판(20)과 콘택하는 플러그(26)를 형성한다.Thereafter, after the plug conductive film is deposited to be filled in the contact hole 25, the conductive film and the hard mask 26 are etched to expose the surfaces of the interlayer insulating film 21, and as shown in FIG. 2G. The plug 26 is formed in the contact hole 25 to contact the substrate 20.
상기 실시예에 의하면, 콘택홀 형성을 위한 식각시 식각 마스크로서 텅스텐막의 하드 마스크를 이용함으로써, 깊은 콘택홀의 형성시에도 콘택홀 상부의 손상이 발생되지 않으므로, 종래와 같은 브리지 현상 등을 방지할 수 있다. 또한, 하드 마스크로서의 텅스텐막을 이후 플러그 형성을 위한 도전막의 전면식각시 동시에 제거할 수 있으므로 하드 마스크 제거를 위한 별도의 제거공정을 수행할 필요가 없다.According to the above embodiment, by using a hard mask of a tungsten film as an etching mask for etching the contact hole, damage of the upper part of the contact hole does not occur even when the deep contact hole is formed, thereby preventing a bridge phenomenon and the like. have. In addition, since the tungsten film as the hard mask can be removed at the same time during the entire surface etching of the conductive film for plug formation, there is no need to perform a separate removal process for removing the hard mask.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
전술한 본 발명은 콘택홀 형성을 위한 식각시 식각 마스크로서 텅스텐막의 하드 마스크를 적용하여 깊은 콘택홀 형성시 발생되는 콘택홀 손상 및 브리지 현상 등을 방지함으로써, 소자의 신뢰성을 향상시킬 수 있다.According to the present invention, by applying a hard mask of a tungsten film as an etching mask for etching a contact hole, the contact hole damage and the bridge phenomenon generated during deep contact hole formation may be prevented, thereby improving reliability of the device.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970052334A (en) * | 1995-12-22 | 1997-07-29 | 김주용 | Metal wiring formation method of semiconductor device |
| KR20000032183A (en) * | 1998-11-13 | 2000-06-05 | 윤종용 | Method for forming storage contact for producing storage electrode of dram cell |
| JP2000216241A (en) * | 1999-01-20 | 2000-08-04 | Applied Materials Inc | Method for manufacturing semiconductor device |
| KR20010029859A (en) * | 1999-06-29 | 2001-04-16 | 니시무로 타이죠 | Method of manufacturing a semiconductor device |
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| KR970052334A (en) * | 1995-12-22 | 1997-07-29 | 김주용 | Metal wiring formation method of semiconductor device |
| KR20000032183A (en) * | 1998-11-13 | 2000-06-05 | 윤종용 | Method for forming storage contact for producing storage electrode of dram cell |
| JP2000216241A (en) * | 1999-01-20 | 2000-08-04 | Applied Materials Inc | Method for manufacturing semiconductor device |
| KR20010029859A (en) * | 1999-06-29 | 2001-04-16 | 니시무로 타이죠 | Method of manufacturing a semiconductor device |
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