KR100457619B1 - Plasma display panel and the fabrication method thereof - Google Patents

Abstract

A plasma display panel and a method of manufacturing the same are disclosed. The present invention provides a front substrate having a plurality of grooves having a predetermined pattern in which a bus electrode is to be formed, a bus electrode embedded in the groove, and a common and scan electrode formed on the lower surface of the annoying front substrate so as to conduct electricity with the bus electrode. A back substrate including an upper dielectric layer filling the common and scan electrodes, a protective film layer applied to a lower surface of the upper dielectric layer, and an address electrode disposed to face the front substrate and orthogonal to the electrodes; And a lower dielectric layer filling the address electrode, a partition wall disposed between the address electrodes on the lower dielectric layer, and a red, green, and blue phosphor layer formed inside the partition wall.

Description

Plasma display panel and manufacturing method thereof

The present invention relates to a plasma display panel, and more particularly, to a plasma display panel having an improved structure of an electrode formed on a front substrate and a method of manufacturing the same.

In general, the plasma display panel injects and discharges a discharge gas on two circuit boards coated with a plurality of electrodes, applies a discharge voltage, and then applies an appropriate pulse voltage when a gas emits light between the electrodes due to the discharge voltage. A display device that implements a desired number, letter, or graphic by addressing a point where two electrodes intersect.

The plasma display panel may be classified into a direct current type and an alternating current type according to a type of a driving voltage applied to a discharge cell, for example, a discharge type, and may be classified into a counter discharge type and a surface discharge type according to the configuration of the electrodes.

The DC plasma display panel has a structure in which all electrodes are exposed to a discharge space, and charges are directly transferred between corresponding electrodes. On the other hand, in the AC plasma display panel, at least one electrode is embedded in the dielectric layer, and instead of direct charge transfer between the corresponding electrodes, the ions and electrons generated by the discharge adhere to the surface of the dielectric layer to form a wall. A wall voltage is formed and discharge can be maintained by a sustaining voltage.

On the other hand, in the opposite discharge type plasma display panel, an address electrode and a scan electrode are provided to face each unit pixel, and addressing discharge and sustain discharge are generated between the two electrodes. On the other hand, in the surface discharge plasma display panel, an address electrode, a common electrode, and a scan electrode corresponding to each unit pixel are provided to generate addressing discharge and sustain discharge.

As shown in FIG. 1, the conventional plasma display panel 10 includes a front substrate 11 and a rear substrate 12 disposed to face the front substrate 11.

Strips of the common and scan electrodes 13 and 14 are alternately formed on the lower surface of the front substrate 11, and electrodes along one edge of the lower surface of the common and scan electrodes 13 and 14 are alternately formed. In order to reduce the line resistance of the 13 and 14, a bus electrode 15 made of a metal material formed by narrowing the width of the electrodes 13 and 14 is provided.

An upper dielectric layer 16 is applied to the bottom surface of the front substrate 11 to bury the electrodes 13, 14 and 15, and a magnesium oxide (magnesium oxide) is applied to the bottom surface of the upper dielectric layer 16 to protect it. A protective film layer 17 made of MgO is formed.

On the other hand, an address electrode 18 having a shape perpendicular to the common and scan electrodes 13 and 14 is formed on an upper surface of the rear substrate 12 provided to face the front substrate 11. The address electrode 18 is buried by a lower dielectric layer 19, and a partition wall 100 is formed on an upper surface of the lower dielectric layer 19 to be spaced apart by a predetermined interval. The phosphor layer 110 of green, blue color is applied.

In the conventional plasma display panel 10 having the above structure, when a trigger voltage is applied between the scan electrode 14 and the address electrode 18, preliminary discharge occurs to charge the wall charge. In this state, when a voltage is applied between the common and scan electrodes 13 and 14, sustain discharge occurs to generate plasma. From this, ultraviolet rays are radiated to excite the phosphor layer 110 to implement a desired image.

However, the conventional plasma display panel 10 patterns a plurality of common and scan electrodes 13 and 14 on the bottom surface of the front substrate 11, and one edge of the bottom surface of the electrodes 13 and 14. The bus electrode 15 is thus formed.

Looking at the formation process of the electrodes 13, 14, 15, the common and scan electrodes 13, 14 made of a transparent conductive film on the substrate 11 are 0.1 micron by sputtering or ion plating. It is formed to have a thickness of about a meter, and the bus electrode 15 having a thickness of about 2 to 4 micrometers should be formed on the lower surfaces of the electrodes 13 and 14, so a high precision is required, so that the manufacturing process It's quite tricky.

The present invention has been made to solve the above problems, and an object thereof is to provide a plasma display panel and a method of manufacturing the same, by improving the structure of a bus electrode formed on a front substrate, thereby simplifying the manufacturing process.

1 is an exploded perspective view illustrating a portion of a conventional plasma display panel cut out;

2 is an exploded perspective view illustrating a portion of a plasma display panel according to an embodiment of the present invention;

3A to 3F illustrate a state after forming a functional layer on the front substrate of FIG. 2.

3A is a cross-sectional view showing a state after a front substrate is provided;

3B is a cross-sectional view illustrating a state after a groove is formed on the front substrate of FIG. 3A;

3C is a cross-sectional view illustrating a state after a bus electrode is embedded in the groove part of FIG. 3B;

3D is a cross-sectional view illustrating a state after a plurality of electrodes are formed on a bottom surface of the front substrate of FIG. 3A;

3E is a cross-sectional view illustrating a state after an upper dielectric layer is embedded in the electrode of FIG. 3D;

3F is a cross-sectional view illustrating a state after a protective film layer is formed on a bottom surface of the upper dielectric layer of FIG. 3E.

<Brief description of symbols for the main parts of the drawings>

10,20 ... plasma display panel

11,21 ... front substrate 12,22 ... back substrate

13,23 ... common electrode 14,24 ... scan electrode

15,25 ... bus electrode 16,26,46 ... top dielectric layer

17,27 ... Protective layer 18,28 ... Address electrode

Lower dielectric layer 21a ... groove

100,200 ... bulk 110,210 ... phosphor layer

In order to achieve the above object, the plasma display panel according to an aspect of the present invention,

A front substrate on which a plurality of grooves of a predetermined pattern on which a bus electrode is to be formed are formed;

A bus electrode made of metal embedded in the groove portion;

A plurality of common and scan electrodes formed alternately on the lower surface of the front substrate so as to be energized with the bus electrodes;

An upper dielectric layer formed on a lower surface of the front substrate to fill the common and scan electrodes;

A passivation layer applied to a lower surface of the upper dielectric layer;

A rear substrate provided to face the front substrate and having an address electrode formed in a form orthogonal to the electrodes;

A lower dielectric layer formed on an upper surface of the rear substrate to fill the address electrode;

Barrier ribs disposed between the address electrodes on the lower dielectric layer to partition discharge spaces; And

And red, green, and blue phosphor layers formed inside the partition wall.

According to another aspect of the present invention,

Providing a front substrate;

Forming a groove having a pattern on which a bus electrode is to be formed on the front substrate;

Filling a bus electrode raw material into the groove and firing to complete a bus electrode;

Alternately forming a common and a scan electrode on the front substrate such that the bus electrode is located at one edge;

Forming an upper dielectric layer to bury the electrodes; And

Forming a protective film layer on the upper dielectric layer provides a method of manufacturing a plasma display panel comprising a.

In the forming of the groove portion,

The groove portion is formed by a sand blasting method.

In the forming of the groove portion,

The groove portion is formed by photolithography.

In addition, in the step of completing the bus electrode,

And smoothing the surface of the front substrate so that the bus electrodes are not exposed.

Hereinafter, a plasma display panel according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 illustrates a plasma display panel 20 according to an embodiment of the present invention.

Referring to the drawing, the plasma display panel 20 is provided with a front substrate 21. Grooves 21a are formed on the lower surface of the front substrate 21 at predetermined intervals, and the grooves 21a are formed with a conductive bus electrode 25 in a strip form.

On the lower surface of the front substrate 21, a plurality of pairs of discharge cells composed of a strip-shaped common electrode 23 and a scan electrode 24 are alternately formed such that the bus electrode 25 is positioned at one edge thereof. .

An upper dielectric layer 26 is formed on the bottom surface of the front substrate 21 to fill the common and scan electrodes 23 and 24. On the lower surface of the upper dielectric layer 26, a protective film layer 27 made of magnesium oxide is formed.

On the other hand, on the upper surface of the rear substrate 22 which is installed to face the front substrate 21, an address electrode 28 in a form orthogonal to the common and scan electrodes 23 and 24 is formed in a strip form. The address electrode 28 is buried by the lower dielectric layer 29. The upper surface of the lower dielectric layer 29 defines a discharge space, and the partition walls 200 are formed to be spaced apart from each other to prevent cross talk, and an inert gas such as argon gas is injected into the discharge space. In addition, red, green, and blue phosphor layers 210 are coated inside the partition wall 200.

3A to 3F illustrate step by step processes of forming the above-mentioned functional layer on the front substrate 21.

First, a substrate 21 made of transparent glass, for example, a substrate 21 made of soda lime glass is provided. (FIG. 3A) The substrate 21 is a material in which deformation of temperature is kept at a minimum. It is preferable that it consists of.

After the substrate 21 is provided, the groove 21a on which the bus electrode 25 to be described later is formed is formed on the substrate 21. (FIG. 3B) Various methods are used to form the groove 21a. This can be.

The groove 21a may be formed on the substrate 21 by a photolithography process. That is, the photoresist is applied onto the substrate 21a, and the photomask on which the pattern of the bus electrode 25 is formed is aligned on the substrate 21, and the groove 21a is formed by exposing, developing and etching. . The depth of the groove portion 21a should be adjusted to be equal to the height of the bus electrode 25, preferably about 2 to 4 micrometers.

Besides the photolithography process, there is a sand blast method. That is, when a mask on which the pattern of the bus electrode 25 is to be formed is placed on the substrate 21, and the abrasive is sprayed at high pressure on the entire surface of the substrate 21, the bus is applied to the substrate 21 at the pressure. The groove portion 21a having a predetermined depth is formed in the portion where the pattern of the electrode 25 is to be formed. This groove portion 21a is on the order of 2 to 4 micrometers as mentioned above.

Subsequently, the groove 21a is filled with a conductive material, preferably a silver paste, of the conductive bus electrode 25 (FIG. 3C). And the raw material of this bus electrode 25 is dried, and it bakes at predetermined temperature. When the baking is completed, the bus electrode 25 is completed through a predetermined polishing process so that the raw material of the bus electrode 25 does not protrude to the upper surface of the substrate 21.

Next, common and scan electrodes 23 and 24 are formed on the front substrate 21. FIG. 3D. That is, raw materials of the electrodes 23 and 24 on the substrate 21 are formed. A phosphor transparent conductive film, preferably an ITO film, is applied, and the patterned photo mask is placed, exposed, developed and etched to form electrodes 23 and 24.

In this case, the common and scan electrodes 23 and 24 are formed on the panel at which the bus electrode 25 is located along one edge of the electrodes 23 and 24 as shown in the drawing. The line resistance of the electrodes 23 and 24 can be reduced while improving the aperture ratio of the 20. Accordingly, the common and scan electrodes 23 and 24 can be energized with the bus electrode 25.

Next, an upper dielectric layer 26 is applied on the front substrate 21 to fill the common and scan electrodes 23 and 24 (FIG. 3E).

After application of the upper dielectric layer 26 is completed, a protective film layer 27 made of magnesium oxide is formed on the upper surface of the upper dielectric layer 26 to protect it (Fig. 3F).

Thus, the formation of the functional layer on the front substrate is completed.

A process of forming a functional layer on the lower substrate will be briefly described with reference to FIG. 2. A substrate 22 made of transparent glass is prepared, and the common and scan electrodes 23 and 24 are formed on the substrate 22. ), The address electrode 28 is formed in the direction crossing the. Subsequently, a lower dielectric layer 29 filling the address electrode 28 is coated, and a partition wall 200 is formed between the address electrodes 28 on the lower dielectric layer 29. Next, the red, green, and blue phosphor layers 210 are respectively applied between the partition walls 200 to be completed.

The front substrate 21 and the rear substrate 22 thus completed are sealed and evacuated, and then Xe having high ultraviolet radiation intensity is injected into the panel 20. Accordingly, the plasma display panel 20 according to the exemplary embodiment of the present invention is completed.

In the plasma display panel 20 according to the present invention having the above structure, a voltage is applied between the scan electrode 24 and the address electrode 28 so that preliminary discharge occurs to charge the wall charge. In the discharge space filled with the wall charges, a voltage is applied between the common electrode 23 and the scan electrode 24 to generate sustain discharge, thereby generating plasma. From this, ultraviolet rays are radiated to excite the red, green, and blue phosphor layers 210 to realize an image.

As described above, the plasma display panel and the method of manufacturing the same of the present invention provide a groove portion on a front substrate, and by providing a bus electrode in the groove portion, the upper dielectric layer filling the common and scan electrodes that are energized with the bus electrode. The thickness can be reduced by the height of the bus electrode. In addition, by applying a thin transparent conductive film on the front substrate on which the bus electrode is formed to form a common and a scan electrode, the contact area becomes more secure and line resistance can be minimized.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. . Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (5)

A front substrate on which a plurality of grooves of a predetermined pattern on which a bus electrode is to be formed are formed; A bus electrode made of metal embedded in the groove portion; A plurality of common and scan electrodes formed alternately on the lower surface of the front substrate so as to be energized with the bus electrodes; An upper dielectric layer formed on a lower surface of the front substrate to fill the common and scan electrodes; A passivation layer applied to a lower surface of the upper dielectric layer; A rear substrate provided to face the front substrate and having an address electrode formed in a form orthogonal to the electrodes; A lower dielectric layer formed on an upper surface of the rear substrate to fill the address electrode; Barrier ribs disposed between the address electrodes on the lower dielectric layer to partition discharge spaces; And And a red, green, and blue phosphor layer formed inside the partition wall. Providing a front substrate; Forming a groove having a pattern on which a bus electrode is to be formed on the front substrate; Filling a bus electrode raw material into the groove and firing to complete a bus electrode; Alternately forming a common and a scan electrode on the front substrate such that the bus electrode is located at one edge; Forming an upper dielectric layer to bury the electrodes; And And forming a passivation layer on the upper dielectric layer. The method of claim 2, In the step of forming the groove portion, And the groove portion is formed by a sand blasting method. The method of claim 2, In the step of forming the groove portion, And the groove portion is formed by a photolithography method. The method of claim 2, In the step of completing the bus electrode, And smoothing the surface of the front substrate so that the bus electrode is not exposed to the surface of the front substrate.