KR100450115B1 - Column redundancy circuit of semiconductor memory device, especially improving efficiency of repair - Google Patents

Abstract

The present invention relates to a column redundancy circuit of a semiconductor memory device, and even if a failure occurs during the first repair, a secondary repair is possible, and a column redundancy circuit of a semiconductor memory device for preventing unnecessary power consumption by an unused fuse box. In order to achieve the above object, a primary repair column disable device and a power consumption prevention device are provided, and when the present invention is implemented in a semiconductor memory device, secondary repair is possible to improve repair efficiency and prevent unnecessary power consumption. It is effective.

Description

Column Redundancy Circuit in Semiconductor Memory Devices

The present invention relates to a column redundancy circuit of a semiconductor memory device. In particular, a primary repair column, which is performed to replace a fail in relation to a fail of a memory cell, also performs a second repair when a fail occurs to improve repair efficiency. The present invention relates to a column redundancy circuit of a semiconductor memory device for reducing unnecessary power consumption by cutting off a path of a circuit that is not used.

FIG. 1 is a column redundancy circuit diagram according to the related art, and includes a sub block selection fuse box 11 connected between a row address signal input terminal and a repair column selection fuse box 21, an output terminal of the sub block selection fuse box 11, and a sub block selection fuse box 11. The repair column selection fuse box 21 connected between the input terminals of the second inverter IV2 and receiving the column address signal, and the signals A and B indicating the column operation through the two input terminals are inputted to convert the logically calculated value into the first inverter ( IV1) a first NOR gate NR1 for outputting to an input terminal, a first inverter for inverting the first NOR gate output signal and outputting the first NAND gate output signal to one input terminal of the first NAND gate ND1, and the first inverter output signal A first NAND gate for receiving the second inverter output signal as two inputs and outputting a logically calculated value to an input terminal of the third inverter IV3, and the first NAND gate output signal; A third inverter for selecting column redundancy Yi <0>, a sub block selection fuse box 12 connected between the row address signal input terminal and the repair column selection fuse box 22, and the sub block selection fuse A repair column select fuse box 22 connected between the box 12 output terminal and the fifth inverter IV5 input terminal and receiving a column address signal, and signals A and B indicating the column operation through two input terminals are inputted and logically operated. A second NOR gate NR2 for outputting a value to an input terminal of the fourth inverter IV4, a fourth inverter for inverting the second NOR gate output signal and outputting the second NAND gate output signal to one input terminal of the second NAND gate, and the fourth inverter A second NAND gate for receiving an output signal and the fifth inverter output signal as two inputs, and outputting a logically calculated value to the sixth inverter IV6 input terminal; A sixth inverter for inverting the output output signal to select column redundancy Yi, a sub block selection fuse box 1n connected between the row address signal input terminal and the repair column selection fuse box 2n, and the sub A repair column select fuse box 2n, which is connected between the block select fuse box 1n output terminal and the eighth inverter IV8 input terminal and receives a column address signal, and signals A and B for informing column operation through two input terminals, A third NOR gate for outputting the logically calculated value to the seventh inverter IV7 input terminal, a seventh inverter for inverting the third NOR gate output signal and outputting the third NAND gate ND3 to one input terminal; A third NAND gate configured to receive the seventh inverter output signal and the eighth inverter output signal as two inputs, and output a logic operation value to the ninth inverter IV9 input terminal; And a ninth inverter for selecting column redundancy Yi by inverting the third NAND gate output signal.

Hereinafter, an operation relationship of the column redundancy circuit having the above configuration will be described.

For example, when the repair column line corresponding to column redundancy Yi is enabled, the output terminal of the sub block selection fuse box 11 is low, the output terminal of the sub block selection fuse box 12 is high, and the sub The output terminal of the block select fuse box 1n is high, the output terminal of the repair column select fuse box 21 is low, the output terminal of the repair column select fuse box 22 is high, and the output column of the repair column select fuse box 2n The output stage becomes high so that the second inverter output stage is high, the fifth inverter output stage is low, and the eighth inverter IV8 output stage is low. On the other hand, when any one or both of the signals A and B indicating the column operation are enabled high, the output terminals of the first inverter, the fourth inverter, and the seventh inverter IV7 are all high. Accordingly, the first NAND gate output terminal is outputted with a low signal and is inverted by the third inverter, so that column redundancy Yi is enabled, and the second NAND gate output terminal and the third NAND gate output terminal are outputted with high column redundancy. Yi <1> and column redundancy Yi (n) are disabled.

FIG. 2 is a circuit diagram of a sub-block selection fuse box and a repair column selection fuse box according to the related art, in which the sub-block selection fuse box 11 is supplied with a CBR signal to a gate, a power supply voltage terminal, and a source of a second PMOS transistor MP2. A first PMOS transistor MP1 connected between the terminals, and a second gate connected to the fourth NOR gate NR4 output terminal and connected between the first PMOS transistor drain terminal and the first node N1. A PMOS transistor, a first NMOS transistor MN1, to which the CBR signal is applied as a gate and connected between the first node and a ground voltage terminal, and one input terminal of which is connected to the first node and / XDP to the other input terminal. A signal is applied and an output terminal is connected to a fourth NOR gate NR4 connected to the second PMOS transistor gate terminal, and a first fuse f1 connected between the first node and the drain terminal of the second NMOS transistor MN2. ), A second NMOS transistor connected with the gate address signal <0> to the gate, and connected between the first fuse and the ground voltage terminal, and between the first node and the drain terminal of the third NMOS transistor MN3. A third NMOS transistor connected to the second fuse f2 connected to the gate and a low address signal < 1 >, and connected between the second fuse and the ground voltage terminal, the first node and the fourth NMOS transistor (MN4) A third fuse f3 connected between the drain terminal, a fourth NMOS transistor connected to the gate and a low address signal and connected between the third fuse and the ground voltage terminal, and one input terminal of the first fuse. The SCE signal is connected to the node, the SCE signal is applied to the other input terminal, and the output terminal includes a fourth NAND gate ND4 connected to the repair column select fuse box 21.

The repair column select fuse box 21 has a third PMOS gate whose gate is connected to the fourth NAND gate output terminal of the sub block select fuse box 11 and is connected between a power supply voltage terminal and a source terminal of a fourth PMOS transistor MP4. A fourth PMOS transistor connected to a transistor, a / ATD signal to a gate, and connected between the third PMOS transistor drain terminal and a second node, and a gate of the fourth NAND gate output terminal of the sub block selection fuse box; A fifth NMOS transistor MN5 and a gate connected to an output terminal of a tenth inverter IV10 and connected between a power supply voltage terminal and the second node. 5 PMOS transistor MP5, between a tenth inverter connected between the second node and the fifth PMOS transistor gate terminal, and between the second node and the sixth NMOS transistor MN6 drain terminal. Connected fourth fuse f4, a column address signal <0> to a gate, and a sixth NMOS transistor MN6 connected between the fourth fuse and the ground voltage terminal; A fifth fuse f5 connected between the drain terminal of the NMOS transistor MN7, a seventh NMOS transistor connected to the ground voltage terminal and having a column address signal <1> applied to a gate thereof; A sixth fuse f6 connected between the second node and the drain terminal of the eighth NMOS transistor MN8 and a column address signal <n> are applied to a gate and connected between the sixth fuse and the ground voltage terminal. An eighth NMOS transistor and an eleventh inverter IV11 for selecting a repair column line by inverting a signal on the second node.

Hereinafter, an operation relationship between the sub block selection fuse box 11 and the repair column selection fuse box 21 having the above configuration will be described.

First, if CBR, / XDP, SCE, and / ATD signals are defined, the CBR (CAS Before RAS) signal is a high signal only in a specific operation and has a low level in normal operation. The / XDP (X Decoder Precharge) signal is a signal that is enabled high by RAS enable at high and is disabled by high by disabling the low address. The Column Enable Selection (SCE) signal is a signal that is enabled high by enabling the low address low to low and deactivated low after disabling the RAS. The / ATD (Address Transition Detection) signal is enabled from high to low due to an address transition, and then disabled again after a predetermined time delay.

When the CBR signal has a low level and the / XDP signal has a high level, the first PMOS transistor is turned on and the second PMOS transistor is turned on by the low level of the fourth NOR gate output terminal to turn on the first node. The phase is precharged with the supply voltage.

In the above state, when the row address signal <0> is described as an example, when the row address signal <0> is applied to the second NMOS transistor gate terminal, the second NMOS transistor is turned on to supply power to the first node. The level is conducted to the ground terminal through the first fuse and the second NMOS transistor so that the potential on the first node has a low level. The low level on the first node is applied to one input terminal of the fourth NAND gate, and thus the fourth NAND gate output terminal has a high level regardless of the SCE signal, so that the repair column select fuse box 21 does not operate.

Referring to the operation of the repair column select fuse box 21 during the normal operation, when the high potential of the fourth NAND gate output terminal of the sub block select fuse box 11 is applied to the third PMOS transistor and the fifth NMOS transistor gate, When the fifth NMOS transistor is turned on, the second node is at a low level, is inverted by the eleventh inverter, and a high signal is output so that a repair operation is not performed.

Meanwhile, referring to the operation relationship between the sub block selection fuse box 11 and the repair column selection fuse box 21 during the repair operation, the first fuse and the repair column selection fuse box 21 of the sub block selection fuse box 11 are described. For example, when the first node is precharged to a high level and the row address signal <0> is applied to the second NMOS transistor gate terminal, the second NMOS transistor is turned on. However, since the first fuse is blown, the high level on the first node is maintained and thus is applied to the fourth NAND gate one input terminal. At this time, since the SCE signal is enabled high when the low address signal is enabled at the low level, the high signal is applied to the other input terminal of the fourth NAND gate. Accordingly, a low signal is output to the fourth NAND gate output terminal and applied to the repair column select fuse box 21 to the third PMOS transistor and the fifth NMOS transistor gate terminal. Thus, the third PMOS transistor is turned on and the fifth NMOS transistor is turned off. On the other hand, since the / ATD signal applied to the fourth PMOS transistor gate terminal transitions from high to low at this time, the fourth PMOS transistor is turned on so that the potential rises to the high level on the second node. At this time, even if the column address signal <0> is applied to the sixth NMOS transistor gate terminal and the sixth NMOS transistor is turned on, the fourth fuse is blown so that the high level on the second node is maintained as it is. The high level on the second node inverted by the inverter is applied to the fifth PMOS transistor gate terminal so that the power supply voltage is transferred onto the second node through the turned on fifth PMOS transistor so that the high level on the second node is high. Keep it. As a result, the high level on the second node is inverted by the eleventh inverter to output a low level potential and perform a repair operation.

When the repair operation described above is applied to the column redundancy circuit of FIG. 1 and the operation relationship thereof is described, the output terminal of the sub block selection fuse box 11 and the output terminal of the repair column selection fuse box 21 are a low level and sub block selection fuse. The outputs of the box 12 and the repair column selection fuse box 22 are at the high level, and the output terminals of the sub block selection fuse box 1n and the repair column selection fuse box 2n are at the high level. At this time, when either or both signals A and B indicating the column operation become high, the first inverter output terminal is high, the second inverter output terminal is high, the fourth inverter output terminal is high, the fifth inverter output terminal is low, and the fifth inverter output terminal is high. 7 The inverter output terminal is high, the eighth inverter output terminal is output a low signal. Therefore, a low signal is output at the first NAND gate output terminal, a high signal is output at the second NAND gate output terminal, and a third NAND gate output terminal, so that redundancy column Yi <0> is high, redundancy column Yi <1> is low, and redundancy column Yi. Becomes low, and only the redundancy column Yi performs the repair operation.

However, if the repair column line selected by the redundancy column Yi <0> fails for some reason, the chip cannot be replaced by any other repair under the address corresponding to the redundancy column Yi <0> and the redundancy column continues. Yi <0> is enabled and therefore always fails.

As such, when a column failure occurs in the operation of a semiconductor memory device such as a conventional DRAM, if a redundancy column also fails after a repair is performed to replace the redundancy column, the device has no useful value and should be discarded. there was.

Therefore, the present invention was devised to solve the above problems, and the power consumption prevention device 41 is added to the sub-block selection fuse box in order to add a primary repair column disable device to the primary repair column fuse box and to prevent unnecessary power consumption. It is an object of the present invention to provide a column redundancy circuit of a semiconductor memory device for enabling secondary repair and preventing unnecessary power consumption.

1 is a column redundancy circuit diagram according to the prior art.

2 is a circuit diagram of a sub-block selection fuse box and a repair column selection fuse box according to the related art.

3 is a circuit diagram of a sub-block selection fuse box and a repair column selection fuse box according to a first embodiment of the present invention.

4 is a circuit diagram of a sub-block selection fuse box and a repair column selection fuse box for preventing unnecessary power consumption of an unused redundancy fuse box according to a second embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

11, 12, 1n: Sub-block selection fuse box

21, 22, 2n: Repair Column Selection Fuse Box

31: Primary repair column disable device

41: power consumption prevention device

The column redundancy circuit of the present invention for achieving the above object comprises a primary repair column disable means for disabling the primary repair column line selection signal so that secondary repair is possible even if a failure occurs during the primary repair;

And a power consumption preventing means for preventing unnecessary power consumption of the unused sub-block selection fuse box.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a circuit diagram of a sub block selection fuse box and a repair column selection fuse box according to a first embodiment of the present invention, and includes a sub block selection fuse box 11 for selecting a sub block by receiving a row address signal. A repair column selection fuse box 21 for receiving a first sub-block selection fuse box output terminal signal as an input, and a connection between the sub-block selection fuse box and the repair column selection fuse box; A primary repair column disable device 31 for disabling a signal for selecting a column line.

The sub-block selection fuse box includes an eleventh PMOS transistor MP11 connected to a power supply terminal and a third node, and a gate of the first repair column disable device 31 connected to a gate. A thirteenth PMOS transistor MP12 connected between the third node and the fourth node and an eleventh NOR gate NR11 output signal are applied to the gate and the fourth node is applied. A thirteenth PMOS transistor (MP13) connected between a second node and a fifth node, an eleventh NMOS transistor (MN11) connected with a gate of the fifth node and a ground voltage terminal, and the CBR signal is applied to a gate; Is connected to the fifth node, an / XDP signal is input to the other terminal, and an eleventh NOR gate NR11 connected to an output terminal of the thirteenth PMOS transistor gate terminal, the fifth node and a twelfth NMOS transistor drain. Between terminals A connected eleventh fuse f11, a twelfth NMOS transistor connected with a gate address signal <0> to the gate, and connected between the eleventh fuse and a ground voltage terminal; the fifth node and a thirteenth NMOS transistor; A twelfth fuse f12 connected between the drain terminal, a thirteenth NMOS transistor connected with a gate address signal < 1 > and connected between the twelfth fuse and a ground voltage terminal; A thirteenth fuse f13 connected between a drain terminal of a 14th NMOS transistor MN14, a 14th NMOS transistor connected to a gate address signal and connected between the thirteenth fuse and a ground voltage terminal; Is connected to the fifth node, an SCE signal is applied to the other terminal, and an output terminal includes an eleventh NAND gate ND11 connected to the repair column select fuse box 21st PMOS transistor MP21 gate terminal.

The repair column select fuse box may include a twenty-first PMOS transistor connected to a power supply terminal and a sixth node, to which a sub block select fuse box is applied, and an eleventh NAND gate output signal to a gate; The sable device 31 receives a signal on a tenth node and is connected to a twenty-second PMOS transistor MP22 connected between the sixth node and a seventh node, and an / ATD signal is applied to a gate, and the seventh node and the eighth node. A twenty-third PMOS transistor MP23 connected between nodes and a signal on a tenth node of the primary repair column disable device 31 as a gate are applied, and a twenty-first node connected between the eighth node and a ground voltage terminal. An NMOS transistor MN21 and a twenty-second NMOS transistor connected to the eighth node and a ground voltage terminal to which the sub-block select fuse box 11th NAND gate output signal is applied as a gate; The twenty-first inverter output signal is applied to the 24th PMOS transistor MP24 connected between the power supply voltage terminal and the eighth node, and the signal on the eighth node is inverted and output to the 24th PMOS transistor gate terminal. A twenty-first inverter (IV21), a twenty-first fuse (f21) connected between the eighth node and a twenty-third NMOS transistor drain terminal, a column address signal is applied to a gate, and A column address signal <1> is connected to a 23rd NMOS transistor connected between a ground voltage terminal, a 22nd fuse f22 connected between the eighth node and a drain terminal of a 24th NMOS transistor MN24, and a gate is provided. A twenty-fourth NMOS transistor applied and connected between the twenty-second fuse and a ground voltage terminal; a twenty-third fuse connected between the eighth node and a drain terminal of the 25 th NMOS transistor (MN25); A twenty-fifth NMOS transistor connected to the twenty-third fuse and a ground voltage terminal; and a twenty-second inverter for inverting a signal on the eighth node to select a primary repair column line.

The primary repair column disable device 31 includes a thirty-first fuse (a fuse for primary repair column disable) connected between a power supply voltage terminal and a ninth node, a gate of which is connected to the ninth node, and a power supply voltage terminal. A thirty-first PMOS transistor MP31 connected between a second node and a tenth node, a thirty-first NMOS transistor MN31 connected to a gate of the tenth node, and connected between the ninth node and a ground voltage terminal; Is connected between the ninth node and between the tenth node and the ground voltage terminal, and between the ninth node and the sub-block selection fuse box twelfth PMOS transistor gate terminal. It is comprised with the 31st inverter connected.

Hereinafter, the operation relationship of the column redundancy circuit having the above configuration will be described. In the normal operation, the eleventh NAND gate output terminal of the sub-block selection fuse box is high, and the 22nd inverter output terminal of the repair column selection fuse box is high. The repair operation is not performed, and in the first repair operation, a low signal is output to the eleventh NAND gate output terminal of the sub-block selection fuse box and a low signal is output to the twenty-second inverter output terminal of the repair column selection fuse box so that the primary repair operation is performed. Since the operation relationship is described in the operation relationship of FIG.

Hereinafter, a description will be given of an operation relationship in which a secondary repair is performed due to a certain failure occurring even in the repair column line during the primary repair operation.

In this case, the sub-block selection fuse box 11th NAND gate output terminal is low, and the repair column selection fuse box 22nd NAND gate output terminal is low, and the repair column selection is performed by the primary repair column disable device 31. By disabling the signal at the 22nd inverter output terminal of the fuse box, a second repair is performed by disabling a signal for selecting a repair column line in which a fail is generated and selecting another repair column line.

When the thirty-first fuse of the primary repair column disable device 31 is cut off, the potential on the ninth node has a low level. Thus, the thirty-first PMOS transistor is turned on and the thirty-second NMOS transistor is turned off. The 31st NMOS transistor is turned on to maintain the potential on the ninth node at a low level. The low level on the ninth node is inverted by a thirty-first inverter such that the sub-block selection fuse box twelfth PMOS transistor is turned off and the eleventh NMOS transistor is turned on by a high CBR signal to thereby turn on the fifth node. The phase has a low level and the fifth node phase is not affected even when the row address signal <0> is applied to the twelfth NMOS transistor by the cut eleventh fuse. Accordingly, a high signal is output to the eleventh NAND gate output terminal regardless of the SCE signal, and is applied to the twenty-first PMOS transistor gate terminal and the twenty-second NMOS transistor gate terminal of the repair column select fuse box, so that the twenty-first PMOS transistor is turned on. -Off The twenty-second NMOS transistor is turned on so that the eighth node has a low level. Meanwhile, the repair column select fuse box is turned off by the high level on the tenth node of the primary repair column disable device 31. The twenty-second PMOS transistor is turned off. The twenty-first NMOS transistor is turned on. The NMOS transistor prevents the low level on the eighth node from raising the potential due to noise or the like. As a result, the low level on the eighth node is inverted by the twenty-second inverter and the high level is output so that the primary repair column enable signal for selecting the failed repair column line is disabled and thus another repair column select fuse. The secondary repair can be performed using the box.

4 is a circuit diagram of a sub-block selection fuse box and a repair column selection fuse box for preventing unnecessary power consumption of an unused redundancy fuse box according to a second embodiment of the present invention. Since high integration of the device is required during the process, there may be a case where a particular part of the chip is worried, and in this case, the cell part generates a lot of failures in the specific part. In addition, there is a case where the process is stabilized so that no fail occurs at all. In this case, the redundancy circuit is not necessary at all except the specific part of the former and the latter. However, when the memory devices such as DRAMs operate repeatedly, unnecessary power consumption is generated by repeatedly performing precharge and discharge.In the dozens to hundreds of redundancy circuits located in the entire chip, such unnecessary power consumption is a large value that cannot be ignored. This is to prevent this.

Referring to the configuration of FIG. 4, the CBR signal is applied to the gate, and the forty-first PMOS transistor MP41 connected between the power supply voltage terminal and the source terminal of the forty-second PMOS transistor MP42, and the gate is a power consumption prevention device ( A 42-th PMOS transistor connected to an eleventh node of FIG. 41 and connected between the forty-first PMOS transistor drain terminal and a forty-third PMOS transistor MP43 source terminal, and a gate thereof are connected to an output terminal of the forty-first NOR gate NR 41. And a forty-third PMOS transistor MP43 connected between the forty-second PMOS transistor drain terminal and a thirteenth node, and a forty-first NMOS connected between the thirteenth node and a ground voltage terminal, with the CBR signal applied to a gate; A NOR transistor NR4 having a transistor MN41 and one terminal connected to the thirteenth node, a / XDP signal applied to the other terminal, and an output terminal connected to the 43rd PMOS transistor gate terminal. 1), a forty-first fuse f41 connected between the thirteenth node and a drain terminal of the forty-second NMOS transistor MN42, and a low address signal are applied to the gate, and the forty-first fuse and the ground voltage terminal are applied. A 42nd fuse f42 connected between the forty-second NMOS transistor, a thirty-second fuse connected between the thirteenth node, and a forty-third NMOS transistor drain terminal, and a gate address signal < 1 > A 43rd NMOS transistor connected between the ground and the ground voltage terminal, a 43rd fuse f43 connected between the thirteenth fuse and a drain terminal of the 44th NMOS transistor (MN44), and a low address signal A forty-fourth NMOS transistor connected between the forty-third fuse and a ground voltage terminal; a first terminal connected to the thirteenth node; an SCE signal is applied to the other terminal; and an output terminal connected to a repair column select fuse box; A drain column ND41, a repair column select fuse box connected to the 41th NAND gate output terminal of the sub block select fuse box, and a power consumption prevention device 41 for preventing unnecessary power consumption of the sub block select fuse box. It is composed.

The power consumption preventing device 41 includes a forty-fourth fuse f44 connected between a power supply voltage terminal and an eleventh node, and a 44th gate connected to the eleventh node and connected between a power supply voltage terminal and a twelfth node. A 45th NMOS transistor MN45 having a PMOS transistor MP44, a gate connected to the twelfth node, and connected between the eleventh node and a ground voltage terminal, and a gate connected to the eleventh node; And a forty sixth NMOS transistor MN46 connected between a twelve node and a ground voltage terminal, and the eleventh node is connected to a forty-second PMOS transistor gate terminal of the sub block select fuse box.

Hereinafter, referring to the operation relationship according to the configuration, the 46th NMOS transistor is turned on and the 44th PMOS transistor is turned off by the power supply voltage on the eleventh node transferred through the 44th fuse. The low level on the twelfth node causes the 45th NMOS transistor to be turned off to prevent the high potential on the eleventh node from falling to ground. On the other hand, the high level on the eleventh node prevents the 42nd PMOS transistor from being turned off to prevent the thirteenth node from being precharged, thereby preventing unnecessary power consumption of the sub-block fuse box.

On the other hand, when a repair occurs due to a failure in the cell, the 44th fuse is also cut together, thereby enabling a repair operation.

As described above, even if a failure occurs during the first repair according to the first embodiment of the present invention, the second repair can be performed again by the second repair, and power of an unnecessary fuse box not used by the second embodiment of the present invention. The consumption will be reduced.

When the present invention is implemented in a column redundancy circuit of a semiconductor memory device, even if a failure occurs during the first repair, the second repair is possible, thereby improving the repair efficiency and preventing unnecessary power consumption of the fuse box.

Preferred embodiments of the present invention are for the purpose of illustration and various modifications, changes, substitutions and additions are possible to those skilled in the art through the spirit and scope of the appended claims.

Claims (5)

A sub block selection fuse box for selecting a sub block by a row address signal during a repair operation; A repair column selection fuse box operated by an output signal of the sub block selection fuse box during a repair operation to select a primary repair column line; And Optionally provide power to the sub-block selection fuse box, but the power connected to the sub-block selection fuse box corresponding to the repair provides power, and the power supply to the sub-block selection fuse box not corresponding to the repair cuts off the power. Power consumption preventing means for operating only the selected fuse box; A column redundancy circuit of a semiconductor memory device comprising a. The method of claim 1, wherein the power consumption preventing means A fuse connected between the power supply voltage and the first node; First transfer means connected to a first node by a gate thereof and connected between a power supply terminal and a second node; Second transfer means connected to a gate of the second node and connected between the first node and a ground voltage terminal; Third transfer means connected to a gate of the first node and connected between the second node and a ground voltage terminal; And Fourth transfer means connected to the first node and connected between the two transistors of the sub block select fuse box to cut off the power supply; A column redundancy circuit of a semiconductor memory device comprising a. A sub block selection fuse box for selecting a sub block by a row address signal during a repair operation; A primary repair column selection fuse box operated by an output signal of the sub block selection fuse box during a primary repair operation to select a primary repair column line; A primary repair column disable means for disabling the sub output selection fuse box and the primary repair column selection fuse box during a secondary repair operation due to a failure of the primary repair; And A secondary repair column line driven in response to an output signal of the primary repair column disable means; A column redundancy circuit of a semiconductor memory device comprising a. The method of claim 3, wherein And a second repair column select fuse box which is operated by an output signal of the sub block select fuse box during the second repair operation and selects the second repair column line. . 4. The apparatus of claim 3, wherein the primary repair column disable means comprises: switch means for cutting off a second repair operation to block a power supply voltage from being transmitted to the first node; First transfer means connected to the first node to transfer a power supply voltage to the second node in a second repair operation; Second transfer means connected to the second node and connected between the first node and a ground voltage terminal to maintain a potential on the first node at a low level during a secondary repair operation; Third transfer means connected to said first node and connected between said second node and a ground voltage terminal to be turned off during a secondary repair operation to maintain a potential on said second node at a high level; Fourth transfer means connected to the second node and connected between the repair column select fuse box and two transistors to shut down during a secondary repair operation to prevent transfer of a power supply voltage; Fifth transfer means connected to the second node to conduct a rise of the potential of the repair column selection fuse box due to noise during the secondary repair operation to the ground terminal to prevent a malfunction; Inverting means for inverting a potential on the first node; And Sixth transfer means connected to an output terminal of the inverting means to block precharge of the sub-block selection fuse box during a secondary repair operation; A column redundancy circuit of a semiconductor memory device comprising a.