KR100451511B1 - Method for fabricating wafer level flip-chip array package - Google Patents

Abstract

The present invention relates to a method of fabricating a wafer level flip-chip array package with expanded memory capacity using flip-chip technology and wafer-like substrates in a wafer state. According to the present invention, there is provided a method comprising: providing a wafer on which a plurality of integrated circuit chips are formed; Forming gold bumps on a chip pad formed on an upper surface of the integrated circuit chip; Forming an adhesive on an upper surface of the integrated circuit chip on both sides of the gold bumps; Bonding a wafer substrate to the entire upper surface of the wafer such that the gold pad of the integrated circuit chip is electrically connected to the bond finger and the ball pad formed on the upper surface of the wafer substrate; Filling an underfill material with a gap between the wafer and the wafer like substrate; Forming solder balls on the ball pads; Electrically connecting the bond fingers formed on two or more neighboring substrates by gold wires; Forming an encapsulation material to protect the bond finger to which the gold wire is connected from an external environment; And cutting the wafer into two or more integrated circuit chip units.

Description

METHODS FOR FABRICATING WAFER LEVEL FLIP-CHIP ARRAY PACKAGE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor package, and more particularly, to a method of manufacturing a wafer level flip-chip array package having an expanded memory capacity using a flip-chip technique and a wafer type substrate in a wafer state.

In the semiconductor industry, packaging technology for integrated circuit chips continues to evolve. For example, the memory capacity is increased by stacking multiple memory chips having the same size and function, or the integrated circuit chips having different functions are assembled in one package to maximize the performance and efficiency of the product. . As is well known, for example, a stack package or a multichip package.

According to the related art of the art, a stack package or a multi chip package is typical of stacking several packages into one and stacking multiple chips in one package. However, such a conventional stacked package or multi-chip package is a package using a lead frame, and it is difficult to apply to a system that requires miniaturization and thinning because the package mounting area and height are high. In addition, the use of lead frames makes them unsuitable for high-speed device products, and their manufacturing processes are generally very complex.

Accordingly, it is an object of the present invention to provide a method of manufacturing a wafer level flip-chip array package that can realize high density, high capacity, high speed, and simplify the manufacturing process while minimizing the mounting area and thickness of the package.

1 to 5 are diagrams illustrating a method of manufacturing a wafer level flip-chip package according to an embodiment of the present invention.

1 is a plan view schematically showing a wafer;

2A and 2B are a plan view and a cross-sectional view showing the integrated circuit chip after the bump forming step;

3A and 3B show plan and cross-sectional views of an integrated circuit chip after an adhesive application step;

4A and 4B are a plan view and a cross-sectional view showing a state after the bonding step of the integrated circuit chip and the wafer type substrate;

5A and 5B are plan and cross-sectional views illustrating a wafer level flip-chip package after an underfill step and a ball forming step.

6 and 7 illustrate a method of manufacturing a wafer level flip-chip array package according to another embodiment of the present invention.

6 is a plan view of the array package after the wire connection step;

7 is a plan view of the array package after the encapsulation step.

<Explanation of symbols for the main parts of the drawings>

10: wafer 11: integrated circuit chip

12: scribe area 13: gold bump

14: adhesive 20: wafer-type substrate

21: bond finger 22: ball pad

23: underfill material 24: solder ball

25: gold wire 26: encapsulation material

30: wafer level flip-chip package 40: wafer level flip-chip array package

In order to achieve these objects, a method of manufacturing a wafer level flip-chip array package according to the present invention comprises the steps of providing a wafer having a plurality of integrated circuit chips; Forming gold bumps on a chip pad formed on an upper surface of the integrated circuit chip; Forming an adhesive on an upper surface of the integrated circuit chip on both sides of the gold bumps; Bonding a wafer substrate to the entire upper surface of the wafer such that the gold pad of the integrated circuit chip is electrically connected to the bond finger and the ball pad formed on the upper surface of the wafer substrate; Filling an underfill material with a gap between the wafer and the wafer like substrate; Forming solder balls on the ball pads; Electrically connecting the bond fingers formed on two or more neighboring substrates by gold wires; Forming an encapsulation material to protect the bond finger to which the gold wire is connected from an external environment; And cutting the wafer into two or more integrated circuit chip units.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, each component is shown to be somewhat exaggerated or schematically illustrated in order to facilitate a clear understanding of the drawings, and does not necessarily reflect the actual size.

1 to 5 are diagrams illustrating a method of manufacturing a wafer level flip-chip package according to an embodiment of the present invention.

1 is a plan view schematically showing a general wafer 10 used in the manufacturing method of the present invention. As shown, the wafer 10 is formed of tens or hundreds of integrated circuit chips 11, and neighboring integrated circuit chips 11 are each scribe lanes 12. Divided.

2 to 5, which will be used in the following description, illustrate one integrated circuit chip 11, but the manufacturing method of the present invention is the same for the entire wafer 10.

2A and 2B are a plan view and a cross-sectional view of the integrated circuit chip 11 after the bump forming step, respectively. Referring to FIGS. 2A and 2B, the chip pads (not shown) of the integrated circuit chip 11 may have gold. A bump 13 is formed. The gold bumps 13 may be formed using various conventional methods such as deposition, plating, stencil printing, stud bumping, and the like. Moreover, although gold bumps are preferable, bumps of other materials are also possible. Since the chip pad is disposed along the center of the upper surface of the integrated circuit chip 11, the arrangement of the gold bumps 13 also follows this.

3A and 3B, an adhesive 14 is formed on the upper surface of the integrated circuit chip 11 on both sides of the gold bumps 13. 3A and 3B are a plan view and a sectional view of the integrated circuit chip 11 after the adhesive application step. The adhesive 14 is formed by applying an adhesive material such as epoxy in a liquid and then curing it. At this time, the stencil printing method is preferably used, and a process of aligning the stencil on the wafer before applying the liquid adhesive material is necessary. The liquid adhesive material has a state of so-called B-stage, and after the application step of the liquid adhesive material goes through the first curing step, the wafer is easily and easily handled in a subsequent process.

Subsequently, as shown in FIGS. 4A and 4B, the wafer-like substrate 20 is adhered to the integrated circuit chip 11. 4A and 4B are a plan view and a cross-sectional view showing a state after the bonding step of the integrated circuit chip 11 and the wafer-type substrate 20. In fact, a wafer type substrate 20 is a substrate of the same size as the wafer, and is aligned with the wafer and then bonded to the entire wafer. At this time, the adhesive 14 is preferably secondary cured. A bond finger 21 and a ball pad 22 are formed on an upper surface of the wafer-type substrate 20, and a predetermined pad (not shown) is electrically connected to the gold bumps 13 on the lower surface. (Not shown), there is formed a predetermined circuit pattern (not shown) for electrically connecting the lower surface pad, the bond finger 21 and the ball pad 22 to each other. The bond fingers 21 are disposed along both edges of the top surface of the wafer-type substrate 20, and the ball pads 22 are arranged in the form of a ball grid array at the center of the top surface.

Next, as shown in FIGS. 5A and 5B, the underfill material 23 is filled with a gap between the integrated circuit chip 11 and the wafer-like substrate 20, and then the ball pads 22 are solder balls 24. ). 5A and 5B are a plan view and a cross-sectional view illustrating the wafer level flip-chip package 30 after the underfill step and the ball forming step. The underfill material 23 protects the gold bumps 13 and relieves stresses acting on the top surface of the integrated circuit chip 11. Underfill material 23 is a liquid resin is used and filled in the gap between the integrated circuit chip 11 and the substrate 20 by the capillary phenomenon is cured. Forming solder balls 24 may include steps such as flux application and reflow as is well known.

After forming the package form for each integrated circuit chip 11 in the wafer 10 state through the above processes, the wafer 10 is cut along the scribe area 12 to each integrated circuit chip 11. The fabrication of the wafer level flip-chip package 30 formed of FIG.

The wafer level flip-chip package 30 according to the present invention can be used to fabricate an array package. 6 and 7 illustrate a method of manufacturing a wafer level flip-chip array package according to another embodiment of the present invention. In order to manufacture the array package, the wafer is not cut by each integrated circuit chip unit as in the above-described embodiment, but the wafer is cut by the chip unit (in this case, by two chip units) to form the array package. .

First, as shown in FIG. 6, bond fingers 21 adjacent to each other are electrically connected to the wafer level flip-chip package 30 formed on two neighboring substrates. The electrical connection between the bond fingers 21 is preferably a wire bonding method using a gold wire 25.

As shown in FIG. 7, the encapsulation material 26 is used to protect the bond finger 21 to which the gold wire 25 is connected from the external environment. Thereafter, the wafer is cut into two integrated circuit chip units to complete the manufacture of the wafer level flip-chip array package 40. Encapsulation material 26 may be a resin such as epoxy.

As described above, according to the manufacturing method of the present invention, since a gold bump can be directly formed on a chip pad of an integrated circuit chip and mounted on an external electronic device through solder balls disposed thereon, that is, flip-chip technology is used. This minimizes the footprint and thickness of the package and enables high density and high speed. In addition, since the electrical bonding between neighboring packages can be easily implemented through wire bonding of the bond fingers formed on the substrate, the memory capacity can be easily extended to enable a high capacity package. In addition, there is an advantage that the manufacturing process is simple because the manufacturing process is performed using the wafer-type substrate in the wafer state.

In the present specification and drawings, preferred embodiments of the present invention have been disclosed, and although specific terms have been used, these are merely used in a general sense to easily explain the technical contents of the present invention and to help the understanding of the present invention. It is not intended to limit the scope. It is apparent to those skilled in the art that other modifications based on the technical idea of the present invention can be carried out in addition to the embodiments disclosed herein.

Claims (2)

delete Providing a wafer having a plurality of integrated circuit chips formed thereon; Forming gold bumps on a chip pad formed on an upper surface of the integrated circuit chip; Forming an adhesive on an upper surface of the integrated circuit chip on both sides of the gold bumps; Bonding a wafer substrate to the entire upper surface of the wafer such that the gold pad of the integrated circuit chip is electrically connected to the bond finger and the ball pad formed on the upper surface of the wafer substrate; Filling an underfill material with a gap between the wafer and the wafer like substrate; Forming solder balls on the ball pads; Electrically connecting the bond fingers formed on two or more neighboring substrates by gold wires; Forming an encapsulation material to protect the bond finger to which the gold wire is connected from an external environment; And And cutting the wafer into two or more integrated circuit chip units.