KR100467527B1 - Double-gate MOSFET and method for fabricating the same - Google Patents

Abstract

The present invention relates to a new double gate MOSFET and a method of manufacturing the same.

An insulator laminated on the semiconductor substrate according to the invention; A source and a drain region formed of single crystal silicon on the insulator and spaced apart from each other with one area interposed therebetween; A channel connecting the source and drain spaced apart from each other across a portion of the area, the channel being formed of single crystal silicon on the insulator; An insulating film formed on the channel; Gate insulating films formed on both sides of the channel and on each side of the source and drain regions; It is composed of a gate formed by stacking the gate insulating film and the channel over the insulating film and stacked on the one area between the source and drain regions, so that wide single crystal silicon can be used as a source / drain pad as it is. The remaining single crystal silicon other than the channel between the source / drain and the low resistance double gate MOSFET having no portion is etched and removed, and the gate electrode is filled in the pattern of the etched silicon and the insulating film stack structure formed before it. Provided is a method of manufacturing a double gate MOSFET having a structure in which front and rear gates are self-aligned by etch-back.

Description

Double gate MOSFET and method for manufacturing the same {Double-gate MOSFET and method for fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double gate MOSFET and a method of manufacturing the same, and more particularly, to a double gate MOSFET manufactured on a silicon on insulator (SOI) substrate and a method of manufacturing the same.

In general, metal-oxide-semiconductor field effect transistors (MOSFETs) are being reduced in device size as part of high performance and high integration.In order to implement transistors having a minimum channel length of 50 nm or less, which are used in the next generation, it is necessary to provide drain voltage. Therefore, it is necessary to effectively suppress the short channel effect in which the potential of the channel region is affected.

Recently, many studies have been conducted to reduce the gate length of the field effect transistor to about 20 to 30 nm, but currently published research results do not obtain the characteristics of the level to be applied to the product. This is because it is difficult to effectively suppress the short short channel effect caused by the source and channel side potential being affected by the drain voltage because the distance between the source and drain which is extremely short is extremely short.

Therefore, it is difficult to obtain stable device operation when the device of the conventional planar structure is used as it is, and as an alternative to the planar structure, a double gate field effect transistor having gates on both sides of the thin channel can be effectively controlled. It is being studied as the most likely candidate.

The ideal double-gate field effect transistor has a structure in which the front and rear gates are self-aligned, the gates are self-aligned at the source and drain, and the parasitic resistance of the source and drain can be reduced. However, many attempts have been made to implement such a double gate field effect transistor structure, but it is difficult to manufacture the front / rear gates in a self-aligned form.

As part of an effort to fabricate a double gate field effect transistor having self-aligned front / rear gates while using existing semiconductor process technology in recent years, as shown in FIGS. 1A-1C by D. Hisamoto et al. Fin field effect transistor (FinFET) devices have been announced. This has the advantage of having high compatibility with the conventional planar semiconductor technology.

In FIG. 1A, a plan view of a fin field effect transistor having a conventional double gate structure is illustrated. FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. 1A, and FIG. 1C is a cross-sectional view taken along line B-B ′ of FIG. 1A. The fin field effect transistor includes a support on which a buried oxide film 7 is stacked on the silicon substrate 8; A fin (3) serving as a channel on the buried oxide film (7); A laminated film 1 of an oxide film / nitride film formed on the fin 3; Source and drain (4,4 ') which surround one side and the other side of the laminated film (1) of the oxide film / nitride film, one side and the other side of the fin (3), and are separated from each other by an opening; An oxide film 2 formed on the source and drain 4, 4 '; Nitride film spacers 5 formed on the sides of the openings separating the source and drain 4, 4 ′, openings including the nitride film spacers 5, a part of the oxide film 2, and both sides of the fins 3. The gate oxide film 9 is formed to surround the formed gate oxide film 9.

The fin field effect transistor uses a structure that connects the polycrystalline silicon (4, 4 ') and the fin (3), but there is a significant increase in resistance in this portion, and to form a small sized gate electrode The gate 6 was formed using the nitride film spacer 5. In this case, since the nitride spacer 5 is formed around the fin 3 serving as a channel, a sufficient excessive etching must be performed to remove it, and there is a possibility that the portion of the fin 3 serving as the channel is damaged in this process. . In addition, since the fin 3 of the portion corresponding to the width of the nitride film spacer 5 remains thin as the channel thickness, the source 4 / drain 4 'resistance greatly increases.

In addition, such a fin field effect transistor needs to form a channel having a thickness of about 20 nm or less in order to manufacture a device having a gate size of about 40 nm and stable operation. There is a problem that this is larger, and there is a disadvantage that it is difficult to increase the drive current.

The present invention has been proposed to solve the problems of the conventional double gate MOSFET and its fabrication method. The structure of the double gate MOSFET fabricated on an SOI substrate in a self-aligned type, which can lower the series resistance between the source and the drain, and its manufacture The purpose is to provide a method.

A double gate field effect transistor for achieving the above object comprises an insulator stacked on top of a semiconductor substrate; A source and a drain region formed of single crystal silicon on the insulator and spaced apart from each other with one area interposed therebetween; A channel connecting the source and drain spaced apart from each other across a portion of the area, the channel being formed of single crystal silicon on the insulator; An insulating film formed on the channel; Gate insulating films formed on both sides of the channel and on each side of the source and drain regions; The gate insulating layer and the upper portion of the insulating film surrounding the channel is characterized in that it consists of a gate formed on the upper surface of the one area between the source and drain regions.

In addition, the method of manufacturing a double gate MOSFET of the present invention includes a first step of forming a fine pattern of a first insulating film made of a silicon oxide film or a silicon nitride film on a portion of a SOI substrate to be a channel of single crystal silicon; A second step of depositing a second insulating film on top of the fine pattern of the single crystal silicon and the first insulating film, and then removing the second insulating film of the portion where the gate is to be formed with a fine line width; A third step of exposing the buried oxide film by removing single crystal silicon of a portion where the gate is to be formed by using the fine patterns of the second insulating film and the first insulating film as a mask; A fourth step of growing a gate insulating film in the single crystal silicon portion exposed by the removal of the single crystal silicon in the portion where the gate is to be formed; Depositing a gate material on the first insulating film and the buried oxide film including the gate insulating film; A sixth step of etching the gate material formed on the second insulating film to expose the second insulating film, and leaving the gate material on the first insulating film; Selectively removing the exposed second insulating layer to expose single crystal silicon to the left and right of the gate material; And an eighth step of doping the dopant in order to use the source / drain electrodes in the left and right single crystal silicon.

1A is a plan view of a fin field effect transistor (FinFET) having a conventional double gate structure.

FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG. 1A.

FIG. 1C is a cross-sectional view taken along the line BB ′ of FIG. 1A.

2A to 2H are perspective views showing the manufacturing process of the double gate MOSFET according to the first embodiment of the present invention.

3 is a cross-sectional view taken along line AA ′ of FIG. 2H showing a state in which the double gate MOSFET according to the first embodiment of the present invention is finally completed.

4 is a cross-sectional view taken along line B-B 'of FIG. 2H showing a state in which the double gate MOSFET according to the first embodiment of the present invention is finally completed.

FIG. 5 is a cross-sectional view taken along line C-C 'of FIG. 2H showing a state in which the double gate MOSFET is finally completed according to the first embodiment of the present invention.

6 is a perspective view of a second embodiment of a double gate MOSFET of the present invention.

7A or 7B are perspective views of a third embodiment of the double gate MOSFET of the present invention.

Fig. 8 is a perspective view of a third embodiment of the double gate MOSFET of the present invention.

FIG. 9 is a cross-sectional view taken along the line D-D 'of FIG. 7B showing a third embodiment of the double gate MOSFET of the present invention.

<Description of the symbols for the main parts of the drawings>

10 silicon substrate 11 oxide film

12: single crystal silicon 12 ': channel

13, 14: 1st, 2nd insulating film 15, 15 ': gate insulating film

112 ', 112: source, drain 113,113': first and second material

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

[First Embodiment]

The double gate MOSFET of the present invention is formed on a silicon on insulator (SOI) substrate made of a single crystal silicon / insulator / semiconductor substrate as shown in FIGS. 2A to 2H.

First, a first insulating film 13 to be used as an etch stop film in a subsequent process is deposited on an SOI substrate made of single crystal silicon 12 / oxide film 11 / silicon substrate 10, and the first insulating film ( 13) to form a fine pattern (FIG. 2A).

A silicon nitride film may be used as the first insulating film 13, and a fine patterning technique using electron beam lithography or sidewalls may be used for the fine pattern of the first insulating film 13.

The second insulating layer 14 is deposited on the substrate on which the fine pattern of the first insulating layer 13 is formed. In this way, when the second insulating film 14 is deposited on the first insulating film 13 by a chemical vapor deposition method with a silicon oxide film, bending is formed, as shown in FIG. 2B. The second insulating layer 14 may be formed of silicon or a material having excellent etching selectivity with the first insulating layer 13 in a subsequent process.

When the second insulating film 14 in the portion where the gate region of the device to be manufactured is formed by lithography or a fine patterning method using sidewalls is etched, the first insulating film 13 and the single crystal silicon 12 are exposed. 2c)

At this time, the removal of the second insulating film 14 of the portion where the gate is to be formed may be removed to the same width as the length of the fine pattern of the first insulating film 13, the fine pattern of the first insulating film 13 When removed to a width smaller than the length, as shown in FIG. 2C, only a portion of the inner side is exposed, and a portion of both sides is surrounded by the second insulating layer 14.

FIG. 2D shows a recessed shape when the single crystal silicon of the portion where the gate region is to be formed is etched using the second insulating layer 14 and the first insulating layer 13 as a mask, and the buried oxide film is exposed to the etched portion. Etching of the single crystal silicon in the portion where the gate region is to be formed exposes the sides of the single crystal silicon in the center and left and right sides. The central single crystal silicon becomes the channel 12 ', and the left and right single crystal silicon becomes the source 112' and the drain 112 of the device, respectively.

In FIG. 2E, the gate insulating layers 15 and 15 ′ are grown on the side surfaces of the single crystal silicon in the center, left and right sides in the state of FIG. 2D, and then the first insulating layer 13 including the gate insulating layers 15 and 15 ′. The gate material 16 is deposited on the over buried oxide film 11.

As the gate insulating layers 15 and 15 ', a conventional silicon oxide film, a nitrided oxide film, a high dielectric constant insulating film, or the like may be used.

Polycrystalline or amorphous silicon may be used as the gate material, which may be used after the doping of n-type or p-type dopants in a subsequent process to increase conductivity.

FIG. 2F is a view illustrating a state in which the left and right gate materials 16 are etched in the region where the gate is to be formed. Most preferably, the gate material is etched back.

When the gate material around the left and right sides of the region where the gate is to be formed is completely etched, the second insulating layer 14 below is exposed and the gate material on the region where the gate is to be formed, that is, the upper portion of the first insulating layer ( 16) remains.

On the other hand, in the present invention, in the process of Figure 2b, by using a CMP (Chemical Mechanical Polishing) process to remove and planarization, it is also possible to perform a subsequent process.

FIG. 2G shows the left and right second insulating layers of the gate material 16 of the region where the gate is to be formed, except for the gate material 16 of the region where the gate is to be formed in FIG. 2F. The state after etching (14) is shown.

When the second insulating layer 14 is etched, portions of both sides 13 ′ and 13 ″ of the first insulating layer are exposed to the left and right sides 112 ′ and 112 of the gate material 16 in the region where the gate is to be formed.

By removing portions (13 ', 13 ") of both sides of the first insulating film exposed to the left and right sides of the gate material 16 and doping the source and the drain, the dual gate field effect transistor of the present invention is finally completed. (FIG. 2H)

3 is a cross-sectional view taken along the line AA ′ of FIG. 2H, FIG. 4 is a cross-sectional view taken along the line B-B ′ of FIG. 2H, and FIG. 5 is a cross-sectional view taken along the line C-C ′ of FIG. 2H. Wow; A source and a drain region formed of single crystal silicon on the insulator and spaced apart from each other with one area interposed therebetween; A channel connecting the source and drain spaced apart from each other across a portion of the area, the channel being formed of single crystal silicon on the insulator; An insulating film formed on the channel; Gate insulating films formed on both sides of the channel and on each side of the source and drain regions; Each cross-sectional view of the dual gate MOSFET of the present invention is formed of a gate insulating film and a gate formed to be stacked on an upper surface of the insulating film and covering the channel.

As shown in FIG. 5, the double gate MOSFET of the present invention is formed by enclosing the gate 16 between the left and right sides of the channel 12 'with the gate insulating layers 15 and 15' interposed therebetween. The channel can be controlled by the gate area of the right side, which can serve as a double gate.

In addition, the conventional polycrystalline silicon is deposited to form source and drain regions, and the fins connected to the source and drain regions form an increase in resistance generated by forming single crystal silicon. It can be formed as a single monocrystalline silicon can be reduced as much as possible.

In order to form a gate electrode of a conventional small size, as shown in FIGS. 1A to 1C, after forming a spacer using the nitride film 5, a gate 6 is formed to form a fin 3. In the present invention, damage to the portion of the pin 3 due to excessive etching for removing the spacer of the nitride film 5 formed on the side surface can be prevented.

Second Embodiment

As shown in FIG. 6 showing the second embodiment of the double gate MOSFET of the present invention, in the process of etching the second insulating film 14 in the region where the gate is to be formed in FIG. 2C, the etching selection with the first insulating film 13 is performed. If the ratio is bad, the first insulating layer 13 may be excessively etched, which may cause a problem that the first insulating layer 13 does not serve as a sufficient mask.

Therefore, in order to solve such a problem, instead of using the first insulating film 13 of FIG. 2A as a single channel so as to act as a channel mask and a mask of the second insulating film, as shown in FIG. 6, silicon is etched. The dual gate electric field effect of the present invention is formed by forming a double stacked structure having a first selector 113 having a high selectivity below and a second interposer 113 'having a high etching selectivity above the second insulating layer 14. It is desirable to manufacture transistors.

Accordingly, the first material 113 is formed of a silicon oxide film or a silicon nitride film to act as a mask when etching single crystal silicon 12, and the second material 113 ′ is formed of polycrystalline silicon or amorphous silicon to form a second film. It is more preferable to form a stacked structure of the polycrystalline / amorphous silicon 113 ′ and the silicon oxide film / nitride film 113 to serve as a mask when etching the insulating film 14.

Third Embodiment

According to the third embodiment of the present invention, as shown in FIG. 7A, a plurality of fine patterns formed by the first insulating layer 13 are formed to be spaced apart from each other, and subsequent processes are performed. You can configure more than one.

In addition, as shown in FIG. 8, the width d3 of the first insulating film fine pattern, the gap d2, and the thickness d1 of the single crystal silicon are made the same size, and the area on the wafer as in the conventional planar element is reduced. While occupying, the same magnitude of current can flow.

Here, when the process margin is sufficient, the thickness d1 of the single crystal silicon may be slightly larger than the width d3 and the interval d2 of the first insulating film fine pattern. That is, when the upper and lower widths d1 of the channel are formed larger than the left and right widths d3 or the interval d2 between the channels, there is an advantage in that the degree of integration can be increased compared to the conventional planar MOSFETs occupying the same area.

FIG. 9 is a cross-sectional view taken along the line D-D 'of FIG. 7B showing a state in which the double gate field effect transistor finally completed according to the third embodiment of the present invention is completed, and the oxide film 11 is formed on the silicon substrate 10. FIG. Is formed, and a gate 16 is formed on the oxide film 11, and a multilayer structure of a plurality of channels 12 'and a first insulating film 13 is formed inside the gate 16. . In addition, gate insulating layers 15 and 15 'exist between the gate 16 and the plurality of channels 12'.

The dual gate MOSFET of the present invention can form a source / drain region in which the single crystal silicon of the portion in which the gate other than the channel portion is present is self-aligned removed by using the single crystal silicon of the SOI substrate, and the gate of the device to be fabricated. It is possible to achieve a structure having a thin channel portion that is approximately the same length as the size, and a front / rear gate that is self-aligned on both sides of the channel portion.

In the present invention, since the portion to be the source / drain pad is used as the single crystal silicon portion on the buried oxide film in the SOI substrate, the contact resistance between the polycrystalline silicon and the fin, which has been a problem in the conventional device, can be reduced, and the nitride film spacer ( Since there is no spacer, there is an effect that can prevent damage to the pin portion that becomes the channel.

In addition, the present invention has the effect that it is possible to manufacture the front / rear gates in a self-aligned, and to implement a microchannel double gate MOSFET having an improved current driving capability while maintaining a low parasitic resistance of the transistor due to the thin channel.

In addition, the current driving capability is higher than that of the MOSFET of the same area, and it is suitable as an element to be used in the next generation system.

Although the present invention has been described in detail only with respect to specific examples above, it will be apparent to those skilled in the art that various modifications and variations are possible within the spirit of the present invention, and such modifications and modifications belong to the appended claims.

Claims (14)

An insulator stacked on the semiconductor substrate; A source and a drain region formed of single crystal silicon on the insulator and spaced apart from each other with one area interposed therebetween; A channel connecting the source and drain spaced apart from each other across a portion of the area, the channel being formed of single crystal silicon on the insulator; An insulating film formed on the channel; Gate insulating films formed on both sides of the channel and on each side of the source and drain regions; And a gate formed on the gate insulating layer and the insulating layer, the gate surrounding the channel and stacked on an area between the source and drain regions. The double gate MOSFET of claim 1, wherein the semiconductor substrate is a silicon substrate, and the insulator is a silicon oxide film. The dual gate MOSFET of claim 1, wherein at least two channels are spaced apart from each other. The dual gate MOSFET of claim 3, wherein the upper and lower widths of the channel are larger than the horizontal width and the gap between the channels. 2. The double gate MOSFET of claim 1, wherein the gate material is any one selected from metal, polycrystalline silicon and amorphous silicon. 2. The double gate MOSFET of claim 1, wherein the gate insulating film is any one selected from a silicon oxide film, a nitrided oxide film, and a high dielectric constant insulating film. A first step of forming a fine pattern of a first insulating film made of a silicon oxide film or a silicon nitride film in a portion of the SOI substrate to be a channel of single crystal silicon; A second step of depositing a second insulating film on top of the fine pattern of the single crystal silicon and the first insulating film, and then removing the second insulating film of the portion where the gate is to be formed with a fine line width; A third step of exposing the buried oxide film by removing the single crystal silicon of the portion where the gate is to be formed using the fine patterns of the second insulating film and the first insulating film as a mask; A fourth step of growing a gate insulating film in the single crystal silicon portion exposed by the removal of the single crystal silicon in the portion where the gate is to be formed; Depositing a gate material on the first insulating film and the buried oxide film including the gate insulating film; A sixth step of etching the gate material formed on the second insulating film to expose the second insulating film, and leaving the gate material on the first insulating film; Selectively removing the exposed second insulating layer to expose single crystal silicon to the left and right of the gate material; And an eighth step of doping the dopant to use the source / drain electrodes in the left and right single crystal silicon. 8. The second insulating film of a portion, in which the gate is to be formed, in the second step, so that the first insulating film is exposed only a portion of an inner portion thereof and a portion of both sides thereof is surrounded by the second insulating film. 1 is removed smaller than the length of the fine pattern of the insulating film; In the seventh step, selectively removing the second insulating film so that portions of both sides of the first insulating film are exposed to the left and right sides of the gate material; And removing a portion of both sides of the first insulating film exposed to the left and right sides of the gate material between the seventh and eighth steps. The method of claim 7, wherein the first insulating film of the first step of forming a fine pattern of the first insulating film in a portion to be the channel of the single crystal silicon is etched with respect to the second insulating film on the silicon oxide film or the silicon nitride film. A method for manufacturing a double gate MOSFET, characterized in that the second material having an excellent selectivity is further deposited. 10. The method of claim 9, wherein the second material is polycrystalline silicon or amorphous silicon. 8. The method of claim 7, wherein the gate material of the fifth step is a metal. 8. The method of claim 7, wherein the gate material of the fifth step is polycrystalline silicon or amorphous silicon; The eighth step further includes the step of doping the gate material with an n-type dopant or a p-type dopant. 8. The method of claim 7, wherein in the eighth step, doping of the dopant for using the source / drain electrodes in the left and right single crystal silicon is performed by varying the energy to obtain a uniform impurity distribution in the depth direction of the left and right single crystal silicon. A method of manufacturing a double gate MOSFET, characterized in that the dopant is implanted in a plurality of ion implantation processes. The method of claim 7, wherein the second step, After the flattening of the second insulating film formed on the first insulating film by the deposition of the second insulating film on the fine pattern of the single crystal silicon and the first insulating film by using a CMP process to planarize, 2 A method for manufacturing a double gate MOSFET, wherein the insulating film is removed at a fine line width.