KR100467817B1 - Method for preventing metal corrosion of semiconductor - Google Patents
Method for preventing metal corrosion of semiconductor Download PDFInfo
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- KR100467817B1 KR100467817B1 KR10-2003-0006408A KR20030006408A KR100467817B1 KR 100467817 B1 KR100467817 B1 KR 100467817B1 KR 20030006408 A KR20030006408 A KR 20030006408A KR 100467817 B1 KR100467817 B1 KR 100467817B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32138—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only pre- or post-treatments, e.g. anti-corrosion processes
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Abstract
본 발명의 목적은 에칭 후 SOG 막을 증착하여 외부의 수분기와의 반응을 차단함으로써 금속 배선의 부식 방지와 자체 저항 및 콘택 저항의 증가를 억제할 수 있는 반도체 소자의 금속 배선 부식 방지 방법을 제공함에 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for preventing corrosion of metal wires in a semiconductor device capable of suppressing corrosion of metal wires and increasing self-resistance and contact resistance by blocking the reaction with external moisture groups by depositing an SOG film after etching. .
이에 본 발명은 플라즈마 건식 식각 공정을 통해 웨이퍼 상에 형성한 금속 배선을 후처리하는 방법에 있어서, 식각공정 후 진공상태에서 소자의 금속배선 상에 SOG 막질을 증착하여 Cl 성분을 희석시키는 제1공정과; 소자의 금속배선 상에 증착된 SOG 막질을 제거하여 Cl 잔유물을 제거하는 제공정; 금속 배선에 잔류하는 레지스트를 제거하는 제3공정을 포함하는 반도체 소자의 금속배선 부식 방지방법을 제공한다.Accordingly, the present invention is a method of post-processing a metal wiring formed on a wafer through a plasma dry etching process, the first step of diluting the Cl component by depositing SOG film on the metal wiring of the device in a vacuum state after the etching process and; Providing a Cl residue by removing SOG film deposited on the metallization of the device; Provided is a method for preventing corrosion of metal wiring in a semiconductor device, including a third step of removing resist remaining on the metal wiring.
Description
본 발명은 본 발명은 반도체 소자의 금속 배선 부식 방지방법에 관한 것으로, 더욱 상세하게는 패터닝한 알루미늄 합금 계열의 금속 배선을 후처리하여 부식을 방지할 수 있도록 된 반도체 소자의 금속 배선 부식 방지 방법에 관한 것이다.The present invention relates to a method for preventing corrosion of metal wires in semiconductor devices. More particularly, the present invention relates to a method for preventing corrosion of metal wires in semiconductor devices that can prevent corrosion by post-processing patterned aluminum alloy-based metal wires. It is about.
잘 알려진 바와 같이, 반도체 소자를 제조하는데 있어서는 다양한 형태의 금속 배선(예를 들면, 알루미늄 합금 금속 배선)을 형성하기 위한 식각 공정(또는 패터닝 공정)을 필요로 하는데, 알루미늄 합금을 임의의 패턴으로 식각하여 금속 배선을 형성하는 전형적인 식각 공정으로는 플라즈마를 이용하는 건식 식각 공정이 있다.As is well known, the manufacture of semiconductor devices requires etching processes (or patterning processes) to form various types of metal interconnects (eg, aluminum alloy metal interconnects), which etch aluminum alloys in arbitrary patterns. A typical etching process for forming metal wirings is a dry etching process using plasma.
금속배선용 금속층의 건식식각은 주식각 가스로 BCl3, Cl2, SF6등을 사용한다. BCl3의 'B'는 일반적으로 폴리머를 잘 형성하므로 알루미늄 식각시 알루미늄 식각부위에 폴리머로 이루어진 측벽을 형성하고, SF6의 'F'는 배리어 금속을 제거하는 주식각제로 사용되고, Cl2는 알루미늄을 제거하기 위한 주식각제로 이용된다.Dry etching of the metal layer for metal wiring uses BCl 3 , Cl 2 , SF 6, etc. as the stock angle gas. Since 'B' of BCl 3 generally forms a polymer well, it forms a polymer sidewall on an aluminum etched portion during aluminum etching, and 'F' of SF 6 is used as a staple remover for removing barrier metals, and Cl 2 is used as an aluminum It is used as a stock depreciation to remove
그러나, 배선형성을 위한 패터닝 직후의 알루미늄층의 노출 부위는 식각제에 포함된 염소기와 결합하여 AlxCly를 형성하여 노출 부위를 부식시키게 된다.However, the exposed portion of the aluminum layer immediately after patterning for wiring formation combines with the chlorine group included in the etchant to form AlxCly to corrode the exposed portion.
즉, 반도체 제조공정의 금속 배선 증착 공정에서 에칭 진행 후 포토레지스트 제거를 즉시 하지 않으면 알루미늄 배선에 부식 문제가 발생하게 된다.In other words, if the photoresist is not removed immediately after the etching process in the metal wiring deposition process of the semiconductor manufacturing process, corrosion problems occur in the aluminum wiring.
이는 에칭시에 사용하는 가스인 Cl2가 알루미늄과 반응하여 AlCl3형태의 화합물로 변하게 되는 데 에칭후 대기중에 노출되게 되면 대기중의 수분기(H2O)와 반응하여 부식이 진행하게 되는 것이다.This is because the gas used for etching Cl 2 reacts with aluminum to change into an AlCl 3 type compound, and when it is exposed to the atmosphere after etching, it reacts with atmospheric water (H 2 O) to cause corrosion. .
따라서 보통 진공상태에서 바로 포토레지스트 제거를 실시하는 것이 일반적이다.Therefore, it is common to perform photoresist removal immediately under vacuum.
즉, 상기한 바와 같이 플라즈마 건식 식각 공정 후에 금속 배선의 표면에 잔류하는 부식 요인을 제거하는 종래의 방법으로는 H2O 플라즈마와 O2플라즈마를 이용하는 방법이 주로 사용된다.That is, as described above, as a conventional method of removing the corrosion factor remaining on the surface of the metal wiring after the plasma dry etching process, a method using H 2 O plasma and O 2 plasma is mainly used.
상기한 종래 방법은 웨이퍼 상에 형성된 알루미늄 합금을 염소계(Cl2, BCl3) 플라즈마를 이용한 건식 식각으로 패터닝하여 금속 배선을 형성한 후, 인-시튜(in situ)로 금속 배선의 표면에 잔류하는 Cl을 제거하기 위하여, H2O 플라즈마를 사용하여 의도적으로 HCl을 형성한 후에 펌핑으로 배기하고, 이어서 O2플라즈마를 이용하여 금속 배선의 표면에 잔류하는 레지스트를 제거한다.According to the conventional method, the aluminum alloy formed on the wafer is patterned by dry etching using a chlorine-based (Cl 2 , BCl 3 ) plasma to form a metal wiring, and then remaining on the surface of the metal wiring in situ. In order to remove Cl, HCl is intentionally formed using H 2 O plasma and then exhausted by pumping, followed by removal of the resist remaining on the surface of the metal wiring using O 2 plasma.
그러나, 상술한 바와 같은 종래의 금속 배선 후처리 방법은, H2O 플라즈마를 이용하기 때문에 O, H 라디칼이 발생하는데, 이러한 라디칼이 잔류하는 Cl과 반응하여 HCl을 형성하기 때문에 부식을 방지하고 레지스트를 제거할 수 있지만, 부식 방지 과정에서 레지스트 표면에 존재하는 폴리머와 반응함으로써 오히려 레지스트 표면이 산화되어 경화되는 현상이 야기되고, 이러한 레지스트의 경화는 후속하는 O2플라즈마 공정에서 레지스트가 완전히 제거되지 않는 문제점을 야기시켜, 완벽한 부식 방지를 실현할 수 없게 함으로써 반도체 소자의 신뢰성을 떨어뜨리는 요인으로 작용하고 있다.However, in the conventional metal wiring post-processing method as described above, O and H radicals are generated because H 2 O plasma is used, and these radicals react with remaining Cl to form HCl, thereby preventing corrosion and resisting. Can be removed, but reaction with the polymer present on the resist surface in the course of corrosion prevents the resist surface from being oxidized and cured, which hardening of the resist does not completely remove the resist in subsequent O 2 plasma processes. It causes a problem and makes it impossible to implement | achieve a complete corrosion protection, and it acts as a factor which reduces the reliability of a semiconductor element.
또한, 제조 장비상의 문제로 에칭 후 바로 대기 중에 공정 웨이퍼를 꺼내야 하는 경우도 발생하는 데, 이때에는 포토레지스트 제거가 즉시 이루어지지 않음으로써 부식이 발생할 우려가 있다.In addition, a problem arises in manufacturing equipment that requires the removal of the process wafer in the air immediately after etching, in which case the photoresist is not immediately removed, which may cause corrosion.
이에 본 발명은 상기와 같은 제반 문제점을 해결하기 위하여 안출된 것으로, 에칭 후 SOG 막을 증착하여 외부의 수분기와의 반응을 차단함으로써 금속 배선의 부식 방지와 자체 저항 및 콘택 저항의 증가를 억제할 수 있는 반도체 소자의 금속 배선 부식 방지 방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, by depositing a SOG film after etching to block the reaction with the external moisture groups to prevent corrosion of the metal wiring and increase of the self-resistance and contact resistance can be suppressed. It is an object of the present invention to provide a method for preventing corrosion of metal wires in semiconductor devices.
도 1a 및 도 1c는 본 발명의 금속배선 부식 방지방법에 따른 각 공정의 개략적인 공정단면도이다.1A and 1C are schematic process cross-sectional views of each process according to the metal wire corrosion prevention method of the present invention.
상기한 바와 같은 목적을 달성하기 위하여 본 발명은,The present invention to achieve the above object,
플라즈마 건식 식각 공정을 통해 웨이퍼 상에 형성한 금속 배선을 후처리하는 방법에 있어서,In the method of post-processing a metal wiring formed on the wafer through a plasma dry etching process,
식각공정 후 진공상태에서 소자의 금속배선 상에 SOG 막질을 증착하여 Cl성분을 희석시키는 제1공정과,A first step of diluting Cl component by depositing SOG film on the metal wiring of the device in a vacuum state after the etching process;
소자의 금속배선 상에 증착된 SOG 막질을 제거하여 Cl 잔유물을 같이 제거하는 제2공정,A second process of removing the Cl residues by removing the SOG film deposited on the metal wiring of the device;
금속 배선에 잔류하는 레지스트를 제거하는 제3공정을 포함한다.And a third step of removing the resist remaining in the metal wiring.
여기서 상기 제1공정은 동일 장비 내에서 챔버만을 옮겨 진행시킴으로써 진공상태를 그대로 유지시킴이 바람직하다.Here, the first step is preferably to maintain the vacuum state by moving only the chamber in the same equipment.
그리고 상기 SOG 막질의 두께는 약 50 - 100Å로 이루어짐이 바람직하다.And the thickness of the SOG film is preferably made of about 50 ~ 100Å.
또한, 상기 제2공정은 CF4, O2가스를 사용하여 플라즈마 처리함이 바람직하다.In addition, the second process is preferably plasma treatment using CF 4 , O 2 gas.
또한, 상기 제3공정은 H2O, O2/N2가스를 사용하여 플라즈마 처리함이 바람직하다.In addition, the third step is preferably plasma treatment using H 2 O, O 2 / N 2 gas.
이하 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 및 도 1c는 본 발명의 금속배선 부식 방지방법에 따른 각 공정의 개략적인 공정단면도이다.1A and 1C are schematic process cross-sectional views of each process according to the metal wire corrosion prevention method of the present invention.
여기서 본 발명의 핵심 기술요지는, 물에 잘 분해되는 Cl 성분을 희석시키기 위하여 액체성 성질을 띄는 SOG 막질을 에칭공정 후 바로 증착시킨다는 것이다.A key technical aspect of the present invention is to deposit a SOG film having a liquid property immediately after the etching process in order to dilute the Cl component that is well decomposed in water.
먼저, 알루미늄 배선 형성공정을 살펴보면, 반도체기판인 실리콘기판상에 소자 또는 하부배선 등이 형성된 하지층과의 층간절연을 위한 층간절연층을 산화막 등으로 형성한 다음, 하부 배리어(barrier)층을 층간절연층상에 스퍼터링(sputtering) 등으로 소정 두께로 증착하여 형성한다.First, referring to the aluminum wiring forming process, an interlayer insulating layer for interlayer insulation with an underlayer on which a device or a lower wiring is formed on a silicon substrate, which is a semiconductor substrate, is formed of an oxide film or the like, and then a lower barrier layer is interlayered. It is formed by depositing a predetermined thickness on the insulating layer by sputtering or the like.
그리고, 하부배리어층 상에 금속배선의 주재료인 금속층을 알루미늄 등을 역시 스퍼터링으로 증착하여 형성한다. 이때, 증착되는 금속층의 두께는 일반적으로 하부배리어층 보다 두껍게 형성한다. 그 다음, 금속층 상에 상부배리어층을 스퍼터링 등의 방법으로 소정의 두께로 증착하여 형성한다. 그리고, 상부배리어층 상에 포토레지스트를 도포한 다음 금속배선 형성용 마스크를 사용한 노광 및 현상을 실시하여 식각될 부위를 노출시키는 포토레지스트패턴을 상부배리어층 상에 형성한다.Then, a metal layer, which is a main material of metal wiring, is formed on the lower barrier layer by vapor deposition of aluminum or the like. At this time, the thickness of the deposited metal layer is generally formed thicker than the lower barrier layer. Then, an upper barrier layer is formed on the metal layer by deposition to a predetermined thickness by a method such as sputtering. Then, a photoresist is applied on the upper barrier layer, followed by exposure and development using a mask for forming a metal wiring to form a photoresist pattern on the upper barrier layer to expose a portion to be etched.
다음으로 BCl3등을 건식식각제로 이용하는 건식식각을 노출된 상부배리어층에 실시하여 포토레지스트패턴으로 보호되지 않는 부위의 상부배리어층을 제거한다. 따라서, 알루미늄으로 이루어진 금속층의 표면이 노출된다.Next, dry etching using BCl 3 or the like as a dry etching agent is performed on the exposed upper barrier layer to remove the upper barrier layer of the portion not protected by the photoresist pattern. Thus, the surface of the metal layer made of aluminum is exposed.
그 다음, 포토레지스트패턴과 잔류한 상부배리어층을 식각마스크로 이용하고 알루미늄 식각을 위한 식각제로 BCl3과 Cl2가스를 사용하여 노출된 알루미늄 금속층을 제거하여 하부배리어층의 표면을 노출시킨다. 따라서, 잔류한 알루미늄 금속층을 금속배선의 주재료로 하는 배선 패턴이 형성된다. 잔류한 포토레지스트패턴, 잔류한 상부배리어층 및 잔류한 금속층을 식각마스크로 이용하고 BCl3과 Cl2를 식각가스로 사용하여 노출된 하부배리어층을 제거하여 잔류한 금속층 하부에만 하부배리어층을 잔류시킨다.Next, the surface of the lower barrier layer is exposed by removing the exposed aluminum metal layer using the photoresist pattern and the remaining upper barrier layer as an etch mask and using BCl 3 and Cl 2 gas as etching agents for aluminum etching. Thus, a wiring pattern is formed in which the remaining aluminum metal layer is the main material of the metal wiring. Using the remaining photoresist pattern, the remaining upper barrier layer and the remaining metal layer as an etch mask, and using BCl 3 and Cl 2 as an etching gas, the exposed lower barrier layer is removed, leaving the lower barrier layer only below the remaining metal layer. Let's do it.
따라서, 잔류한 상부배리어층/금속층/하부배리어층으로 이루어진 금속배선 패턴이 완성된다. 이때, 포토레지스트는 아직 상부배리어층상에 잔류한다.Thus, the metal wiring pattern composed of the remaining upper barrier layer / metal layer / lower barrier layer is completed. At this time, the photoresist still remains on the upper barrier layer.
이 상태는 도 1a에 잘 예시되어 있는 데, 도시된 바와 같이 Cl- 잔류가 알루미늄 금속층(10) 표면에 흡착되어 있게 된다.This state is well illustrated in FIG. 1A, where Cl − residues are adsorbed onto the surface of the aluminum metal layer 10 as shown.
여기서 본 발명은 상기와 같은 에칭공정이 끝난 상태에서 반도체 소자를 식각챔버에서 동일장비상의 막질 증착용 챔버로 이동시키고 SOG 막질을 증착하는 과정을 거친다.In the present invention, the semiconductor device is moved from the etching chamber to the film deposition chamber on the same equipment in the state where the etching process is completed, and the SOG film is deposited.
이때, 챔버 내의 진공상태는 그대로 유지한다.At this time, the vacuum state in the chamber is maintained as it is.
도 1b는 반도체 소자의 금속층(10)과 상부 포토레지스트(20)에 SOG 막질(30)이 코팅되어 있는 상태를 예시하고 있다.FIG. 1B illustrates a state in which the SOG film quality 30 is coated on the metal layer 10 and the upper photoresist 20 of the semiconductor device.
증착되는 SOG 막질(30)은 SiO2계열이 사용되며 코팅되는 두께는 약 50 - 100Å정도이다.As the SOG film 30 to be deposited, SiO 2 series is used and the coating thickness is about 50 to about 100 mm 3.
이와같이 코팅되는 SOG 막질은 여러 가지 산화막질 중에서도 액체성 성질을 띄기 때문에 물에 잘 분해되는 Cl성분을 희석시키는 작용을 하게 된다. 따라서 자연히 금속층 표면에 흡착되어 있는 Cl-가 희석되어 지며 결국 상기 막질은 외부의수분기를 차단하는 역할을 수행함으로써 알루미늄의 부식 반응을 방지하게 되는 것이다.The coated SOG film has a liquid property among various oxide films, so that the Cl component decomposes well in water. Therefore, Cl- which is naturally adsorbed on the surface of the metal layer is diluted, and thus the film quality serves to prevent external corrosion of water, thereby preventing the corrosion reaction of aluminum.
다음 공정으로 상기 반도체 소자를 포토레지스트 제거장비로 이동하여 두단계에 걸쳐 금속층 상부의 포토레지스트를 제거하게 된다.In the next process, the semiconductor device is moved to a photoresist removing apparatus to remove photoresist on the metal layer in two steps.
먼저 일단계는 전체적으로 덮여 있는 SOG 막질(30)을 제거하는 과정으로 CF4, O2가스를 사용한 플라즈마 에칭처리를 통해 막질을 제거한다.First, the first step is to remove the entire SOG film (30) covered by the plasma etching process using a CF 4 , O 2 gas to remove the film.
이때 SOG와 결합된 Cl 잔유물들도 SOG 막질과 함께 제거된다.Cl residues combined with SOG are also removed together with the SOG film.
다음 단계로 H2O, O2/N2가스 등을 사용하여 플라즈마 건식식각을 실시함으로써 금속층(10) 상부의 포토레지스트(20)를 제거한다.As a next step, plasma dry etching is performed using H 2 O, O 2 / N 2 gas, or the like to remove the photoresist 20 on the metal layer 10.
따라서 상기의 과정을 통해 Cl 잔류를 깨끗이 제거할 수 있게 되어 Al-Cl 반응에 의한 알루미늄의 부식은 발생하지 않게 되는 것이다.Therefore, it is possible to cleanly remove the Cl residue through the above process so that the corrosion of aluminum by Al-Cl reaction does not occur.
이상 설명한 바와 같은 본 발명에 따른 반도체 소자의 금속배선 부식 방지방법에 의하면, 에칭공정과 포토레지스트 제거 공정 사이에 SOG 막질을 코팅하여 Cl 잔류를 제거하는 공정을 포함시킴으로써 반도체 소자의 금속 배선에 대한 완벽한 부식 방지를 실현할 수 있어 반도체 소자의 신뢰성 및 수율을 증진시킬 수 있다.According to the method for preventing corrosion of metal wires of a semiconductor device according to the present invention as described above, a process of removing Cl residue by coating SOG film quality between an etching process and a photoresist removal process is completed. Corrosion prevention can be realized, so that the reliability and yield of the semiconductor device can be enhanced.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05211146A (en) * | 1991-11-18 | 1993-08-20 | Matsushita Electric Ind Co Ltd | Corrosion protecting method of metal wiring |
| KR19990005866A (en) * | 1997-06-30 | 1999-01-25 | 김영환 | Interlayer planarization method of semiconductor device |
| KR100241529B1 (en) * | 1996-12-12 | 2000-02-01 | 김영환 | Method for preventing corrosion of metal wiring in semiconductor device using plasma |
| KR20040025163A (en) * | 2002-09-18 | 2004-03-24 | 아남반도체 주식회사 | Method for preventing metal-corrosion in the metal-etch process |
| KR20040069856A (en) * | 2003-01-30 | 2004-08-06 | 아남반도체 주식회사 | Method for preventing metal corrosion of semiconductor |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05211146A (en) * | 1991-11-18 | 1993-08-20 | Matsushita Electric Ind Co Ltd | Corrosion protecting method of metal wiring |
| KR100241529B1 (en) * | 1996-12-12 | 2000-02-01 | 김영환 | Method for preventing corrosion of metal wiring in semiconductor device using plasma |
| KR19990005866A (en) * | 1997-06-30 | 1999-01-25 | 김영환 | Interlayer planarization method of semiconductor device |
| KR20040025163A (en) * | 2002-09-18 | 2004-03-24 | 아남반도체 주식회사 | Method for preventing metal-corrosion in the metal-etch process |
| KR20040069856A (en) * | 2003-01-30 | 2004-08-06 | 아남반도체 주식회사 | Method for preventing metal corrosion of semiconductor |
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