KR100461545B1 - Method for Generating and Detecting Synchronisation Codes of Synchronisation Channel - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

In a CDMA asynchronous mobile communication system, a method for generating and detecting a synchronization code used to acquire synchronization for a communication system signal so that a mobile station can demodulate transmitted channels from a communication system.

2. The technical problem to be solved by the invention

It is possible to generate and detect synchronization codes with efficient synchronization detection probability even in the presence of high frequency offset, as in satellite mobile system environments, and to generate and detect synchronization codes with excellent performance in synchronous coupling in terrestrial mobile communication systems. Provides sync code generation and detection method.

3. Solution summary of invention

Default Golay Code Step 1, construct Golay code to generate A second step of generating a and the generated basic Golay code And configuration Golay code Based on the first hierarchical Golay code expressed as or It provides a synchronization code generation method comprising a third step of generating a.

4. Important uses of the invention

Used for CDMA asynchronous mobile communication system.

Description

Method for Generating and Detecting Synchronization Code of Synchronization Channel {Method for Generating and Detecting Synchronization Codes of Synchronization Channel}

According to the present invention, a synchronization code generation of a synchronization channel (Synchronization CHannel, SCH) used in a code division multiple access (CDMA) asynchronous mobile communication system to obtain synchronization for a signal transmitted from a communication system by a mobile station And a detection method.

The sync channel is broadcasted to facilitate synchronization acquisition of the primary scrambling code commonly applied to the downlink channel in an asynchronous CDMA system, where a predefined sync code is periodically transmitted from the communication system to the mobile stations through the sync channel. Broadcasted by

The technical standard of the 3rd Generation Partnership Project (3GPP) defines an asynchronous CDMA technical standard for application in third-generation terrestrial mobile communication systems, as defined in Technical Specifications (TS) 25.211, 25.213 and 25.214. The document discloses a structure of a synchronization channel, a structure of a synchronization code, and a synchronization acquisition procedure.

In an asynchronous CDMA system, a synchronization channel has one radio frame section consisting of 15 slot sections, and each slot section has a length of 2560 chips. The sync channel is classified into a primary sync channel and a secondary sync channel.

In the primary synchronization channel, a primary synchronization code (PSC) having a length of 256 chips is periodically transmitted at the beginning of each slot interval. Only one PSC is defined and the same in all slot intervals of all cells of an asynchronous CDMA system.

In the secondary synchronization channel, a secondary synchronization code (SSC) of the same length as the PSC is transmitted at the beginning of each slot interval equal to the transmission time of the PSC. SSCs are different from each other in 15 slot intervals corresponding to one radio frame interval, and 15 different SSCs transmitted in each slot interval constitute an SCC sequence. The SCC sequence is repeated every one radio frame period, and the SCC sequence used for each cell may be different. These different SCC sequences correspond one-to-one with a specific group to which a pilot code used in a cell belongs.

The PSC is created by hierarchically combining two different Golay codes with a length of 16 chips.

The SSC is generated by a secondary Golay code having characteristics complementary to the Golay code used for the PSC. The 16 second SSCs are generated by multiplying the second Golay code by 16 Hadamard codes having a length of 256 chips, and the SCC sequence is generated by arranging them into 15 different codes. In this case, the Hadamard code that distinguishes 16 SSCs is repeated with the same +1 or -1 chip every 16 chips. Thus, when detecting an SSC, a 16-chip length Golay is used regardless of the type of Hadamard code. The code can be detected.

In an asynchronous CDMA system, the mobile station must initially perform synchronization acquisition for pilot codes used in cells that are in close proximity when attempting to connect to the system and in case of handoff, and the synchronization channel is used in this synchronization acquisition process. The mobile station recognizes the start time of the slot interval by detecting the PSC broadcast in the slot interval period in the primary synchronization channel. Next, the mobile station detects an SCC sequence that is broadcasted in a radio frame section in a secondary synchronization channel to recognize a start point of the radio frame section and a group to which a pilot code of a corresponding cell belongs. The mobile station detects the pilot code used in the corresponding cell from the recognized pilot code group and the start of the frame interval and acquires synchronization.

As such, when synchronization is obtained for the pilot code, a main channel such as a control channel broadcast in the corresponding cell may be received.

However, in the asynchronous satellite mobile communication system, Doppler Shift of several tens of KHz occurs due to the movement of satellites, and thus frequency offset of several tens of KHz between the center frequency of the carrier broadcast from the satellite and the reception frequency of the mobile station. There is a problem that the mobile station is limited to the maximum length that can be synchronized in the process of receiving the synchronization code.

For example, when there is a frequency offset of 10 to 15 KHz and the chip rate is 3 to 4 Mchip / s, the 256 chip length synchronous coupling significantly reduces the synchronization detection probability than the 128 chip length synchronous coupling.

In addition, reducing the sync coupling length to 64 chips results in poor detection performance over 128 chip sync coupling in the small frequency offset range. As such, when there is a frequency offset of up to 15 KHz, the 128 chip length becomes the appropriate synchronous coupling length.

Therefore, the primary and secondary sync codes of the conventional asynchronous CDMA system, which is a terrestrial mobile communication system, are designed to have excellent performance in 256 chip synchronous coupling. In a satellite mobile system environment where elements that are not a major consideration in a mobile communication system, 128 chip length primary and secondary sync codes having excellent performance in 128 chip synchronous coupling need to be designed.

In addition, in order to generate the primary and secondary sync codes using the 128-chip long sync code for the 128-chip sync coupling in the satellite mobile communication system, the Hadamard code necessary for generating the SCC sequence also needs to be changed. That is, as described above, the Hadamard code used in the conventional asynchronous CDMA system is a structure that is identically repeated for 16 chips, which is the basic configuration Golay code length, and has a length of 256 chips. In order to apply the combination, a Hadamard code of 128 chips in length is designed for a 128-chip sync code, and a Hadamard code in which the same chip is repeated during a chip section corresponding to the length of a basic Golay code is detected. can do.

Accordingly, the present invention has an efficient synchronization detection probability even in an environment where a high frequency offset exists, such as in a satellite mobile system environment, by a 128- and 256-chip sync code by a basic Golay code, a configuration Golay code, and a Hadamard code. The purpose of the present invention is to provide a synchronization code generation and detection method as well as a synchronization code generation and detection method capable of generating and detecting a synchronization code having excellent performance in synchronous coupling in a terrestrial mobile communication system.

Those skilled in the art to which the present invention pertains can readily recognize other objects and advantages of the present invention from the drawings, the description of the invention, and the claims.

1 is a schematic diagram for explaining generation of a primary sync code according to an embodiment of the present invention;

2 is a schematic diagram for explaining generation of a secondary sync code according to an embodiment of the present invention;

3 is a timing diagram illustrating the transmission of a sync code generated according to an embodiment of the present invention;

4 is a block diagram of an apparatus for generating a basic code used for generating a sync code according to an embodiment of the present invention;

5 is a configuration diagram of an apparatus for generating a configuration code used for generating a primary sync code according to an embodiment of the present invention;

6 is a block diagram of a configuration code generating apparatus used for generating a secondary sync code according to an embodiment of the present invention;

7 is a block diagram of a 256-chip primary sync code detection apparatus according to an embodiment of the present invention;

8 is a block diagram of a 128-chip primary sync code detection apparatus according to another embodiment of the present invention;

9 is a block diagram of a 256-chip secondary sync code detection apparatus according to an embodiment of the present invention;

10 is a block diagram of a 128-chip secondary sync code detection apparatus according to another embodiment of the present invention;

11 is a block diagram of a 256-chip secondary sync code detection apparatus according to another embodiment of the present invention;

12 is a block diagram of a 128-chip secondary sync code detection apparatus according to another embodiment of the present invention.

In order to achieve the above object, the present invention provides a synchronization code generation method for a synchronization channel used by a mobile station for synchronization acquisition in an asynchronous mobile communication system. Step 1, construct Golay code to generate A second step of generating a and the generated basic Golay code And configuration Golay code Based on the first hierarchical Golay code expressed as or It provides a sync code generation method comprising a third step of generating a.

According to the present invention, the 128-chip primary sync code generated by the 16-chip basic Golay code and the 8-chip component Golay code is effective in the environment where high frequency offset exists as in the satellite mobile system environment. It is possible to generate and detect a synchronization code having a synchronization detection probability, as well as to achieve excellent synchronization in a terrestrial mobile communication system by a 256-chip primary sync code generated by concatenating two 128-chip primary sync codes. Capable of generating and detecting sync codes with performance.

Also, according to the present invention, a 256-chip long hierarchical Golay generated by a 16-chip long basic Golay code having a Golay complementary characteristic to a basic Golay code of a primary sync code and a 16-chip long component Golay code Code and 128-chip and 256-chip secondary sync codes generated by 256-chip Hadamard codes with the same chip repeated for 8 chip intervals and 128 chips repeated twice, as in the satellite mobile system environment. Synchronization code generation and detection with efficient synchronization detection probability is possible even in the presence of high frequency offset, as well as synchronization code generation and detection with excellent performance in synchronization combining in a land mobile communication system.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. If it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic diagram illustrating a configuration of a PSC according to an embodiment of the present invention. As shown in Fig. 1, the PSC is generated by a hierarchical Golay code generation method, and the sequence a ₁ and , a ₂ and Are hierarchically combined to generate a complex sequence having the same real and imaginary parts. A 256-chip PSC is constructed by concatenating two different 128-chip hierarchical Golay codes.

Each hierarchical Golay code has excellent aperiodic auto correlation properties for 128-chip synchronous coupling.

The basic Golay codes a ₁ and a ₂ of 16-chip length are constructed as in Equations 1 and 2 below.

Configuration of 8-chip length Golay codes α ₁ and α ₂ are constructed as shown in Equations 3 and 4 below.

The 128-chip first hierarchical Golay code C _P1 is generated by hierarchically forming the basic Golay code a ₁ and the constituent Golay code α ₁ as shown in Equation 5, and the 128-chip first hierarchical Golay code C _P2 Is generated by hierarchically configuring a basic Golay code a ₂ and a configuration Golay code α ₂ as shown in Equation (6).

The 256-chip PSC is generated as shown in Equation 7 by concatenating the first hierarchical Golay codes C _P1 and C _P2 .

Figure 2 is a schematic diagram for explaining the configuration of the SSC according to an embodiment of the present invention, as shown in the drawing, SSC is a complex code having the same real part and imaginary part, Hadamard code and hierarchical Golay code C _S Multiplication by position, that is, by chip multiplication.

The 256-chip SSC is constructed by hierarchically combining two different 16-chip basic Golay codes with a 16-chip long configuration Golay code. The basic Golay code for SSC generation has a complementary characteristic to the basic Golay code used for PSC generation. SSC is code that has excellent aperiodic cross correlation properties with PSC.

The basic Golay codes b ₁ and b ₂ having a length of 16 chips are inverted codes of the last 8 chip portions of a ₁ and a ₂ used in the PSC, and are constructed as shown in Equations 8 and 9.

A 16-chip long configuration Golay code β is constructed as shown in Equation 10.

The 256-layer long hierarchical Golay code C _S is hierarchically constructed as shown in Equation 11 by the basic Golay codes b ₁ and b ₂ and the configuration Golay code β.

On the other hand, the Hadamard code h _m of 256 chips long is generated from the Hadamard matrix H ₈ which is recursively generated as in Equation 12.

Hadamard matrix H ₈ is composed of 256 rows of 256 chips each row h _m as shown in equation (13) (m = 0 ~ 255).

SSC is for generating Hadamard codes h _m is a Hadamard matrix is obtained from the m-th row that satisfies the equation (14) in the H ₈ Hadamard code h _m has a length of 256 chips (i.e. ), The same chip is repeated every 8 chip sections, and the first 128 chip ( ) And the later 128 chips ( ) Has the same characteristics.

The kth SSC C _S ^k (k = 1, 2, ..., 16) is generated by the multiplication of 256 hierarchical Golay codes C _S of 256 chips and the chip-by-chip multiplication of Hadamard code h _m as do.

The SCC sequence is composed of N different SSC columns, and various kinds of sequences can be generated according to the arrangement of the SSCs. That is, the specific i-th SCC sequence [C _S ] _i may be configured as an array of N different C _S ^k as shown in Equation 16.

For example, if M SCC sequences [C _S ] _i composed of N different SSCs, C _S ^k , have M (i = 1, 2, ..., M), the M SCC sequences [C _S ] _i Is configured such that a cyclically shifted sequence is unique.

That is, T of the M SCC sequences [C _S ] _i ), Any one SCC sequence [C _S ] _i cyclically shifted by (t) of t M ( _{S S} ) sequences [C _S ] _i Is not equivalent to any one SCC sequence [C _S ] _i cyclically shifted by).

The configuration of the SCC sequence [C _S ] _i can be designed by the system designer in a predefined pattern through C _S ^k , which is SSC, and each SCC sequence [C _S ] _i corresponds to a pilot code group i so that the mobile station can By detecting the SCC sequence [C _S ] _i , it is possible to recognize the group to which the pilot code belongs.

3 is a timing diagram illustrating the transmission of a synchronization code according to an embodiment of the present invention. As shown in the figure, a primary synchronization channel includes a 256-chip demodulated code. PSC (C _P ') is transmitted every slot interval. The PSC is the same for each beam of communication system. The secondary synchronization channel is configured by repeatedly transmitting N SSCs (C _S ^k '), which are 256 chip length demodulated codes, for each radio frame period. In SSC (C _S ^{i, N} ') of FIG. 3, i means a scrambling code group number, and N means a slot number. Each SSC (C _S ^{i, N} ′) is selected from 16 (k = 1, 2, ..., 16) different 256 chip length codes. This sequence of secondary synchronization channels indicates to which code group the downlink scrambling code belongs.

The PSC and SCC sequences are transmitted by the timing as shown in FIG. The radio frame section is composed of N slot sections, and the 256-chip PSC (C _P ') is repeatedly transmitted in every slot section in the 256-chip section in front of each slot section. The SCC sequence is transmitted through the 256-chip section in front of the slot section with N SSCs (C _S ^k ) in a frame section according to a predefined pattern. In N SSCs, the nth sync code is transmitted in the first 256 chip sections of the nth slot section of every frame section.

Meanwhile, according to the present invention, instead of transmitting a 256-chip length sync code in the sync code transmission timing diagram shown in FIG. 3, a sync code having a 128 chip length may be transmitted. In this case, PSC (C _P ') is configured as shown in Equation 17 and has a 128-chip length.

or

PSC (C _P ′) generated by Equation 17 is shown in FIG. And It is expressed as

On the other hand, SSC (C _S ') is configured as shown in Equation 18 and has a 128-chip length.

or

SSC (C _S ') generated by Equation 18 is represented by C _S ' in FIG. In FIG. 2, C _S 'of the first half is It consists of, the second half of the C _S 'is It consists of.

Also, the kth SSC (C _S ^k ', k = 1,2, ..., 16) is a multiplication by chip with the code corresponding to 128 chips of the first half or the second half of the HSC (C _S ') and Hadamard code h _m . Is generated as shown in equation (19).

or

The k th SSC (C _S ^k ', k = 1, 2, ..., 16) generated by Equation 19 is represented by C _S ^k ' in FIG. In FIG. 2, the first half of C _S ^k 'is the first half SSC (C _S ') and the first half 128 chips of the Hadamard code h _m ( ) Is generated by multiplying each chip, and the latter C _S ^k 'is the second half SSC (C _S ') and the latter 128 chips (Hadamard code h _m ). ) By multiplying by chip.

According to an embodiment of the present invention, a 128-chip long sync code is transmitted, Is transmitted in the first half of each slot constituting a radio frame of the primary sync channel, the k-th SSC causes the first half C _S ^k 'of FIG. 2 to be transmitted in the same transmission interval, Is transmitted in the first half of each slot of the primary synchronization channel, the k-th SSC is preferably such that the second half C _S ^k ′ of FIG. 2 is transmitted in the same transmission interval.

The primary and secondary sync codes may be transmitted according to Quadrature Phase Shift Keying (QPSK). In this case, the same code may be transmitted in both the I channel and the Q channel. In this case, the phases of the carriers of the I channel and the Q channel have a 90 degree difference. In this case, the primary and secondary synchronization codes may be represented as Equations 20 and 21 as complex codes. The real part and the imaginary part of the complex code are transmitted through the I channel or the Q channel, respectively.

or

or

4 is a block diagram of a basic code generating apparatus used to generate a sync code according to an embodiment of the present invention. The Golay codes a ₁ , a ₂ , b ₁ , b ₂ , α ₁ , α ₂ and β which are used in the sync code may be generated by the Golay complementary sequence generator.

4 is a sequence generator 401 used to generate basic Golay codes a ₁ and b ₁ and / or a ₂ and b ₂ having complementary relationships to each other. The basic Golay codes a ₁ and b ₁ may be generated by the sequence generator 401 having the value of Equation 22 in FIG. 4.

In Equation 22, D ⁿ means a delay for n chips. A output in FIG. 4 corresponds to a ₁ code, and b ₁ is generated by inverting the last 8 chip portions of the a ₁ code.

The basic Golay codes a ₂ and b ₂ may be generated by the sequence generator 401 having a value as shown in Equation 23 in FIG. 4.

A output in FIG. 4 corresponds to a ₂ code, and b ₂ is generated by inverting the last 8 chip portions of the a ₂ code.

Figure 5 below is a sequence generating unit 501 is used to generate the configuration Golay code generation device that is configured Golay code α ₁ and α ₂ is used for the PSC configured according to one embodiment of the invention, the configuration Golay code α ₁ It is generated by the generating device 501 having the value of equation (24).

In addition, the configuration Golay code α ₂ is generated by the generating device 501 having the value of Equation 25 below.

In Fig. 5, codes corresponding to α ₁ and α ₂ are generated from the output α, respectively.

6 is a configuration Golay code generation device used for SSC configuration, that is, a sequence generation device 601 used to generate configuration Golay code β, and the configuration Golay code β is represented by Equation 26. It can be generated by the sequence generating device 601 having.

In Fig. 6, a code is generated from the output β.

7 is a block diagram of a 256-chip PSC detection apparatus according to an embodiment of the present invention, wherein the PSC transmitted from the communication system can be detected by the detection apparatus configured as shown in FIG. 7 in the mobile station. Since the PSC is composed of hierarchical Golay codes, the correlators used in the detection device can also be hierarchically configured, and the hierarchical correlators are used in a smaller number of devices than the general correlators that directly correlate the entire sync code. Can be implemented.

In FIG. 7, r (n) denotes a sample value at a discrete time n when the received signal is converted to baseband. In an actual receiver design, an integer number of samples may be taken for each chip to take a sampling rate higher than the chip rate. In 7, it is assumed that each chip has one sample value.

The preprocessor performs a function of converting a complex sample received in the I channel and the Q channel into a real sample when the sync code is transmitted in the QPSK signal. If the sync code is transmitted as a signal of binary phase shift keying (BPSK) instead of QPSK, the preprocessor is omitted.

α ₁ correlation unit performs a function for obtaining a correlation value with the 8 configuration of the chip length Golay code α ₁ is used to configure the part corresponding to the first half 128-chip by the PSC and the received samples in 16-chip interval, each of α ₁ Take care of the chip.

α ₂ correlation unit performs a function of obtaining a 8-chip length of the constituent Golay code α ₂ between the correlation value is used to configure the part corresponding to the second half 128-chip by the PSC and the received samples 16 chip interval to each chip of α ₂ Take care of

α ₁ correlation output of the correlation is a ₁ a ₁ a negative input the correlation unit obtains the correlation value of the base Golay code a ₁ of 16 chips long. Similarly, the output of correlation α ₂ is the input correlation portion a ₂ a ₂ in the correlation unit obtains the correlation value between the base of the Golay code a ₂ 16 chip length.

The output of the a ₁ correlator indicates a correlation value between the received sample and the first 128 chips of the PSC, and the output of the a ₂ correlator indicates a correlation value between the received sample and the latter 128 chips of the PSC.

Each correlation value for the first 128 and the second 128 chips is the input of the asynchronous combiner. In the asynchronous combiner, the squares of the two correlations are squared and added together to the final output value of the correlation for PSC at sample time n. (n) is obtained.

The method of estimating the reception timing by using the output R (n) for each sample time n is omitted because it is outside the gist of the present invention. From the reception timing obtained as above, the mobile station can obtain synchronization for the slot interval.

8 is a configuration diagram of a 128-chip PSC detection apparatus according to another embodiment of the present invention. When 128 chips are used for a synchronization code, the detection apparatus for the PSC is configured as shown in FIG. When 128 chips in the first half are used in the PSC having a 256-chip length, α ₁ and a ₁ are used as the codes α _x and a _x in FIG. 8, respectively. In the case where 128 chips in the second half are used, the codes α _x and α ₂ and a ₂ are used as a _x , respectively.

9 is a configuration diagram of a 256-chip SSC detection apparatus according to an embodiment of the present invention, in which an SSC transmitted from a communication system can be detected by a detection apparatus configured as shown in FIG. 9 in a mobile station. The detection apparatus for the SSC detects the SSC (C _S ^k ) used in the corresponding slot section using the detection device of FIG. 9 for the first 256 chips of every slot section based on the slot section timing obtained at the time of PSC detection. In FIG. 9, r (k) is the k-th sample value after converting the received signal to the baseband, and the preprocessor is omitted when the sync code is transmitted as a BPSK signal instead of QPSK.

Is in the C _S correlation unit SSC Hadamard performs code h _m and multiplication before the facilities to take a hierarchical Golay code C _S with a correlation value of 256 chip length, the outputs of eight-chip interval multiplied by the received samples and C _S Add. Since the Hadamard code h _m repeats the same chip at 8 chip intervals when generating SSC (C _S ^k ), even if the correlation output is added at 8 chip intervals, there is no influence by the Hadamard code.

Since the correlation output is obtained at intervals of 8 chips for all 256 chips, there are 32 C _S correlator outputs, and the first 16 outputs and the second 16 outputs are inputs of the 16 * 16 fast Hadamard converter.

Hadamard code h _m used to generate SSC (C _S ^k ) is the same chip is repeated at 8 chip intervals. Therefore, considering each 8 chip section as one chip in the first 128 chip part, it has a length of 16 chips. Same as the Hadamard code. Thus, a 16 * 16 fast Hadamard converter can be used for the first 16 output values of the C _S correlator. In addition, since the second half 128 chip in the Hadamard code h _m is the same as the first half 128 chip, the same 16 * 16 fast Hadamard converter can be used for the latter sixteen output values of the C _S correlation part. The 16 outputs of the 16 * 16 fast Hadamard converters represent the correlation values for the 16 Hadamard codes in sequence. The outputs of the two fast Hadamard converters are the inputs of the asynchronous coupling, and the asynchronous coupling takes the square of the input and then one of the first sixteen values and one of the last sixteen values in the same order. Add up to get 16 outputs.

The asynchronous coupling unit combines the correlation values obtained during the first 128 chip period and the second 128 chip period for the Hadamard code used in the SSC. The 16 outputs of the asynchronous coupling unit finally become the input of the maximum selector, and the maximum selector selects the maximum value of the 16 inputs and outputs the output value R (n) and the number I (n) for the selected input value. The output value R (n) is the final correlation value for the SSC, and I (n) is the number of the most correlated Hadamard code among the Hadamard codes used in the SSC.

By the above method, the SSC (C _S ^k ) received in each slot section is detected, and the sequence of 15 slot slots is decoded (when the sequence is encoded) and the code of the SCC sequence (when the sequence is encoded). Compared to the sequence, it is possible to detect a matching reception timing and sequence type. The synchronization for the frame period can be obtained from the reception timing, and the group of pilot codes used in the corresponding cell can be recognized from the sequence type.

10 is a configuration diagram of a 128-chip SSC detection apparatus according to another embodiment of the present invention, wherein a mobile station can obtain synchronization acquisition for a pilot code by using a detection result for an SCC sequence. When 128 chip length is used for the synchronization code, the detection apparatus for the SSC is configured as shown in FIG.

256-chip length of the SSC in the first half of the 128-chip portion only case 10 of C _S 'correlation unit 128 to a code chip of the _{<C S, 1, C S} , 2, C S, 3, ... used in the , C _{S, 128} > is used, and when only the latter 128 chip portion is used, the <C _{S, 129} , C _{S, 130} , C _{S, 131} , ..., C _{S, 256} > of 128 chips are used.

11 is a block diagram of a 256-chip SSC detection apparatus according to another embodiment of the present invention, Figure 12 is a block diagram of a 128-chip SSC detection apparatus according to another embodiment of the present invention. Since detection for SSC has already obtained slot interval timing in PSC detection, an active correlator is used rather than the structure of a matched filter for the Cs and C _S correlations in FIGS. 9 and 10. 11 and 12, the structure is very simple.

Fig. 11 is a detection device structure for a 256-chip sync code, which uses an active correlator as the Cs correlator to correlate Cs with every chip sample, adds samples for 8 chip intervals at the 8 chip combiner, and adds samples added at 8 chip intervals. Output

The serial / parallel converter divides the inputted samples into 16 outputs every 16 chip intervals, and passes the high-speed Hadamard transform unit to find the correlation value for the first 128 chips and the correlation for the second 128 chips, and asynchronously combines the two samples. Find the correlation value for 256 chips.

The maximum selector takes a sample having the maximum value among the 16 parallel input values and outputs the number I (k) of the Hadamard code having the highest correlation with the final correlation value R (k).

A detecting device structure for 12 of 128-chip synchronization code, C _S 'using a high active matter portion Any each maechip sample C _S' taking the correlation by adding a sample of the 8-chip coupling portion 8 chip section 8 chip interval Print samples added with.

The serial / parallel converter distributes the sample input for every 16 chip intervals to 16 outputs, and passes through the fast Hadamard transform unit to obtain a correlation value for 128 chips.

The maximum selector takes a sample having the maximum value among the 16 parallel input values and outputs the number I (n) of the Hadamard code having the highest correlation with the final correlation value R (n).

In this document, in order to effectively explain the contents of the present invention, as an example, a sync code and a detection device used in a sync channel in an asynchronous mobile communication system have been described. However, the synchronization code and the detection device of the present invention can be applied to other communication systems, and those skilled in the art to which the present invention belongs can be applied to other system environments or various modifications and adjustments can be made without departing from the technical matters of the present invention. This is clear. Therefore, the protection scope of the present invention will be limited only by the appended claims, not the application target or the embodiment, and should be construed as including all the various applications or modifications mentioned above.

In addition, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is a technology that the various permutations, modifications and changes can be made within the scope without departing from the spirit of the present invention It will be apparent to those of ordinary skill in the art.

As described above, the present invention enables the mobile station to easily synchronize the broadcast channel in the system by receiving the sync code transmitted on the sync channel before receiving the broadcast channel of the system.

In addition, there is an effect that the synchronization acquisition time is reduced and the synchronization acquisition probability is increased in the situation where the Doppler transition has a large difference between the frequencies of the reception carrier and the receiver.

Claims (17)

A method for generating a sync code of a sync channel used by a mobile station for synchronization acquisition in an asynchronous mobile communication system, Basic Golay code expressed as Equation 1 below Generating a first step; A constituent Golay code expressed as in Equation 2 below Generating a second step; And Generated default Golay code And configuration Golay code Based on the first hierarchical Golay code expressed as or Third step to generate Synchronization code generation method comprising a. [Equation 1] [Equation 2] [Equation 3] The method of claim 1, The first hierarchical Golay code is Code transmitted during the 128 chip period of the first half of the slot constituting the sync channel radio frame period as a primary sync code Synchronization code generation method characterized in that. The method of claim 1, The primary sync code represented by Equation 4 by concatenating the first hierarchical Golay code 4th step to generate Synchronization code generation method further comprising. [Equation 4] The method of claim 3, The primary sync code is Code transmitted during 256 chip intervals of a slot constituting the sync channel radio frame interval Synchronization code generation method characterized in that. The method of claim 3, Basic Golay code expressed as Equation 5 below Generating a fifth step; A constituent Golay code expressed as in Equation 6 below Generating a sixth step; And Generated default Golay code And configuration Golay code Based on the second hierarchical Golay code expressed as Step 7 to create a Synchronization code generation method comprising a. [Equation 5] [Equation 6] [Equation 7] The method of claim 5, As shown in Equation 8, the same chip is repeated during the 8-chip period, and the Hadamard code of 128 chips is repeated twice (h _m = Creating an eighth step; 128 chips of the first half of the second hierarchical Golay code ) And the first 128 chips of the Hadamard code (h _m ) ) Is a second-order code of 128 chips represented by the following equation (9) Creating a ninth step; And The latter 128 chips of the second hierarchical Golay code ( ) And the latter 128 chips of the Hadamard code (h _m ) ) Is a second-order code of 128 chips represented by the following equation (10) Step 10) Synchronization code generation method further comprising. [Equation 8] only, [Equation 9] [Equation 10] The method of claim 6, The secondary sync code ( ) The primary sync code Is transmitted when the primary sync code Code transmitted during the same transmission interval as Synchronization code generation method characterized in that. The method of claim 6, The secondary sync code ( ) The primary sync code Is transmitted when the primary sync code Code transmitted during the same transmission interval as Synchronization code generation method characterized in that. The method of claim 5, Step 11 of multiplying the second hierarchical Golay code and the Hadamard code h _m by chip to generate a 256-chip length secondary sync code represented by Equation 11 below; Synchronization code generation method further comprising. [Equation 11] The method of claim 9, The 256-second long secondary sync code generated in step 11 The primary sync code Is transmitted when the primary sync code Code transmitted during the same transmission interval as Synchronization code generation method characterized in that. A method for detecting a sync code generated by any one of claims 1 to 10, 128 chip primary sync code If is sent, Received samples sent and the configuration Golay code A first step of correlating at 16 chip intervals for; And The correlation value taken in the second step and the basic Golay code The 128 chip primary sync code at sample time n by correlating to Second step of obtaining a correlation value for Including, 128 chip primary sync code If is sent, Received samples sent and the configuration Golay code A third step of correlating at 16 chip intervals for; And The correlation value taken in the third step and the basic Golay code The 128 chip primary sync code at sample time n by correlating to Fourth step of obtaining a correlation value for Sync code detection method comprising a. The method of claim 11, When 256 chip primary sync code is transmitted, Received samples sent and the configuration Golay code A fifth step of correlating at 16 chip intervals for; The correlation value taken in the fifth step and the basic Golay code The first half chip of the 256 chip primary sync code at sample time n by correlating A sixth step of obtaining a correlation value for; Received samples sent and the configuration Golay code A seventh step of correlating at intervals of 16 chips for; The correlation value taken in the seventh step and the basic Golay code The latter half of the 256 chip primary sync code at sample time n by correlating An eighth step of obtaining a correlation value for; A ninth step of obtaining a correlation value for the 256-chip primary sync code at sample time n by adding a square of each of the correlation values obtained in the seventh and eighth steps and then adding them; Sync code detection method further comprising. The method of claim 12, The secondary sync code ( ) Is sent, 128 chips in the first half of the received sample and the second hierarchical (10) outputting 16 values by multiplying &lt; RTI ID = 0.0 &gt;)&lt; / RTI &gt; An eleventh step of obtaining 16 correlation values for the 16 Hadamard codes by performing 16 * 16 fast Hadamard transforms of the 16 values output in the 10th step based on the Hadamard code (h _m ); And By selecting the maximum value of the 16 correlation values obtained in the eleventh step, the secondary sync code ( Final correlation value and) The 12th step of outputting the number of the most correlated Hadamard code among Including, The secondary sync code ( ) Is sent, The latter 128 chips of the received sample and the second hierarchical Golay code ( (11) outputting 16 values by multiplying &lt; RTI ID = 0.0 &gt; A twelfth step of obtaining sixteen correlation values for sixteen Hadamard codes by performing 16 * 16 fast Hadamard transforms of the sixteen values output in the eleventh step based on the Hadamard code (h _m ); And By selecting the maximum value among the 16 correlation values obtained in the twelfth step, the secondary sync code ( Final correlation value and) The 13th step of outputting the number of the most correlated Hadamard code among Sync code detection method comprising a. The method of claim 13, When the secondary sync code of 256 chip length is transmitted, 128 chips in the first half of the received sample and the second hierarchical 14) outputting 16 values by multiplying &lt; RTI ID = 0.0 &gt; 16 * 16 high-speed Hadamard transform of the 16 values output in the 14th step based on the Hadamard code (h _m ) by performing 16 for the first half of the 256-chip secondary sync code and the 16 for 16 Hadamard codes Obtaining fifteen correlation values; The latter 128 chips of the received sample and the second hierarchical Golay code ( 16) outputting 16 values by multiplying &lt; RTI ID = 0.0 &gt; 16 * 16 high-speed Hadamard transform of the 16 values output in the 16th step based on the Hadamard code (h _m ), 16 for the latter 128 chips and 16 Hadamard codes of the 256-chip secondary sync code. A seventeenth step of obtaining two correlation values; By taking the squares of the 16 correlation values obtained in the 15th and 16th steps, respectively, each of the values corresponding to each other is sequentially added to obtain 16 output values. An eighteenth step of combining the correlation values obtained during the interval and the latter 128-chip interval of the 256-chip secondary sync code; And By selecting the maximum value among the 16 output values obtained in step 18, the most correlated Hadamard code between the final correlation value for the 256-chip secondary sync code and the Hadamard code used for the 256-chip secondary sync code Step 19 of outputting the number of Sync code detection method comprising a. The method of claim 12, When the secondary sync code of the 128 chip length is transmitted, A twenty step of taking a correlation value for every chip sample for the received sample and 128 chips of the second hierarchical Golay code; A twenty-first step of adding the correlation value of the twentieth step every eight chip periods and outputting the sum; A twenty-second step of distributing 16 output values every 16 chip sections with respect to the output value of the twenty-first step; 16 correlation values for the 128-chip secondary sync code and 16 Hadamard codes are obtained by performing 16 * 16 fast Hadamard conversion of the 16 values output in step 22 based on the Hadamard code h _m . Obtaining a twenty-third step; And By selecting the maximum value of the 16 correlation values obtained in step 23, the most correlated value between the final correlation value for the 128 chip secondary synchronization code and the Hadamard code used for the 128 chip secondary synchronization code is Step 24 to output the code number Sync code detection method comprising a. The method of claim 15, The 128-chip-long secondary sync code is the secondary sync code ( ) 128 chips of the second hierarchical Golay code is the first 128 chips of the second hierarchical Golay code. )ego, The 128-chip-long secondary sync code is the secondary sync code ( ), The 128 chips of the second hierarchical Golay code are the second 128 chips of the second hierarchical Golay code. ) A synchronization code detection method characterized in that. The method of claim 15, When the secondary sync code of 256 chip length is transmitted, A twenty-fifth step of taking a correlation value for every chip sample for a received sample and the second hierarchical Golay code; A twenty sixth step of adding the correlation value of the twenty-fiveth step every eight chip periods and outputting the sum; A twenty-seventh step of distributing 16 output values every 16 chip sections with respect to the output value of the twenty-sixth step; Based on the Hadamard code (h _m ) by converting the 16 values output in step 27 by 16 * 16 fast Hadamard conversion, the first half of the 256-chip secondary sync code and the second half of the 256-chip secondary sync code 128 A twenty-eighth step of sequentially obtaining sixteen correlation values for a chip and sixteen Hadamard codes; By taking the squares of the 16 correlation values sequentially obtained in step 28 and adding each value corresponding to each other in sequence, 16 output values are obtained to obtain the first 128 chip sections of the 256 chip secondary sync code and the Combining the correlation values obtained during the latter 128 chip period of the 256 chip secondary sync code; And By selecting the maximum value of the 16 output values obtained in step 29, the most correlated Hadamard code of the final correlation value for the 256-chip secondary sync code and the Hadamard code used for the 256-chip secondary sync code 30th step of outputting the number of Sync code detection method comprising a.