KR100474549B1 - Casby Force Refresh Device for Semiconductor Memory Devices - Google Patents

Abstract

The present invention relates to an internal function of a semiconductor memory device to automatically perform CBR refresh, which is one of the essential refresh operations during DRAM operation, during normal read or write operation.

Description

Cas Biporas refresh apparatus of semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a refresh apparatus for a semiconductor memory device. In particular, a cas non-for refresh device for a semiconductor memory device for automatically performing CBR refresh, which is one of the essential refresh operations during a DRAM operation, during a normal read or write operation. It is about.

In general, refresh is essential in DRAM writing.

This refresh operation is generated internally by automatically refreshing the word line selected by an external address and inputting a specific refresh command externally when an externally provided RAS (row address strobe) signal is enabled during a normal read or write operation. The selected word line is refreshed by the address to be refreshed.

A typical example of the latter refresh is CBR (CAS BEFORE RAS) refresh, which causes the internal counter to float the word line after the DRAM enters CBR mode.

In more detail, the ROH address is not input from the outside, and instead, the ROH address is generated from the address generation circuit inside the DRAM whenever there is a CBR refresh request.

Therefore, an address switch device is attached to the address buffer to accept an external address during normal operation and to accept an internal address during CBR refresh.

The address generator is connected in series with the same number of flip flip-flops with the row address bits. In the circuit that detects the CBR situation, once the CBR situation is detected, the signal CBR, which is notified, transitions to "high", whereby each flip-flop reacts in series to perform up-counting. Correspondingly connected to the address buffer. The status output of each flip-flop is connected to its respective address buffer, accepting the output of the internal address counter as an address instead of the address input from an external pin.

In the CBR situation, the CAS (Column Adress Strobe) is "low" so that an external address is input. In the CBR situation, the CAS is "high" and the address generated by the CBR counter is input to the address buffer.

The CBR signal is generated in the CBR sensing circuit, which is made of a combination of RAS and CAS.

The CBR detection circuit detects whether CAS is input before RAS, generates a CBR signal, and maintains this value until / RAS is "high" disabled.

However, in the conventional CBR refresh which has been used so far, it is very troublesome to insert a CBR cycle every refresh operation during the normal read / write operation.

In particular, it is very inefficient when considering the long RAS cycle to the CBR cycle, which causes poor refresh characteristics. There is also a hidden refresh, which activates CBR mode for a short time while RAS and CAS are enabled during normal read or write operation, and then refreshes the word line selected by the internally generated address. will be. Therefore, since both CBR and Hidden refresh have to make a signal from outside, it is troublesome to do this.

Therefore, the present invention was devised to solve the above-mentioned problem, and the casbiphoras mode is caused by an internal casing to be pulsed by an external casing while enabled in an internal lath receiving an external lath during a normal read or write operation. It is an object of the present invention to provide a cas biphoras refresh apparatus of a semiconductor memory device for entering.

According to the present invention, a casbifos ras refresh apparatus for achieving the above object comprises: a lath buffer for receiving an external ras signal and outputting an internal ras signal;

A cas non-fora refresh device of a semiconductor memory device comprising a cas buffer for receiving an external cas signal and outputting an internal cas signal.

Cas enable delay means for receiving an output signal of the cas buffer and outputting a cas enable relay signal;

Cas pulse generating means for receiving the output signal of the cas enable delay means and outputs a cas pulse signal;

And a cas nonphoras mode operation signal generating means for generating a pulse type-ras signal according to the lath buffer output signal and receiving an output signal of the cas pulse generator. .

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. 1 is a PULSED-RAS signal generating circuit for a CBR refresh operation according to an embodiment of the present invention, a cas buffer 20 for receiving a cas signal input from the outside and outputting an internal cas signal; A cas enable delay unit 30 for receiving an output signal of 20) and outputting a cascade delay signal (CASEN-DELAY), and a cascade pulse signal (CAS) for receiving the cascade delay signal CASEN-DELAY. Cass pulse generator 40 for outputting a pulse, a las buffer 10 for receiving an external las signal and outputting an internal las signal, an output signal of the las buffer 10 and the cas pulse A cas bipolar mode operation signal generator 50 receives the signal CAS-PULSE and outputs a pulse type-ras signal PULSED-RAS.

The cas enable delay unit 30 may include a first inverter IV1 for inverting the output signal of the cas buffer 20 and a first delay unit 31 for delaying the first inverter IV1 output signal for a predetermined time. ), The second inverter IV2 for inverting the output signal of the first delay unit 31, the output signal of the cas buffer 20 and the output signal of the second inverter IV2 to receive the cas- in. The first NOR gate NR1 outputs the enable delay signal CASEN-DELAY.

The cas pulse generator 40 may include a third inverter IV3 for inverting the CAS enable delay signal CASEN-DELAY and a second delay unit for delaying an output signal of the third inverter IV3 for a predetermined time. 41 and the first NAND gate ND1 for outputting a cas pulse signal CAS-PULSE by performing a logical operation on the cas enable relay signal CASN-DELAY and the output signal of the second delay unit 41. It is composed.

The cas biphoras mode operation signal generator 50 receives the output signal of the las buffer 10 and the cas pulse signal (CAS-PULSE) and outputs a pulse type-ras signal (PULSED-RAS). A fifth inverter IV5 for inverting the output signal of the lath buffer 10, a fourth inverter IV4 for inverting the cas pulse signal CAS-PULSE, A third NAND gate that receives the fifth inverter IV5 output signal and the fourth inverter IV4 output signal and outputs a logic operation signal, and inverts the third NAND gate ND3 output signal to invert the pulse; The seventh inverter IV7 outputs to one terminal of the second NOR gate NR2 of the type-lath signal generator 51.

The pulsed-lath signal generator 51 receives a output signal of the las buffer 10 and the cas-pulse signal CAS-PULSE to output a logic-operated signal, and the second NAND gate; A second NOR for receiving the sixth inverter IV6 for inverting the NAND gate ND2 output signal, the second inverter IV6 for outputting the sixth inverter IV6 and the seventh inverter IV7 output signal, and outputting a logic operation signal; A gate NR2 and an eighth inverter IV8 for inverting the second NOR gate NR2 output signal and outputting a pulsed-las signal PULSED-RAS.

Hereinafter, a cas biphoras mode operation signal generation circuit having the above-described configuration will be described in detail with reference to the operation timing diagram shown in FIG. 2.

The external las and cas signals are generated through the buffer and several inverters to generate the internal las and internal cas signals. The buffer circuit for converting the lath and casing signals, which are external TTL (transistor transistor logic) signals, into internal CMOS signals, is omitted.

First, as shown in (a) and (b) of FIG. 2, when the ras signal is enabled (falling from the high potential power supply voltage to the low potential ground voltage), the pulsed-ras signal PULSED-RAS is generated. Almost simultaneously it is enabled from the supply voltage to ground voltage.

After a while, as shown in (b) and (d), when the cas signal is enabled, the cas enable-delay signal (CASEN-DELAY) passes the appropriate delay at the output terminal of the cas enable delay unit 30, and then the ground voltage. After the casing pulse signal CAS-PULSE is enabled at the output terminal of the cas pulse generator 40 as shown in (f), the casable delay signal CASEN-DELAY is enabled. A low potential pulse is generated.

As shown in (i) by the low potential pulse of this cas-pulse, the pulse type Ras signal (PULSED-RAS) enabled by the low potential causes a high potential pulse and the external ras signal When disabled at high potential, the pulsed-ras signal (PULSED-RAS) is also immediately disabled at high potential.

When the final pulsed-ras signal (PULSED-RAS) and the cas signal are input to the CBR circuit, the CBR refresh operation can be performed.

Therefore, when inputting a lath and a cas cycle that performs a normal read or write operation from the outside, the CBR refresh signal is generated by performing a normal pulse and placing a pulse on the internal las signal in the enabled state, which is a CAS BEFORE RAS condition. This will automatically create the CBR refresh operation.

If you disable the fast disabling, you can get the pulse to work the same way as usual. Of course, the timing and width of the pulse can be adjusted according to circumstances.

As described above, the present invention is to enable the CBR refresh to be automatically performed during normal read or write operations. When the present invention is applied to a semiconductor memory device, it is inconvenient to insert a CBR cycle every time the refresh operation is performed. It can be removed and has the effect of improving the refresh characteristics.

Preferred embodiments of the present invention are for the purpose of illustration and various modifications, changes, substitutions and additions are possible to those skilled in the art through the spirit and scope of the present invention as set forth in the appended claims.

1 is a PULSED-RAS signal generation circuit for automatic CBR refresh according to an embodiment of the present invention.

2 is an operation timing diagram of FIG. 1.

<Description of Symbols for Main Parts of Drawings>

10: las buffer 20: cas buffer

30: cas enable delay unit 40: cas pulse generator

50: cas biphoras mode operation signal generator

31: first delay unit 41: second delay unit

51 pulse-laser signal generator

Claims (10)

A lath buffer for receiving an external lath signal and outputting an internal lath signal; A cas non-fora refresh device of a semiconductor memory device comprising a cas buffer for receiving an external cas signal and outputting an internal cas signal. A cas enable delay means for receiving an output signal of the cas buffer and outputting a cas enable delay signal; Cas pulse generating means for receiving the output signal of the cas enable delay means and outputs a cas pulse signal; And a cas nonphoras mode operation signal generating means for generating a pulse type-ras signal using the lath buffer output signal and the cas pulse signal. And an internal refresh signal to automatically generate an internal refresh using the internal CAS signal and the pulsed-RAS signal. The method of claim 1, The cas enable delay means comprises: first inverting means for inverting an output signal of the cas buffer; First delay means for delaying the output signal of the first inverting means for a predetermined time; Second inverting means for inverting the output signal of the first delay means; And a first logic means for receiving the output signal of the cas buffer and the output signal of the second inverting means to generate the casable enable delay signal. The method of claim 2, And the first logic means comprises a noah gate. The method of claim 1, The cas pulse generating means comprises: third inverting means for inverting the cas enable delay signal; Second delay means for delaying the output signal of the third inverting means for a predetermined time; And a second logic means for receiving the cas enable delay signal and the output signal from the second delay means to generate the cas pulse signal. The method of claim 4, wherein Wherein the second logic means comprises a NAND gate; The method of claim 1, The cas non-force mode operation signal generating means receives the output signal of the lath buffer and the cas pulse signal so that the pulsed-lath signal is immediately enabled when the output signal of the lath buffer is enabled. Lars signal generating means, And a third logic means for receiving the output signal of the lath buffer and the cas pulse signal and outputting the output signal to a predetermined logic input terminal of the pulse type-las signal generating means. . The method of claim 6, And the third logic means comprises a NAND gate. The method of claim 6, The pulsed-ras signal generating means includes fourth logic means for logically calculating the output signal of the lath buffer and the caspulse signal; And a fifth logic means for receiving the output signal of the fourth logic means and the output signal of the third logic means and outputting a pulse type-lath signal. The method of claim 8, And the fourth logic means comprises a NAND gate. The method of claim 8, And said fifth logic means comprises a noah gate.

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