KR100482997B1 - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR100482997B1 KR100482997B1 KR10-2003-0040533A KR20030040533A KR100482997B1 KR 100482997 B1 KR100482997 B1 KR 100482997B1 KR 20030040533 A KR20030040533 A KR 20030040533A KR 100482997 B1 KR100482997 B1 KR 100482997B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
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Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 게이트전극과 중첩되는 하드마스크층을 후속 랜딩플러그 분리를 위한 CMP 공정에서 식각선택비가 큰 재질로 형성하고, 랜딩플러그 콘택홀 형성을 위한 장벽 질화막을 단차피복성이 떨어지는 재질로 형성하여 하드마스크층 상부와 측면이 보강되도록형성한 후 랜딩플러그를 형성하였으므로, 랜딩플러그 형성시 기판 손상이 방지되어 소자으 리플레쉬 특성이 향상되고, 하드마스크층이 손상되지 않아, 충분한 CMP 공정마진을 확보할 수 있어 랜딩플러그의 단락이나, 게이트전극의 단락등이 방지되어 공정수율 및 소자의 신뢰성을 향상시킬 수 있다. The present invention relates to a method for manufacturing a semiconductor device, and in particular, a hard mask layer overlapping a gate electrode is formed of a material having a high etching selectivity in a CMP process for subsequent landing plug separation, and a barrier nitride film for forming a landing plug contact hole. Since the landing plug is formed after the hard mask layer is formed of a material having low step coverage and reinforcement, the damage of the substrate is prevented when the landing plug is formed, thereby improving the refresh characteristics of the device and damaging the hard mask layer. Therefore, sufficient CMP process margin can be secured, and shorting of the landing plug, short circuit of the gate electrode, etc. can be prevented, thereby improving process yield and device reliability.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 모스 전계효과 트랜지스터(Metal Oxide Semi conductor Field Effect Transistor; 이하 MOS FET라 칭함)의 게이트전극 보호를 위한 하드마스크층의 손상을 방지하고, 랜딩 플러그 형성시의 기판 손상에 의한 리플레쉬 특성 저하를 방지할 수 있는 반도체소자의 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to prevent damage to a hard mask layer for protecting a gate electrode of a metal oxide semi conductor field effect transistor (hereinafter referred to as a MOS FET) and to form a landing plug. The present invention relates to a method for manufacturing a semiconductor device capable of preventing a decrease in refresh characteristics due to substrate damage at the time.
최근의 반도체 장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체 장치의 제조 공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다. The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.
이러한 감광막 패턴의 분해능(R)은 감광막 자체의 재질이나 기판과의 접착력등과도 밀접한 연관이 있으나, 일차적으로는 사용되는 축소노광장치의 광원 파장(λ) 및 공정 변수(k)에 비례하고, 노광 장치의 렌즈 구경(numerical aperture; NA, 개구수)에 반비례한다. The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate. It is inversely proportional to the lens aperture (NA, numerical aperture) of the device.
[R=k*λ/NA, R=해상도, λ=광원의 파장, NA=개구수][R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]
여기서 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를들어 파장이 436 및 365㎚인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 라인/스페이스 패턴의 경우 각각 약 0.7, 0.5㎛ 정도가 한계이고, 0.5㎛ 이하의 미세 패턴을 형성하기 위해서는 이보다 파장이 더 작은 원자외선(deep ultra violet; DUV), 예를들어 파장이 248㎚인 KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 노광 장치를 이용하여야 한다. Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.
또한 축소노광장치와는 별도로 공정 상의 방법으로는 노광마스크(photo mask)로서 위상반전마스크(phase shift mask)를 사용하는 방법이나, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘(contrast enhancement layer; CEL) 방법이나, 두층의 감광막 사이에 에스.오.지(spin on glass; SOG)등의 중간층을 개재시킨 삼층레지스트(Tri layer resister; 이하 TLR이라 칭함) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다. In addition to the reduction exposure apparatus, the process method includes a method of using a phase shift mask as a photo mask, or forming a separate thin film on the wafer to improve image contrast. A contrast enhancement layer (CEL) method or a tri layer resister (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers. In addition, a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.
또한 상하의 도전배선을 연결하는 콘택홀은 상기에서의 라인/스페이스 패턴에 비해 디자인룰이 더 크게 나타나는데, 소자가 고집적화 되어감에 따라 자체의 크기와 주변배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스팩트비(aspect ratio)가 증가한다. 따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택 형성 공정에서의 마스크들간의 정확하고 엄격한 정렬이 요구되어 공정여유도가 감소돠거나, 여유가 전혀없이 공정을 진행하여야하는 어려움이 있다. In addition, the contact hole connecting the upper and lower conductive wirings has a larger design rule than the above line / space pattern. As the device becomes more integrated, the size of the contact hole and the distance between the peripheral wirings are reduced, and the contact hole diameter and The aspect ratio, which is the ratio of depths, increases. Therefore, in the highly integrated semiconductor device having the multilayer conductive wiring, accurate and strict alignment between the masks in the contact forming process is required, so that the process margin is reduced or the process must be performed without any margin.
이러한 콘택홀은 홀간의 간격 유지를 위하여 마스크 정렬시의 오배열 여유(misalignment tolerance), 노광공정시의 렌즈 왜곡(lens distortion), 마스크 제작 및 사진식각 공정시의 임계크기 변화(critical dimension variation), 마스크간의 정합(registration)등과 같은 요인들을 고려하여 마스크를 형성한다. These contact holes can be used for misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, The mask is formed by considering factors such as registration between the masks.
상기와 같은 콘택홀의 형성 방법으로는 직접 식각 방법과, 측벽 스페이서를 사용하는 방법 및 SAC 방법등이 있다. As a method of forming the contact hole as described above, there are a direct etching method, a method using a sidewall spacer, a SAC method, and the like.
상기에서 직접 식각방법과 측벽 스페이서 형성 방법은 현재의 재반 기술 수준에서 0.3㎛ 이하의 디자인 룰을 갖는 소자 제조에는 사용할 수 없어 소자의 고집적화에 한계가 있다. In the above method, the direct etching method and the sidewall spacer forming method cannot be used for manufacturing a device having a design rule of 0.3 μm or less in the current technology level, and thus there is a limitation in high integration of the device.
또한 콘택홀 형성시 리소그래피(Lithography) 공정의 한계를 극복하기 위하여 고안된 SAC 방법은 식각장벽층으로 사용하는 물질에 따라 다결정실리콘층이나 질화막 또는 산화질화막등을 사용하는 것으로 나눌 수 있으며, 가장 유망한 것으로 질화막을 식각 방어막으로 사용하는 방법이 있다. In addition, the SAC method, which is designed to overcome the limitations of the lithography process in forming contact holes, can be divided into polysilicon layer, nitride film, or oxynitride film, depending on the material used as the etch barrier layer. Can be used as an etch shield.
도 1a 내지 도1d는 종래 기술에 따른 반도체소자의 제조공정도이다. 1A to 1D are manufacturing process diagrams of a semiconductor device according to the prior art.
먼저, 반도체기판(10)상에 게이트산화막(12)을 형성하고, 상기 게이트산화막(12)상에 하드마스크층(16)과 중첩되어있는 게이트전극(14)을 형성한 후, 상기 구조의 전표면에 스페이서용 질화막(18)과 식각장벽용 질화막(20)을 순차적으로 형성한다. 여기서 상기 게이트전극(14)은 다결정실리콘 상에 W이나 텅스텐 실리사이드가 적층되어있는 저저항 구조이다. (도 1a 참조). First, the gate oxide film 12 is formed on the semiconductor substrate 10, and the gate electrode 14 overlapping the hard mask layer 16 is formed on the gate oxide film 12. On the surface, a spacer nitride film 18 and an etching barrier nitride film 20 are sequentially formed. The gate electrode 14 has a low resistance structure in which W or tungsten silicide is stacked on polycrystalline silicon. (See FIG. 1A).
그다음 상기 구조의 전표면에 층간절연막(22)을 도포한후, 평탄화 시키고, 랜딩플러그용 식각마스크를 사용한 사진 식각 공정으로 랜딩플러그 콘택홀(24)을 형성한다. 이때 상기 식각 공정은 일차로 식각장벽용 질화막(20)을 식각 정지층으로하여 층간절연막(22)을 식각하고, 이차로 노출된 식각장벽용 질화막(20)과 스페이서용 질화막(18)을 순차적으로 식각하여 반도체기판(10)을 노출시킨다. (도 1b 참조). Then, the interlayer insulating film 22 is applied to the entire surface of the structure, and then planarized, and the landing plug contact hole 24 is formed by a photolithography process using an etching mask for landing plug. In this etching process, the interlayer insulating film 22 is etched using the etch barrier nitride film 20 as an etch stop layer, and the etch barrier nitride film 20 and the nitride nitride film 18 for spacers are sequentially exposed. The semiconductor substrate 10 is exposed by etching. (See FIG. 1B).
그후 상기 구조의 전표면에 랜딩플러그용 다결정실리콘층(26)을 도포하여 상기 콘택홀(24)을 메우고, (도 1c 참조), CMP 공정으로 상기 다결정실리콘층(26)이 분리될 때 까지 식각하여 랜딩플러그(28)를 형성한다. (도 1d 참조). After that, the landing plug polycrystalline silicon layer 26 is applied to the entire surface of the structure to fill the contact hole 24 (see FIG. 1C), and the etching process is performed until the polysilicon layer 26 is separated by a CMP process. The landing plug 28 is formed. (See FIG. 1D).
상기와 같은 종래 기술에 따른 반도체소자의 제조방법은 랜딩플러그 콘택홀 식각 공정시 하드마스크층 상부의 식각장벽용 질화막과 스페이서용 질화막이 일부 손상되고, 이때 노출되는 반도체기판도 손상되어 소자의 리플레쉬 특성을 저하시키고, 또한 랜딩플러그 분리를 위한 CMP 공정에서 하드마스크층의 상부가 일정 두께 제거되어 충분한 공정 마진을 가지기 어려워져, 랜딩플러그 분리에서 불량이 발생하거나, 하드마스크층이 유실되어 후속 공정시 단락이 발생하여 공정 수율 및 소자 동작의 신뢰성을 저해하는 문제점이 있다. In the method of manufacturing a semiconductor device according to the related art as described above, during the landing plug contact hole etching process, the nitride barrier film and the spacer nitride film on the hard mask layer are partially damaged, and the exposed semiconductor substrate is also damaged to refresh the device. In the CMP process for landing plug separation, the upper part of the hard mask layer is removed to a certain thickness, making it difficult to have a sufficient process margin, resulting in a defect in the landing plug separation or a loss of the hard mask layer. There is a problem in that a short circuit occurs to impair process yield and reliability of device operation.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 The present invention is to solve the above problems, the object of the present invention is
하드마스크층을 랜딩플러그 분리를 위한 CMP 공정에서 식각 선택비를 가지는 물질로 형성하고, 랜딩플러그 콘택홀 식각 장벽층은 단차피복성이 떨어지는 물질로 형성하여 콘택홀 식각시 하드마스크층의 손상 가능성을 낮추어 하드마스크층의 손실을 방지하고, 기판 손상에 따른 리플레쉬 특성 저??도 방지하여 공정 수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공함에 있다. The hard mask layer is formed of a material having an etching selectivity in the CMP process for landing plug separation, and the landing plug contact hole etching barrier layer is formed of a material having low step coverage, thereby preventing the possibility of damaging the hard mask layer during contact hole etching. The present invention provides a method of manufacturing a semiconductor device that can reduce the loss of the hard mask layer and reduce the refresh characteristics due to the substrate damage, thereby improving process yield and reliability of device operation.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자 제조방법의 특징은, Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,
반도체기판상에 게이트절연막을 형성하는 공정과, Forming a gate insulating film on the semiconductor substrate;
상기 게이트절연막상에 하드마스크층과 중첩되어있는 게이트전극을 형성하되, 상기 하드마스크층을 과실리콘 질화막으로 형성하는 공정과, Forming a gate electrode overlapping the hard mask layer on the gate insulating layer, wherein the hard mask layer is formed of a silicon nitride film;
상기 구조의 전표면에 식각장벽용 질화막을 형성하되, 상기 식각장벽용 질화막을 상기 하드마스크층의 상부와 측벽이 반도체기판상에 형성된 두께 보다 두껍게 형성하는 공정과, Forming an etch barrier nitride film on the entire surface of the structure, wherein the etch barrier nitride film is formed thicker than the thickness formed on the semiconductor substrate by the upper side and the sidewall of the hard mask layer;
상기 구조의 전표면에 층간절연막을 형성하는 공정과, Forming an interlayer insulating film on the entire surface of the structure;
상기 반도체기판에서 랜딩플러그와 접촉되도록 예정되어있는 부분상의 층간절연막을 랜딩플러그 콘택홀 식각마스크를 사용하여 식각하여 식각장벽층용 질화막을 노출시키는 공정과, Etching the interlayer insulating film on the portion of the semiconductor substrate, which is intended to be in contact with the landing plug, by using a landing plug contact hole etching mask to expose the nitride film for the etch barrier layer;
상기 노출되어있는 식각장벽용질화막과 스페이서용 질화막을 순차적으로 식각하여 반도체기판을 노출시키는 랜딩플러그 콘택홀을 형성하는 공정과, Sequentially etching the exposed etch barrier nitride film and the spacer nitride film to form a landing plug contact hole exposing a semiconductor substrate;
상기 구조의 전표면에 다결정실리콘층을 형성하여 상기 랜딩플러그 콘택홀을 메우는 공정과, Forming a polysilicon layer on the entire surface of the structure to fill the landing plug contact hole;
상기 다결정실리콘층과 층간절연막을 순차적으로 CMP 방법으로 식각하여 독립된 랜딩플러그를 형성하는 공정을 구비함에 있다. The polysilicon layer and the interlayer insulating film are sequentially etched by a CMP method to form an independent landing plug.
또한 본발명의 다른 특징은, 상기 하드마스크층은 SiH4 : NH3 = 1∼5 : 1 가스 유량비, 2200∼3100sccm, 500∼3000Å 두께로, 챔버 압력은 0.1∼10Torr, 파워는 500∼1000W 의 조건으로 형성하고, 상기 식각장벽용 질화막은 SiH4 : NH3 = 1∼2 : 1 가스 유량비, 4000∼9500sccm, 2000∼5000Å 두께로, 챔버 압력은 5∼10Torr, 파워는 500∼1000W 의 조건으로 형성하며, 상기 식각장벽용 질화막은 하드마스크층의 상부와 측면에 형성된 두께가 게이트전극의 측면이나 반도체기판상에 형성된 것 보다 1∼20% 두껍게 형성하고, 상기 랜딩플러그 분리를 위한 CMP 공정은 CeO2 슬러리를 사용하며, 연마제의 크기 50∼500㎚, pH가 5∼9인 슬러리를 사용하는 것을 특징으로 한다.In another aspect of the present invention, the hard mask layer has a SiH 4 : NH 3 = 1-5: 1 gas flow rate ratio, 2200-3100 sccm, 500-3000 Pa thickness, chamber pressure of 0.1-10 Torr, and power of 500-1000 W. The etch barrier nitride film was SiH 4 : NH 3 = 1 to 2: 1 gas flow rate, 4000 to 9500 sccm, 2000 to 5000 kPa thick, chamber pressure was 5 to 10 Torr, power was 500 to 1000 W. The etching barrier nitride layer has a thickness formed on the top and side surfaces of the hard mask layer 1 to 20% thicker than that formed on the side of the gate electrode or the semiconductor substrate, and the CMP process for separating the landing plug is CeO. 2 slurries are used, and a slurry having a size of 50 to 500 nm of abrasive and a pH of 5 to 9 is used.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체소자의 제조방법에 대하여 상세히 설명을 하기로 한다. Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 따른 반도체소자의 제조공정도이다. 2A to 2C are manufacturing process diagrams of a semiconductor device according to the present invention.
먼저, 반도체기판(30)상에 게이트산화막(32)을 형성하고, First, the gate oxide film 32 is formed on the semiconductor substrate 30,
상기 게이트산화막(32) 상에 다결정실리콘 상에 W이나 텅스텐 실리사이드가 적층되어있는 저저항 구조의 게이트전극(34) 및 상기 게이트전극(34)과 중첩되어있는 하드마스크층(36)을 형성한다. 여기서 상기 하드마스크층(36)은 후속 랜딩플러그 다결정실리콘층 분리를 위한 CMP 공정에서 슬러리에 식각되지 않는 재질로서, 예를 들어 산화막 식각시 사용되는 CeO2 슬러리에 대해서 식각되지 않는 과실리콘 질화막 재질로 형성한다. 상기 과실리콘 질화막은 SiH4 : NH3 가스 유량비를 1∼5 : 1 의 비로서, 2200∼3100sccm의 유량으로, 500∼3000Å 정도의 두께로, 챔버 압력은 0.1∼10Torr, 파워는 500∼1000W 로 형성한다.On the gate oxide layer 32, a gate electrode 34 having a low resistance structure in which W or tungsten silicide is stacked on polycrystalline silicon and a hard mask layer 36 overlapping the gate electrode 34 are formed. Here, the hard mask layer 36 is a material that is not etched into the slurry in the CMP process for subsequent landing plug polycrystalline silicon layer separation, for example, as a silicon nitride film that is not etched with respect to the CeO 2 slurry used for etching the oxide film. Form. The silicon silicon film has a SiH 4 : NH 3 gas flow rate ratio of 1 to 5: 1, a flow rate of 2200 to 3100 sccm, a thickness of about 500 to 3000 Pa, a chamber pressure of 0.1 to 10 Torr, and a power of 500 to 1000 W. Form.
그다음 상기 구조의 전표면에 스페이서용 질화막(38)과 식각장벽용 질화막(40)을 형성한다. 여기서 상기 스페이서용 질화막(38)은 형성하지 않을 수도 있으며, 상기 식각장벽용 질화막(40)은 단차피복성이 약한 성질을 가지도록 형성하여 오버행이 형성되어 게이트전극(34)의 사이드부가 보강되며, 증착 조건은 SiH4 : NH3 가스 유량비를 1∼2 : 1 의 비로서, 바람직하게는 1.7 : 1의 비이며, 4000∼9500sccm의 유량으로, 2000∼5000Å 정도의 두께로, 챔버 압력은 5∼10Torr, 파워는 500∼1000W 로 형성한다.Then, a spacer nitride film 38 and an etch barrier nitride film 40 are formed on the entire surface of the structure. Here, the spacer nitride film 38 may not be formed, and the etch barrier nitride film 40 is formed to have a weak step coating property, so that an overhang is formed so that the side portion of the gate electrode 34 is reinforced. The deposition conditions are a ratio of SiH 4 : NH 3 gas flow rate of 1 to 2: 1, preferably 1.7: 1, a flow rate of 4000 to 9500 sccm, a thickness of about 2000 to 5000 Pa, and a chamber pressure of 5 to 5 10 Torr, the power is formed to 500 ~ 1000W.
즉 하드마스크층(36)의 상부와 측면에 형성된 질화막(40)의 두께가 게이트전극(34)의 측면이나 반도체기판(30)상에 형성된 질화막(40) 보다 1∼20% 두??게 형성되도록한 것이다. (도 2a 참조). That is, the thickness of the nitride film 40 formed on the top and side surfaces of the hard mask layer 36 is 1 to 20% thicker than the nitride film 40 formed on the side surface of the gate electrode 34 or the semiconductor substrate 30. It is as possible. (See FIG. 2A).
그후, 상기 구조의 전표면에 층간절연막(42)을 형성하고, 그 상부를 평탄화한 후, 랜딩플러그용 콘택 마스크(도시되지 않음)를 이용한 사진식각 공정으로 상기 층간절연막(42)을 식각하여 식각장벽용 질화막(40)을 노출시킨다. Thereafter, the interlayer insulating film 42 is formed on the entire surface of the structure, and the upper portion of the interlayer insulating film 42 is planarized. Then, the interlayer insulating film 42 is etched and etched by a photolithography process using a landing plug contact mask (not shown). The barrier nitride film 40 is exposed.
그다음 상기 노출되어 있는 식각장벽용 질화막(40)과 스페이서용 질화막(38)을 순차적으로 식각하여 반도체기판(30)을 노출시키는 랜딩플러그용 콘택홀(44)을 형성한 후, 상기 구조의 전표면에 랜딩플러그용 다결정실리콘층(46)을 형성한다. 여기서 상기 콘택홀(44) 식각 공정시 식각장벽용 질화막(40)이 상측 및 측면이 두껍게 형성되어 층간절연막(42) 식각 공정이나 반도체기판(30) 오픈 식각 공정에서 상당량이 남아 있게되며, 따라서 하드마스크층(36)이 효과적으로 보호된다. (도 2b 참조). Then, the exposed etch barrier nitride film 40 and the spacer nitride film 38 are sequentially etched to form a landing plug contact hole 44 exposing the semiconductor substrate 30, and then the entire surface of the structure. A polysilicon layer 46 for landing plug is formed on the substrate. Here, the etching barrier nitride layer 40 is formed to have a thick upper and side surfaces during the etching process of the contact hole 44, so that a considerable amount remains in the interlayer insulating layer 42 etching process or the open etching process of the semiconductor substrate 30. The mask layer 36 is effectively protected. (See FIG. 2B).
그후, 상기 다결정실리콘층(46)과 층간절연막(42)을 순차적으로 CMP 식각하여 다결정실리콘층(46)을 각각의 랜딩플러그(48)로 분리시킨다. 여기서 상기 CMP 공정은 CeO2 슬러리를 사용하며, 연마제의 크기는 50∼500㎚ 정도이며, 슬러리는 pH가 5∼9인 슬러리를 사용한다. 상기 CeO2 슬러리는 과실리콘질화막에 대하여 식각 선택비가 일반의 질화막 보다 크므로, 상기 하드마스크층(36)이 식각 정지층이 되어도 많이 손상되지는 않는다. 또한 상기 CMP 공정후에 반도체기판(30)을 H2SO4 + H2O2 + BOE + NH4OH + H2O 혼합 용액에서 2초에서 1분간 세정할 수도 있으며, BOE 대신 HF를 사용할 수도 있다. (도 2c 참조).Thereafter, the polysilicon layer 46 and the interlayer insulating layer 42 are sequentially CMP-etched to separate the polysilicon layer 46 into respective landing plugs 48. Here, the CMP process uses a CeO 2 slurry, the size of the abrasive is about 50 ~ 500nm, the slurry uses a slurry of pH 5-9. Since the etching selectivity of the CeO 2 slurry is greater than that of the general nitride film with respect to the oversilicon nitride film, even if the hard mask layer 36 becomes an etch stop layer, it is not damaged much. In addition, after the CMP process, the semiconductor substrate 30 may be cleaned in a mixed solution of H 2 SO 4 + H 2 O 2 + BOE + NH 4 OH + H 2 O for 2 seconds to 1 minute, and HF may be used instead of BOE. . (See FIG. 2C).
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은 게이트전극과 중첩되는 하드마스크층을 후속 랜딩플러그 분리를 위한 CMP 공정에서 식각선택비가 큰 재질로 형성하고, 랜딩플러그 콘택홀 형성을 위한 장벽 질화막을 단차피복성이 떨어지는 재질로 형성하여 하드마스크층 상부와 측면이 보강되도록형성한 후 랜딩플러그를 형성하였으므로, 랜딩플러그 형성시 기판 손상이 방지되어 소자으 리플레쉬 특성이 향상되고, 하드마스크층이 손상되지 않아, 충분한 CMP 공정마진을 확보할 수 있어 랜딩플러그의 단락이나, 게이트전극의 단락등이 방지되어 공정수율 및 소자의 신뢰성을 향상시킬 수 있는 이점이 있다. As described above, in the method of fabricating a semiconductor device according to the present invention, a hard mask layer overlapping the gate electrode is formed of a material having a high etching selectivity in a CMP process for subsequent landing plug separation, and a barrier for forming a landing plug contact hole. Since the nitride film was formed of a material having low step coverage, the top and side surfaces of the hard mask layer were formed to be reinforced, and the landing plug was formed. Thus, damage to the substrate was prevented when the landing plug was formed, thereby improving the refresh characteristics of the device, and the hard mask layer. There is an advantage in that the CMP process margin can be secured without damage, and shorting of the landing plug, shorting of the gate electrode, and the like can be prevented, thereby improving process yield and device reliability.
도 1a 내지 도 1d는 종래 기술에 따른 반도체소자의 제조공정도. 1A to 1D are manufacturing process diagrams of a semiconductor device according to the prior art.
도 2a 내지 도 2c는 본 발명에 따른 반도체소자의 제조공정도. 2a to 2c is a manufacturing process diagram of a semiconductor device according to the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
10, 30 : 반도체기판 12, 32 : 게이트산화막10, 30: semiconductor substrate 12, 32: gate oxide film
14, 34 : 게이트전극 16, 36 : 하드마스크층14, 34: gate electrode 16, 36: hard mask layer
18, 38 : 스페이서용 질화막 20, 40 : 식각장벽용 질화막18, 38: nitride film for spacer 20, 40: nitride film for etching barrier
22, 42 : 층간절연막 24, 44 : 랜딩플러그 콘택홀 22, 42: interlayer insulating film 24, 44: landing plug contact hole
26, 46 : 다결정실리콘층 28, 48 : 랜딩플러그26, 46 polysilicon layer 28, 48: landing plug
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