KR100494680B1 - Thin film transistor-liquid crystal display device - Google Patents
Thin film transistor-liquid crystal display device Download PDFInfo
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- KR100494680B1 KR100494680B1 KR10-1999-0024173A KR19990024173A KR100494680B1 KR 100494680 B1 KR100494680 B1 KR 100494680B1 KR 19990024173 A KR19990024173 A KR 19990024173A KR 100494680 B1 KR100494680 B1 KR 100494680B1
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- 239000004973 liquid crystal related substance Substances 0.000 title claims description 11
- 238000000926 separation method Methods 0.000 claims abstract description 9
- 239000011159 matrix material Substances 0.000 claims abstract description 7
- 239000010408 film Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/441—Interconnections, e.g. scanning lines
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Abstract
본 발명은 마스크 샷간의 오정렬이 발생하더라도 일정한 Cgs값을 얻음으로써 화질을 향상시킬 수 있는 TFT-LCD를 제공한다.The present invention provides a TFT-LCD that can improve image quality by obtaining a constant Cgs value even when misalignment between mask shots occurs.
본 발명에 따른 TFT-LCD는 절연기판 상에 매트릭스 형태로 배치된 게이트 라인 및 데이터 라인; 상기 게이트 라인과 데이터 라인간 교차부에 배치된 박막트랜지스터; 및 상기 게이트 라인과 데이터 라인에 의해 한정된 화소영역 내에 상기 박막트랜지스터와 콘택하도록 배치된 화소전극을 포함하는 박막트랜지스터 액정표시소자에 있어서, 상기 박막트랜지스터는, 상기 게이트 라인으로부터 인출된 게이트 전극과, 상기 게이트 상부에 배치된 액티브층과, 상기 데이터 라인으로부터 인출되고 상기 게이트 전극의 일측과 오버랩되면서 이격해서 서로 평행하게 배열된 제1 및 제2 드레인 전극과, 상기 게이트 전극의 타측과 오버랩되면서 상기 제1 드레인 전극과 제2 드레인 전극 사이의 중앙에 배치되고 상기 화소전극과 콘택되는 소오스 전극을 포함한다. 또한, 제 1 및 제 2 드레인 전극과 소오스 전극 사이의 이격거리는 서로 같고, 소오스 전극의 폭은 이격거리보다 크다. 또한, 소오스 전그과 게이트 전극 사이의 캐패시턴스의 면적은 게이트 절연막의 단위면적당 용량×게이트의 폭×(소오스 전극의 폭+소오스 전극과 드레인 전극 사이의 거리)이다.TFT-LCD according to the present invention comprises a gate line and a data line arranged in a matrix form on an insulating substrate; A thin film transistor disposed at an intersection between the gate line and the data line; And a pixel electrode arranged to contact the thin film transistor in a pixel region defined by the gate line and the data line, wherein the thin film transistor comprises: a gate electrode drawn from the gate line; An active layer disposed on the gate, first and second drain electrodes drawn from the data line and spaced apart from each other while overlapping with one side of the gate electrode, and overlapping with the other side of the gate electrode; And a source electrode disposed in the center between the drain electrode and the second drain electrode and in contact with the pixel electrode. Further, the separation distance between the first and second drain electrodes and the source electrode is the same, and the width of the source electrode is larger than the separation distance. In addition, the area of the capacitance between the source electrode and the gate electrode is the capacity per unit area of the gate insulating film x the width of the gate x (the width of the source electrode + the distance between the source electrode and the drain electrode).
Description
본 발명은 액티브 매트릭스형 액정 표시 소자에 관한 것으로, 특히 화질을 개선할 수 있는 박막 트랜지스터 액정 표시 소자에 관한 것이다.The present invention relates to an active matrix liquid crystal display device, and more particularly to a thin film transistor liquid crystal display device capable of improving image quality.
일반적으로, 액티브 매트릭스형 액정표시(active matrix-type liquid crystal display; AM-LCD) 장치는 얇아서 다양한 표시장치에 사용된다. 이러한 AM-LCD 장치에서, 박막 트랜지스터(thin film transistor; TFT)가 각 화소에 대한 스위칭 소자로서 제공되어, 개개의 화소전극들이 독립적으로 구동되기 때문에, 듀티(duty) 비의 감소에 기인하는 콘트라스트가 감소되지 않고, 또한 디스플레이 용량이 증가하여 라인수가 증가될 때에도 시야각이 감소되지 않는다.In general, an active matrix-type liquid crystal display (AM-LCD) device is thin and is used in various display devices. In such an AM-LCD device, a thin film transistor (TFT) is provided as a switching element for each pixel, so that individual pixel electrodes are driven independently, so that the contrast due to the reduction in the duty ratio is reduced. It does not decrease and also the viewing angle does not decrease even when the display capacity increases and the number of lines increases.
도 1은 종래의 TFT-LCD를 나타낸 평면도이다. 1 is a plan view showing a conventional TFT-LCD.
도 1을 참조하면, 유리와 같은 투명한 절연기판(10; 도 2 참조) 상에 게이트 라인 (11)과 데이터 라인(15)이 매트릭스 형태로 배열되고, 게이트 라인(11)과 데이터 라인(15)의 교차부분에 TFT(100)가 배치된다. TFT(100)는 게이트 라인(11)에서 돌출된 게이트(11A)와, 액티브층(13)과, 데이터 라인(15)에서 돌출되고 게이트(11A)의 일측과 오버랩된 드레인(15B)과, 드레인(15B)과 소정간격 이격되고 게이트(11A)의 다른측과 오버랩된 소오스(15A)를 포함한다. 또한, 게이트 라인(11)과 데이터 라인(15)에 의해 형성된 공간에는 TFT(100)의 소오스(15A)와 콘택하는 화소전극(16)이 배치된다. Referring to FIG. 1, a gate line 11 and a data line 15 are arranged in a matrix on a transparent insulating substrate 10 (see FIG. 2) such as glass, and the gate line 11 and the data line 15 are arranged in a matrix form. The TFT 100 is arranged at the intersection of. The TFT 100 includes a gate 11A protruding from the gate line 11, an active layer 13, a drain 15B protruding from the data line 15 and overlapping one side of the gate 11A, and a drain. A source 15A is spaced apart from the predetermined distance 15B and overlapped with the other side of the gate 11A. In the space formed by the gate line 11 and the data line 15, the pixel electrode 16 in contact with the source 15A of the TFT 100 is disposed.
도 2는 도 1에 도시된 TFT(100)의 Ⅱ-Ⅱ'선에 따른 단면도로서, 도 2에 도시된 바와 같이, 절연기판(10) 상에 게이트(11A)가 형성되고, 기판 전면에 게이트 절연막(12)이 형성된다. 게이트(11A)에 대응하는 게이트 절연막(12) 상부에 반도체층(13)이 형성되고, 반도체층(13) 상부에는 게이트(11A)의 양 측과 각각 오버랩하면서 서로 이격된 소오스 및 드레인(15A, 15B)이 형성된다. 또한, 소오스 및 드레인(15A, 15B)과 반도체층(13) 사이에는 오믹층(14)이 개재되어 있다.FIG. 2 is a cross-sectional view taken along line II-II 'of the TFT 100 shown in FIG. 1, and as shown in FIG. The insulating film 12 is formed. The semiconductor layer 13 is formed on the gate insulating layer 12 corresponding to the gate 11A, and the source and drain 15A spaced apart from each other while overlapping both sides of the gate 11A, respectively, on the semiconductor layer 13. 15B) is formed. The ohmic layer 14 is interposed between the source and drain 15A, 15B and the semiconductor layer 13.
상기한 TFT의 동작을 살펴보면, 게이트 전압(Vg)이 문턱전압(Vth) 보다 큰 경우에는, 도 2에 도시된 바와 같이, 반도체층(13)에 전자(-)가 유기되어 채널이 형성된다. 반면, 게이트 전압(Vg)이 문턱전압(Vth) 보다 작은 경우에는, 반도체층(13)에 유기되었던 전자(-)가 소오스(15A)으로 빠져나가게 된다.Referring to the operation of the TFT, when the gate voltage Vg is greater than the threshold voltage Vth, as shown in FIG. 2, electrons (−) are induced in the semiconductor layer 13 to form a channel. On the other hand, when the gate voltage Vg is smaller than the threshold voltage Vth, electrons (-) which have been induced in the semiconductor layer 13 exit to the source 15A.
상기한 바와 같이, TFT에서 채널을 형성하기 위해서는 소오스(15A)가 게이트(11A)와 오버랩되도록 배치되어야 한다. 이때, 게이트-소오스 사이의 캐패시턴스(Cgs)는 화소전압의 변화분으로서, TFT-LCD의 화질을 결정하는 킥백전압(kick-back voltage ; ΔVp)의 변수이다.As described above, in order to form a channel in the TFT, the source 15A must be arranged to overlap the gate 11A. At this time, the capacitance Cgs between the gate and the source is a change in pixel voltage, which is a variable of kick-back voltage (ΔVp) that determines the image quality of the TFT-LCD.
즉, ΔVp는 하기와 같이 나타낼 수 있다.That is, ΔVp can be expressed as follows.
ΔVp =ΔVgCgs/(Cst+CLC+Cgs)ΔVp = ΔVgCgs / (Cst + C LC + Cgs)
여기서, ΔVg는 게이트 전압의 변화분이고, Cgs는 게이트-소오스 캐패시턴스이고, Cst는 스토리지 캐패시턴이고, CLC는 액정 캐패시턴스이다.Here, ΔVg is the change in gate voltage, Cgs is the gate-source capacitance, Cst is the storage capacitance, and C LC is the liquid crystal capacitance.
한편, ΔVp의 변수인 Cgs의 면적은 소오스(15A) 및 드레인(15B)의 중간부터 게이트(11A)와 오버랩되는 부분의 반도체층(13)의 면적이다.On the other hand, the area of Cgs which is a variable of ΔVp is the area of the semiconductor layer 13 in the portion overlapping with the gate 11A from the middle of the source 15A and the drain 15B.
그러나, 노광공정에 사용되는 노광기의 노광영역은 6인치 또는 5인치 정도이기 때문에, 6인치 이상의 TFT-LCD를 제작하기 위해서는 여러개의 포토 마스크를 이용하여 분할 노광을 진행하여야 하므로, 마스크 샷(shot) 간의 오정렬(misalign)이 발생된다. 예컨대, 소오스 및 드레인(15A, 15B)의 오정렬이 발생된 경우, 도 3 및 도 4에 도시된 바와 같이, Cgs의 면적(A, B)이 각각 다르게 나타난다.However, since the exposure area of the exposure machine used in the exposure process is about 6 inches or 5 inches, in order to fabricate TFT-LCDs of 6 inches or more, the divisional exposure must be performed using a plurality of photo masks. Misalignment of the liver occurs. For example, when misalignment of the source and drain 15A, 15B occurs, as shown in Figs. 3 and 4, the areas A and B of Cgs appear differently.
이에 따라, 각 샷의 ΔVp가 서로 다르게 나타나고, 액정에 인가되는 실효전압의 차이가 발생된다. 이에 따라, 샷간의 휘도차가 발생될 뿐만 아니라 화면에 플리커 현상이 발생되어 결국 TFT-LCD의 화질이 저하된다.Accordingly, ΔVp of each shot is different from each other, and a difference in the effective voltage applied to the liquid crystal is generated. As a result, not only the luminance difference between shots is generated, but also a flicker phenomenon occurs on the screen, resulting in deterioration of the image quality of the TFT-LCD.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 샷간의 오정렬이 발생하더라도 일정한 Cgs값을 얻음으로써 화질을 향상시킬 수 있는 TFT-LCD를 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a TFT-LCD capable of improving image quality by obtaining a constant Cgs value even when misalignment between shots occurs.
상기한 본 발명의 목적을 달성하기 위하여, 본 발명에 따른 TFT-LCD는 절연기판 상에 매트릭스 형태로 배치된 게이트 라인 및 데이터 라인; 상기 게이트 라인과 데이터 라인간 교차부에 배치된 박막트랜지스터; 및 상기 게이트 라인과 데이터 라인에 의해 한정된 화소영역 내에 상기 박막트랜지스터와 콘택하도록 배치된 화소전극을 포함하는 박막트랜지스터 액정표시소자에 있어서, 상기 박막트랜지스터는, 상기 게이트 라인으로부터 인출된 게이트 전극과, 상기 게이트 상부에 배치된 액티브층과, 상기 데이터 라인으로부터 인출되고 상기 게이트 전극의 일측과 오버랩되면서 이격해서 서로 평행하게 배열된 제1 및 제2 드레인 전극과, 상기 게이트 전극의 타측과 오버랩되면서 상기 제1 드레인 전극과 제2 드레인 전극 사이의 중앙에 배치되고 상기 화소전극과 콘택되는 소오스 전극;을 포함하는 것을 특징으로 하는 박막트랜지스터 액정표시소자.In order to achieve the above object of the present invention, a TFT-LCD according to the present invention includes a gate line and a data line disposed in a matrix form on an insulating substrate; A thin film transistor disposed at an intersection between the gate line and the data line; And a pixel electrode arranged to contact the thin film transistor in a pixel region defined by the gate line and the data line, wherein the thin film transistor comprises: a gate electrode drawn from the gate line; An active layer disposed on the gate, first and second drain electrodes drawn from the data line and spaced apart from each other while overlapping with one side of the gate electrode, and overlapping with the other side of the gate electrode; And a source electrode disposed in the center between the drain electrode and the second drain electrode and in contact with the pixel electrode.
또한, 제 1 및 제 2 드레인 전극과 소오스 전극 사이의 이격거리는 서로 같고, 소오스 전극의 폭은 이격거리보다 크다. 또한, 소오스 전그과 게이트 전극 사이의 캐패시턴스의 면적은 게이트 절연막의 단위면적당 용량×게이트의 폭×(소오스 전극의 폭+소오스 전극과 드레인 전극 사이의 거리)이다.Further, the separation distance between the first and second drain electrodes and the source electrode is the same, and the width of the source electrode is larger than the separation distance. In addition, the area of the capacitance between the source electrode and the gate electrode is the capacity per unit area of the gate insulating film x the width of the gate x (the width of the source electrode + the distance between the source electrode and the drain electrode).
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 5는 본 발명의 실시예에 따른 TFT-LCD를 나타낸 평면도이다.5 is a plan view illustrating a TFT-LCD according to an embodiment of the present invention.
도 5를 참조하면, 유리와 같은 투명한 절연기판(미도시) 상에 게이트 라인 (51)과 데이터 라인(55)이 매트릭스 형태로 배열되고, 게이트 라인(51)과 데이터 라인(55)의 교차부분에 TFT(200)가 배치된다. TFT(200)는 게이트 라인(51)에서 돌출된 게이트(51A)와, 게이트(51A) 상부에 배치된 액티브층(53)과, 데이터 라인(55)에서 돌출되고 게이트(51A)의 일측과 오버랩하면서 서로 평행하게 배열된 제 1 및 제 2 드레인(55B, 55C)과, 제 1 및 제 2 드레인(55B, 55C) 상의 중앙에서 게이트(51A)의 다른측과 오버랩하면서 제 1 및 제 2 드레인(55B, 55C)과 평행하게 배열된 소오스(55A)를 포함한다. Referring to FIG. 5, a gate line 51 and a data line 55 are arranged in a matrix on a transparent insulating substrate (not shown) such as glass, and an intersection portion of the gate line 51 and the data line 55 is formed. The TFT 200 is arranged in this. The TFT 200 overlaps the gate 51A protruding from the gate line 51, the active layer 53 disposed above the gate 51A, and protruding from the data line 55 and overlapping one side of the gate 51A. The first and second drains 55B and 55C arranged in parallel with each other, and the first and second drains while overlapping the other side of the gate 51A at the center on the first and second drains 55B and 55C. Sources 55A arranged parallel to 55B, 55C).
여기서, 소오스(55A)와 제 1 및 제 2 드레인(55B, 55C)과의 이격거리(L1, L2)는 같고, 소오스(55A)의 폭(W2)은 이격거리(L1, L2) 보다 크다. 또한, 게이트 라인(51)과 데이터 라인(55)에 의해 형성된 공간에는 TFT(200)의 소오스(55A)와 콘택하는 화소전극(56)이 배치된다. Here, the separation distances L1 and L2 between the source 55A and the first and second drains 55B and 55C are equal, and the width W2 of the source 55A is larger than the separation distance L1 and L2. In the space formed by the gate line 51 and the data line 55, a pixel electrode 56 in contact with the source 55A of the TFT 200 is disposed.
상기한 바와 같이, 본 발명에서는 소오스(55A)를 제 1 및 제 2 드레인(55B, 55C) 사이에서 그들과 평행하게 배치한다. 또한, Cgs의 면적(C)는 소오스(55A)와 제 1 및 제 2 드레인(55B, 55C) 사이의 중간부터 게이트(51A)와 오버랩되는 부분의 반도체층(53)의 면적으로서, 다음과 같이 나타낼 수 있다. As described above, in the present invention, the source 55A is disposed in parallel between them between the first and second drains 55B and 55C. The area C of Cgs is the area of the semiconductor layer 53 in the portion overlapping with the gate 51A from the middle between the source 55A and the first and second drains 55B and 55C, as follows. Can be represented.
Cgs의 면적(C) = Ci×W1×(W2+L1)Area of Cgs (C) = Ci x W1 x (W2 + L1)
여기서, Ci는 게이트 절연막의 단위면적당 용량이고, W1은 게이트의 폭이고, W2는 소오스의 폭이고, L1은 드레인과 소오스 사이의 거리이다.Where Ci is the capacitance per unit area of the gate insulating film, W1 is the width of the gate, W2 is the width of the source, and L1 is the distance between the drain and the source.
도 6 및 도 7은 마스크 샷간의 오정렬이 발생되어, 게이트(55A)와 데이터 라인(55) 사이의 간격(M1, M2)이 서로 다른 경우를 나타낸다. 그러나, 도 6 및 도 7에 도시된 바와 같이, 마스크 샷간의 오정렬이 발생하더라도, 드레인(55B, 55C)과 소오스(55A)의 간격(L1, L2)이 일정하기 때문에, 각각의 Cgs의 면적(C1, C2)가 일정하게 나타남을 알 수 있다.6 and 7 illustrate a case in which misalignment between mask shots occurs, and the distances M1 and M2 between the gate 55A and the data line 55 are different from each other. However, as shown in Figs. 6 and 7, even if misalignment between mask shots occurs, the intervals L1 and L2 between the drains 55B and 55C and the source 55A are constant, so that the area of each Cgs ( It can be seen that C1 and C2) are constantly shown.
즉, Cgs가 일정하기 때문에, TFT의 화질을 결정하는 ΔVp가 샷마다 동일하게 나타나고, 액정에 인가되는 실효전압의 차이가 발생되지 않는다. 이에 따라, 샷간의 휘도차가 발생되지 않을 뿐만 아니라 플리커 현상이 방지된다.That is, since Cgs is constant, ΔVp for determining the image quality of the TFT appears the same for each shot, and no difference in the effective voltage applied to the liquid crystal is generated. Accordingly, not only does the luminance difference between shots occur, but also the flicker phenomenon is prevented.
상기한 본 발명에 의하면, 드레인을 이중으로 배치하고 그 사이에 소오스를 배치함으로써 마스크 샷 간의 오정렬에 따른 Cgs 값의 변동을 방지하므로, 샷간의 휘도차 및 플리커 현상등이 효과적으로 방지됨으로써, 결국 TFT-LCD의 화질이 개선된다.According to the present invention described above, by disposing the drains in duplicate and disposing the source therebetween, the variation of the Cgs value due to the misalignment between the mask shots is prevented, so that the luminance difference and the flicker phenomenon between the shots can be effectively prevented, resulting in a TFT- LCD image quality is improved.
또한, 드레인이 이중 배치에 의해 일측의 드레인의 단선이 발생되더라도 리페어가 가능하므로, 수율 향상의 효과를 얻을 수 있다.In addition, since the drain can be repaired even if disconnection of the drain on one side occurs due to the double arrangement, the effect of yield improvement can be obtained.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
도 1은 종래의 TFT-LCD의 평면도.1 is a plan view of a conventional TFT-LCD.
도 2는 종래의 TFT의 단면도.2 is a cross-sectional view of a conventional TFT.
도 3 및 도 4는 종래의 마스크 오정렬에 의한 Cgs의 차이를 나타낸 평면도.3 and 4 are plan views showing differences in Cgs due to conventional mask misalignment.
도 5는 본 발명의 실시예에 따른 TFT-LCD의 평면도.5 is a plan view of a TFT-LCD according to an embodiment of the present invention;
도 6 및 도 7은 마스크 오정렬이 발생된 경우 본 발명의 Cgs를 나타낸 평면도.6 and 7 are plan views showing Cgs of the present invention when mask misalignment occurs.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
51 : 게이트 라인 53 : 액티브층 51: gate line 53: active layer
55 : 데이터 라인 55A : 소오스55: data line 55A: source
55B, 55C : 제 1 및 제 2 드레인55B, 55C: first and second drain
56 : 화소전극 56 pixel electrode
W1 : 게이트의 폭W1: width of gate
W2 : 소오스의 폭 W2: width of source
L1, L2 : 소오스와 드레인 사이의 이격거리L1, L2: separation distance between source and drain
C, C1, C2 : Cgs의 면적 C, C1, C2: Area of Cgs
200 : TFT200: TFT
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| KR20040032603A (en) * | 2002-10-10 | 2004-04-17 | 비오이 하이디스 테크놀로지 주식회사 | Digital x-ray detector |
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| KR20080030799A (en) | 2006-10-02 | 2008-04-07 | 삼성전자주식회사 | Thin film transistor substrate |
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| JPH01267617A (en) * | 1988-04-20 | 1989-10-25 | Seiko Epson Corp | thin film transistor |
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| JPH06258667A (en) * | 1993-03-05 | 1994-09-16 | Hitachi Ltd | Liquid crystal display device |
| KR19990016188A (en) * | 1997-08-13 | 1999-03-05 | 윤종용 | Thin film transistor substrate for liquid crystal display |
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| JPH01267617A (en) * | 1988-04-20 | 1989-10-25 | Seiko Epson Corp | thin film transistor |
| JPH05119347A (en) * | 1991-10-28 | 1993-05-18 | Sanyo Electric Co Ltd | Liquid crystal display device |
| JPH06258667A (en) * | 1993-03-05 | 1994-09-16 | Hitachi Ltd | Liquid crystal display device |
| KR19990016188A (en) * | 1997-08-13 | 1999-03-05 | 윤종용 | Thin film transistor substrate for liquid crystal display |
| KR19990032427A (en) * | 1997-10-17 | 1999-05-15 | 윤종용 | Thin Film Transistor for Liquid Crystal Display |
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