KR100492792B1 - Voltage generator of ferroelectric memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generator of a ferroelectric memory device. In particular, in constructing a reference voltage generator in a ferroelectric memory device, a plurality of reference cells are arrayed to selectively drive the plurality of reference cells in accordance with an address change. In order to compensate for the shortening of the lifetime of the chip due to the Fatigue phenomenon, the present invention provides a reference bit line precharge unit for removing the voltage difference across the ferroelectric capacitor by precharging the reference bit line pair to ground level, and A reference bit line equalization unit for charge distribution of a reference bit line pair, a reference cell array unit having a plurality of reference cells in parallel at both ends of the reference bit line pair, and a storage information in the plurality of reference cells A reference cell information control unit for controlling to alternately store and a plurality of input addresses A life cycle of a chip is provided by providing a reference cell array driver for generating a plurality of designated reference word line enable signals and a plurality of designated reference plate line enable signals for selectively driving the plurality of reference cells according to a combination of switch signals. It can be extended and thus reduce the cost relatively.

Description

Voltage generator of ferroelectric memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generator of a ferroelectric memory device. In particular, in constructing a reference voltage generator in a ferroelectric memory device, a plurality of reference cells are arrayed to selectively drive the plurality of reference cells in accordance with an address change. The present invention relates to a reference voltage generator of a ferroelectric memory device for compensating shortening of a chip life due to a fatigue phenomenon.

A memory made of ferroelectric material can make a nonvolatile memory by using a property that maintains a certain amount of charge due to the characteristics of the ferroelectric even when there is no potential difference across the capacitor.

1A to 1B illustrate hysteresis curves showing a relationship between a symbol of a capacitor made of ferroelectric and a voltage-charge amount of a ferroelectric capacitor.

As shown in the hysteresis curve of FIG. 1B, the polarization state of the ferroelectric capacitor storing information of "1" is in the state of P1 even if the voltage difference between both ends of a and b disappears, and stores information of "0". In the ferroelectric capacitor, the polarization state is in the state of P3.

When a large enough negative voltage (> │Vc |) is applied across a and b of the ferroelectric capacitor to read the stored information, the ferroelectric capacitor that stores the information of "1" maintains the polarization state of P1. It moves to the state of P2 along the hysteresis curve to generate charge as much as Qm1, and if the voltage difference between both ends is removed again, it goes to the state of P3, and then it is restored while the information is stored in P3 state again. The state of P1 is returned.

In addition, the ferroelectric capacitor which stores the information of "0" becomes the state of P2 in the P3 state, generates charge as much as Qm0, and returns to the original position P3 through the restoring process.

In this case, a memory for storing binary information by detecting a difference between charges Qm1 and Qm0 generated may be configured.

Various types of memories are constructed by using the characteristics of such ferroelectric capacitors.

3 is an embodiment of a core configuration in a conventional memory.

To read the information stored in this circuit, when the gate of the switching transistor is turned on and the plate voltage is driven high, the bit lines have different voltages V0 and V1 according to the information stored in the cell, "0" or "1".

Since these voltages V0 and V1 are small signals, they must be amplified using a sense amplifier.

To amplify these V0 and V1, a reference voltage having a value between V0 and V1 should be applied to the bit line bar.

That is, it is determined whether the information of the cell is 0 or 1 by amplifying with a sense amplifier whether the voltage V0 or V1 of the bit line is lower or higher than the reference voltage applied to the bit line bar.

In generating the reference voltage, in the conventional circuit (IEEE Solid-Static Circuit, Vol. 31, NO. 11, November 1996, pp1625-pp1633), two ferroelectrics having the same area as the memory cell in the reference voltage generator 20 "0" and "1" are stored in the reference cells C1 and C2 made of capacitors, respectively, to turn on the reference word line driving signal RWL as in the reading process of the memory cell, and to set the reference plate line driving signal RPL to "high". ", And the voltage generated by the amount of charges occupied by the reference bit lines RBL and RBLB are equalized so that the induced voltage becomes an intermediate value of the voltage when the voltages" 0 "and" 1 "are not selected. It is amplified by comparing it to the induced voltage on the memory cell by loading it on the unused bit line (the role of DTGT and DTGN).

However, in the related art, since one reference voltage generator is used for a bit line in which a plurality of memory cells are arrayed as shown in FIG. 3, the number of use of the reference cell is increased as much as the number of arrays of memory cells.

As shown in FIG. 2, the ferroelectric capacitor has a Fatigue phenomenon in which the amount occupied by the capacitor gradually decreases as a result of the accumulation of the use frequency, thereby changing the voltage value induced by the amount of charge.

FIG. 2 is a diagram schematically illustrating a fatigue phenomenon, in which the hysteresis curve of the ferroelectric capacitor in the initial state is represented by a solid line, and when a sufficiently negative voltage is applied, the charge by Q0 is induced.

However, as the number of times of use of the cell increases, the state of the aged ferroelectric capacitor gradually decreases in the amount of charge as shown by the dotted line.

Thus, when looking at the problem of the conventional prior art, as shown in the reference voltage generator 20 of FIG. 3, the number of times of use is increased because the information of "0" is always stored in C1 and "1" is stored in C2. As the amount of charge decreases and the induced voltage changes, it is difficult to secure a sensing margin, which causes a problem in the reliability of the memory device.

More specifically, as shown in FIGS. 4A and 4B, the ferroelectric capacitor C1 storing "0" at the time of read / write is used because it repeats only the state (c → b → c). Aging by the number of times hardly occurs (FIG. 4A).

On the other hand, the ferroelectric capacitor C2 storing "1" repeats (a → b → c → d → a) states every time it is read / write (Fig. 4B) to loop ( Because of the looping, the amount of charges caused by the fatigue is more likely to be generated than the C1, and as the number of times of use increases, it is difficult to secure a sensing margin, which causes problems in chip reliability.

If 1024 memory cells are connected to one reference voltage generator 20, the cell used for the reference voltage generator 20 may age 1024 times faster than the memory cells.

Accordingly, the present invention was devised to solve the above-mentioned problems of the prior art, by arraying a plurality of reference cells used in the reference voltage generator of the ferroelectric memory to selectively use the reference cells as the addresses change. The purpose of the present invention is to provide a reference voltage generator of a ferroelectric memory device for increasing the number of times of use of a reference cell and securing chip reliability by reducing deterioration caused by the fatigue of the reference cell to 1 / N.

The reference voltage generator of the ferroelectric memory device according to the embodiment of the present invention for achieving the above object to precharge the reference bit line pair to the ground level to remove the reference bit line precharge to remove the voltage difference across the ferroelectric capacitor A reference cell array unit having a branch portion, a reference bit line equalization unit for charge distribution of the reference bit line pair, a plurality of reference cells in parallel at both ends of the reference bit line pair, and a plurality of reference cells A reference cell information control unit for controlling the storage information to be alternately stored; a plurality of designated reference word line enable signals and a plurality of designated reference plates for selectively driving the plurality of reference cells according to a combination of a plurality of input address signals; And a reference cell array driver for generating a line enable signal. The.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

5 shows an example of the reference voltage generator 30 proposed in the present invention. Referring to the configuration of the reference voltage generator 30 for generating a reference voltage in the memory cell array 10, the reference bit line RBL And a precharge unit 22 connected between the RBLBs and driven by the precharge driving signal PRL to precharge the reference bit lines RBL and RBLB to ground level to remove the voltage difference across the ferroelectric capacitor. And a reference bit line equalizer 24 connected between the reference bit lines RBL and RBLB and driven by an equalization signal EQ-RL to distribute charges of the reference bit lines RBL and RBLB. And a reference cell information control unit 26 connected between the reference bit lines RBL and RBLB and driven by a reference cell information control signal PDC to alternately store stored information 0 and 1 in the reference cell. ) And a pair of opposite phases First and second devices connected in parallel between the preparation lines RBL and RBLB and driven by the designated reference word line enable signal and the designated reference play line enable signal, respectively, to read / write the storage information (0 and 1). And a reference cell array unit 32 including third and fourth reference cell units 32-1, 32-2, 32-3, and 32-4.

Each of the first, second, third, and fourth reference cell units 32-1, 32-2, 32-3, and 32-4 is simultaneously supplied with a designated reference word line enable signal to a gate and a reference bit line ( Two NMOS transistors connected to RBL and RBLB), and two ferroelectric capacitors having one electrode connected to one terminal of the NMOS transistor and the other terminal connected to a designated reference line.

For convenience, ferroelectric capacitors are denoted as C1, C2, C3, C4, C5, C6, C7, and C8 in each reference cell unit of FIG. 5.

FIG. 6 illustrates a reference cell array driver 34 for driving the reference cell array unit 32 of FIG. 5.

Referring to the configuration, an address decoder 36 for receiving and decoding two address signals A0 and A1 to generate four reference cell selection signals SW1, SW2, SW3, and SW4, and the four reference cells Designated reference word line for receiving selection signals SW1, SW2, SW3, and SW4 respectively and simultaneously receiving the reference word line enable signal RWL and the reference plateline enable signal RRP to enable one reference cell. The reference cell driver 38 includes four designated reference cell drivers 38-1, 38-2, 38-3, and 38-4 for outputting an enable signal and a designated reference play line enable signal.

The address decoder 36 includes: a first inverter for inverting and outputting A0; a sixth inverter for inverting and outputting A1; a third inverter for receiving and inverting and outputting the first inverter output signal; A seventh inverter that receives a six inverter output signal and inverts the sixth inverter output signal, a first NAND gate that receives and logically performs an output signal of the first inverter and a sixth inverter output signal, the first inverter output signal and the first inverter; A second NAND gate that receives and logically operates an inverter output signal, a third NAND gate that receives and logically operates the third inverter output signal and the sixth inverter output signal, the third inverter output signal, and the third inverter; A fourth NAND gate for logically operating an inverter output signal, a second inverter for receiving the first NAND gate output signal and inverting the same, and outputting a reference cell selection signal SW1; A fourth inverter configured to receive a second NAND gate output signal and invert the output signal to output a reference cell selection signal SW2; a fifth inverter configured to receive the inverted third NAND gate output signal and output the reference cell selection signal SW3; And an eighth inverter that receives the NAND gate output signal and inverts the signal to output the reference cell selection signal SW4.

FIG. 7 is a circuit diagram of each designated reference cell driver constituting the reference cell driver 38 of FIG.

The configuration for this is as follows.

A fifth NAND gate that receives and operates a reference word line enable signal RWL and a reference cell selection signal, and a sixth NAND that receives and logically operates a reference plate line enable signal RPL and the reference cell selection signal; A ninth inverter receiving a gate, the fifth NAND gate output signal, and inverting the same to output a designated reference word line enable signal, and receiving the inverted sixth NAND gate output signal and inverting the specified reference plate line enable signal; It consists of a 10th inverter which outputs.

Here, SW may be any one of SW1, SW2, SW3, and SW4, respectively.

Similarly, RWL can be any of RWL1, RWL2, RWL3, RWL4, and RPL as well.

Hereinafter, the overall operation of the reference voltage generator 30 according to the present invention having the above-described configuration and the effects thereof will be described.

In the present invention, three pairs of reference cells are added to a pair of reference cells included in the conventional reference voltage generator 20. The reference cell array unit 32 having N pairs of reference cells can be configured by generalizing them.

In this case, it is possible to increase the lifespan of about N times. In one embodiment of the present invention, four pairs of reference cells are used as an example, and the lifespan of about 4 times can be achieved than the conventional reference voltage generator 20.

Referring to the overall operation for selectively driving the four pairs of reference cells, as shown in FIG. 6, two addresses are selected to select the four pairs of reference cells (first, second, third, and fourth reference cell units). Input is required.

In addition, a reference word line enable signal (RWL) for driving a conventional reference word line and a reference plate enable signal (RPL) for driving a reference plate line are required.

8 illustrates a process of combining the signals to generate a new signal capable of selectively driving four pairs of reference cells.

First, there is an address decoder unit 36 in which two addresses are combined to generate four sections in order to select one reference cell unit from the first, second, third, and fourth reference cell units.

That is, the address decoder 36 for outputting four reference cell selection signals SW1, SW2, SW3, and SW4 by inputting the address signals A0 and A1 will be described below.

When "logic low" is input to each of the address inputs A0 and A1, SW1 waits in the "high" state as shown in FIG. 8C among the signals for selecting one reference cell unit, and the reference word line in When the enable signal RWL and the reference plate enable enable signal RPL are input, the designated reference cell driver 38-1 of the reference cell driver 38 causes (g), (h), (i), (j As shown in Fig. 6), the reference word line enable signal (RWL) and the reference plate line enable signal (RPL) and the specified reference word line enable signal (RWL1) and the specified reference plate line are new signals having the same phase and pulse width. The enable signal RPL1 is generated.

Next, when "Logic High" is input to the address input A0 and a "Logic Low" signal is input to A1, the reference cell selection signal SW2 waits in a "high" state as shown in (d), and the designated reference cell driver By 38-2, the designated reference word line enable signal RWL2 and the designated reference line enable signal RPL2 are selected as shown in (k) and (1).

Next, when the address signal A0 becomes "logic low" and A1 becomes "logic high", as shown in (e), the reference cell selection signal SW3 waits in a "high" state and sends the signal to the designated reference cell driver 38-3. (M) and (n), the designated reference word line enable signal RWL3 and the designated reference line enable signal RPL3 are selected, and when both the address signals A0 and A1 become "logic high", (f) As shown in FIG. 4, the SW4 waits in the "high" state and is designated by the designated reference cell driver 38-4 as shown in (o) and (p), and the designated reference word line enable signal RWL4 and the designated reference plateline. Enable signal RPL4 is selected.

When one of the first, second, third, and fourth reference cell units is selected by the above operation, the reference voltage generator 30 applies a pulse as shown in FIGS. 4A and 4B to apply the reference voltage. Will be generated.

In this way, when a plurality of reference cells are arrayed and a reference voltage is generated by selecting a pair of reference cells according to an input change of an address, the reference voltage generator 20 generates about N than a pair of reference cells. The life of the chip can be extended by about twice (4 times in the embodiment of the present invention).

The reason is that even if a plurality of addresses change randomly, since each address will be similar to the case of "logic low" and "logic high", the number of times the reference cell is written will be similar.

In this case, since the aging phenomenon (Fatigue phenomenon) of the cell that the reference cell storing "1" in the existing reference voltage generator 20 having a pair of reference cells can be multiplied into a plurality of cells, The charge reduction caused by the chip is significantly reduced, thereby extending the life of the chip.

In summary, in order to improve the reliability of the chip by extending the life of the reference cell, the present invention suggests a method in which a plurality of reference cells can also be selectively used, such as the memory cell array 10. However, the reference If the cells are arrayed as many as the memory cell array 10, the area of the chip becomes too large. If the number of reference cells is arrayed and selectively used within a range that does not significantly affect the chip area, the lifetime of the chip is extended. It can be significantly improved.

As described above, since the present invention can selectively use a plurality of arrays of reference cells, the life of the chip can be remarkably improved and the relative cost can be reduced.

Preferred embodiments of the present invention are for the purpose of illustration and various modifications, changes, substitutions and additions are possible to those skilled in the art through the spirit and scope of the present invention as set forth in the appended claims.

1A is a symbol of a typical ferroelectric capacitor.

Figure 1b is a hysteresis curve graph showing the relationship between the voltage-charge amount of a typical ferroelectric capacitor.

Figure 2 is a hysteresis curve graph for explaining the fatigue phenomenon of a typical ferroelectric capacitor.

3 is a circuit diagram showing a relationship between a general memory cell array and a reference voltage generator.

4A and 4B are diagrams of signals for driving the reference voltage generator of FIG. 3 and graphs showing voltage relationships across ferroelectric capacitors by driving signals.

5 is a detailed circuit diagram of a reference voltage generator according to an embodiment of the present invention.

FIG. 6 is a detailed circuit diagram of a reference cell array driver for selectively driving the reference voltage generator of FIG. 5. FIG.

7 is an internal circuit of the reference cell selector of FIG.

FIG. 8 is a timing diagram for selectively driving a reference cell in FIG. 6. FIG.

<Explanation of symbols for main parts of drawing>

10: memory cell array 20, 30: reference voltage generator

32: reference cell array unit 34: reference cell array driver

36: address decoder 38: reference cell driver

38-1, 38-2, 38-3, 38-4: Designated reference cell driver

22: precharge unit 24: reference bit line equalization unit

26: reference cell information control unit RBL, RBLB: reference bit line

PRL: Precharge drive signal EQ-RL: Equalize signal

PDC: Reference cell information control signal A0, A1: Address signal

RWL: Reference word line enable signal RPL: Reference play line enable signal

SW1, SW2, SW3, SW4: Reference Cell Selection Signal

RWL1, RWL2, RWL3, RWL4: Specified reference word line enable signal

RPL1, RPL2, RPL3, RPL4: Specified reference play line enable signal

Claims (6)

A reference bit line precharge unit for precharging the reference bit line pair to ground level to remove the voltage difference across the ferroelectric capacitor; A reference bit line equalizer for distributing charges of the reference bit line pairs; A reference cell array unit including a plurality of reference cells in parallel at both ends of the reference bit line pair; And A reference cell information control unit which controls to alternately store the storage information in the plurality of reference cells; A reference cell array driver for generating a plurality of designated reference word line enable signals and a plurality of designated reference plate line enable signals for selectively driving the plurality of reference cells according to a combination of a plurality of input address signals; A reference voltage generator of a ferroelectric memory device, characterized in that comprising a. The method of claim 1, wherein the reference cell array driver, An address decoder to output a plurality of reference cell selection signals by combining the plurality of input address signals; Receiving a plurality of reference word line enable signals, a reference plate line enable signal, and the plurality of reference cell selection signals, respectively, to receive the plurality of specified reference word line enable signals and the plurality of specified reference plate line enable signals; And a reference cell driver including a plurality of designated reference cell drivers respectively output to four reference cells. The method of claim 2, wherein the address decoder, A plurality of inverters for inverting the plurality of input address signals, respectively; And A plurality of NAND gates for NAND combining the outputs of the plurality of inverters A reference voltage generator of a ferroelectric memory device, characterized in that it comprises a. The method of claim 2, wherein the plurality of designation reference cell driver, A first logic gate configured to logically operate the reference word line enable signal and the plurality of reference cell selection signals; And A second logic gate for performing a logic operation on the reference plate line enable signal and the plurality of reference cell selection signals A reference voltage generator of a ferroelectric memory device, characterized in that it comprises a. 5. The reference voltage generator of claim 4, wherein the first and second logic gates are NAND gates. The method of claim 1, wherein the plurality of designation reference cell driver, A ferroelectric for outputting the specified reference word line enable signal and the designated reference play line enable signal to have the same phase and the same pulse width as the reference word line enable signal and the reference plate line enable signal, respectively. Reference voltage generator for memory devices.

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