KR100504688B1 - Test circuit for semiconductor chip - Google Patents

Abstract

The present invention relates to a test circuit of a semiconductor chip, and more particularly, to a boundary scan chain circuit, and receives a right shift scan data (RSD) and a left shift scan data (LSD), respectively, and selectively outputs one signal. First selecting means (230); Second selecting means (240) for receiving an output of the first selecting means (230) and a signal (DI) output from an internal circuit of the semiconductor chip and selectively outputting one signal; Latch means (250) for inputting and latching an output of the second selection means (240); And a third selecting means 260 for receiving an output of the latch means 250 and a signal DI output from an internal circuit of the semiconductor chip and selectively outputting one signal. The latch means 250 latches data output at the time and shifts it left / right to output serially. Therefore, the shift operation can be performed in the direction required for the test of the semiconductor chip, so that data on the test result can be output in a short time, thereby saving test time of the semiconductor chip. It is also very useful for debugging semiconductor chips.

Description

Semiconductor Chip Test Circuits {TEST CIRCUIT FOR SEMICONDUCTOR CHIP}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test and debugging circuit of a semiconductor chip, and more particularly, to a boundary scan chain circuit that is easy to test and debug a chip through a boundary scan. It is about.

As the degree of integration of semiconductor chips increases and becomes more complex, test problems are becoming very important. There is a boundary scan chain circuit as one of the test circuits of the conventional semiconductor chip.

1 is a block diagram schematically illustrating a circuit configuration of a conventional boundary scan chain, and FIG. 2 is a detailed circuit diagram illustrating an internal circuit configuration of a boundary scan cell illustrated in FIG. 1.

Referring to FIG. 1, the boundary scan chain circuit includes a plurality of boundary scan cells (hereinafter, abbreviated as 'scan cells'). Two of the scan cells 110 and 120 are shown. The first and second scan cells 110 and 120 are configured on a semiconductor chip, which are connected to corresponding pads (not shown), respectively.

2 shows a detailed circuit for one scan cell. As shown in FIG. 2, the scan cell includes first and second multiplexers (MUX) 130 and 150, and a D flip-flop 140 for data latches. The first multiplexer 130 receives a signal DI output from an internal circuit (not shown) and scan data SI shifted from a scan cell configured at a side of the first multiplexer 130, and selectively provides it to the D flip-flop 140. The second multiplexer 150 receives the DI signal and the output of the D flip-flop 140 and selectively outputs them. The output of the D flip-flop 140 is shifted to the next scan cell. The first multiplexer 130 provides a shift_DR signal (a shift operation when '1' and a capture operation when '0') as a selection signal, and a mode signal as a selection signal to the second multiplexer 150. The operation of the conventional boundary scan chain circuit as described above is as follows.

First, predetermined signals are input to each pad, and a corresponding chip is operated. The circuits in the chip then operate to output the signals in response to the pads (not shown). Each scan cell latches (or captures) a corresponding signal. Each scan cell shifts the latched data according to the sheet operation to output serial scan data to a corresponding output terminal (not shown).

As described above, the boundary scan chain circuit is gradually expanded to provide a debugging environment when the chip is operating, as well as testing a general semiconductor chip. As the function is expanded as described above, the following problems occur.

Since conventional boundary scan chain circuits can perform data shift operations in only one direction, a lot of time is required when the data of a specific boundary scan cell needs to be accessed when the scan chain is long. This will occur.

Accordingly, an object of the present invention is to provide a boundary scan chain circuit capable of bidirectional shifting operations to reduce the test and debugging time of a semiconductor chip as proposed to solve the above-mentioned problems.

According to one aspect of the present invention for achieving the object of the present invention as described above, a semiconductor chip test circuit having a plurality of boundary scan cells: receives the right shift scan data and the left shift scan data, respectively, First selecting means for outputting one signal; Second selection means for receiving an output of the first selection means and a signal output from an internal circuit of the semiconductor chip and selectively outputting one signal; Latch means for inputting and latching an output of the second selection means; And third selecting means for receiving an output of the latching means and a signal output from an internal circuit of the semiconductor chip, and selectively outputting one signal. Can be latched and shifted left / right to output in series.

In this embodiment, the first to third selecting means are constituted by a multiplexer.

In this embodiment, the latch means consists of a D flip-flop.

In this embodiment, the semiconductor chip test circuit is built in the semiconductor chip and is composed of the same single chip.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram schematically illustrating a circuit configuration of a boundary scan chain of the present invention, and FIG. 4 is a detailed circuit diagram showing a circuit configuration of a boundary scan cell shown in FIG. 3.

The novel boundary scan chain circuit of the present invention is capable of bidirectional shift operation. 3 illustrates some configurations of a plurality of boundary scan cells of a boundary scan chain circuit according to the present invention. As shown in FIG. 3, the first and second boundary scan cells 210 and 220 perform a left or right shift operation according to a selection signal for selecting a left and right shift operation.

Specifically, FIG. 4 shows a detailed circuit of the boundary scan cell.

Referring to FIG. 4, boundary scan cells (hereinafter, abbreviated as 'scan cells') according to an exemplary embodiment of the present invention may include first to third multiplexers 230, 240, and 260 and D flip-flops for data latches. 250).

The first multiplexer 230 inputs left scan data LSD and right scan data RSD to selectively output one signal in response to an input of the selection signal select. That is, the left scan data LSD is output during the left shift operation, and the right scan data RSD is output during the right shift operation. The second multiplexer 240 inputs the output of the first multiplexer 230 and the output signal DI of the internal circuit, and inputs the selection signal shift_DR ('0', the internal output signal DI to capture). , If it is '1', shift is performed). The D flip-flop 250 receives and latches an output of the second flip-flop 240 in synchronization with the input of the synchronization signal clock_DR (test clock). The third multiplexer 260 inputs the output signal DI of the internal circuit and the output of the D flip-flop 250 and selectively outputs one signal in response to the input of the selection signal mode.

The boundary scan chain circuit including a plurality of scan cells having the above configuration can perform left and right shift operations together with adjacent scan cells. The operation of the boundary scan chain circuit of the present invention is as follows.

First, predetermined signals are input to each pad (not shown), and a corresponding chip is operated. The circuits in the chip then operate to output the signals in response to the pads (not shown). Each scan cell latches (or captures) a corresponding signal. Each scan cell shifts the latched data according to the shift operation, and serial scan data is output to a corresponding output terminal (not shown). Here, the shift operation to the left or right is performed according to the input of the selection signal select input to the first multiplexer 230. Therefore, the shift operation can be performed in the required direction.

According to the present invention as described above, since the shift operation is performed in the required direction during the test of the semiconductor chip, data for the test result can be output within a short time, thereby saving test time of the semiconductor chip. It also saves time when debugging semiconductor chips.

1 is a block diagram schematically showing a circuit configuration of a conventional boundary scan chain;

FIG. 2 is a detailed circuit diagram showing an internal circuit configuration of the boundary scan cell shown in FIG. 1;

3 is a block diagram schematically showing a circuit configuration of a boundary scan chain of the present invention; And

4 is a detailed circuit diagram illustrating a circuit configuration of the boundary scan cell illustrated in FIG. 3.

Claims (4)

In a semiconductor chip test circuit having a plurality of boundary scan cells connected in series: Each boundary scan cell First selection means (230) for receiving right shift scan data (RSD) and left shift scan data (LSD), respectively, and selectively outputting one signal; Second selecting means (240) for receiving an output of the first selecting means (230) and a signal (DI) output from an internal circuit of the semiconductor chip and selectively outputting one signal; Latch means (250) for inputting and latching an output of the second selection means (240); And third selecting means 260 for receiving the output of the latching means 250 and the signal DI output from the internal circuit of the semiconductor chip and selectively outputting one signal. And the latch means (250) latches the data output during the test of the semiconductor chip and selectively shifts the data to the left or right to output the data in series. The method of claim 1, And said first to third selecting means comprise a multiplexer. The method of claim 1, And said latch means comprises a D flip-flop. The method of claim 1, The semiconductor chip test circuit is a semiconductor chip test circuit, characterized in that composed of a single chip embedded in the semiconductor chip.

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