KR100515337B1 - A driving apparatus and a method of plasma display panel - Google Patents

Abstract

The present invention relates to an apparatus and method for driving a plasma display panel capable of forming wall charges and improving contrast, which are advantageous for addressing.

According to the driving method of the plasma display panel according to the embodiment of the present invention, a dropping ramp waveform is applied to the scan electrode during the first period in the reset period of each subfield, and the sustain electrode is floated in some of the first periods so that The voltage is lowered to a voltage corresponding to the voltage applied to the scan electrode and the voltage across the panel capacitor. As a result, the voltage difference between the scan electrode and the sustain electrode does not change, thereby preventing the disappearance of the negative wall charges present in the scan electrode. That is, it becomes a state of favorable wall charge in the addressing operation after the reset period, and further improves the contrast.

Description

A driving apparatus and a driving method of the plasma display panel {A DRIVING APPARATUS AND A METHOD OF PLASMA DISPLAY PANEL}

The present invention relates to a driving apparatus of a plasma display panel (PDP) and a method thereof.

A plasma display panel is a flat panel display device that displays characters or images using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. First, a structure of a general plasma display panel will be described with reference to FIGS. 1 and 2.

1 is a partial perspective view of a plasma display panel, and FIG. 2 shows an electrode arrangement diagram of the plasma display panel.

As shown in FIG. 1, the plasma display panel includes two glass substrates 1 and 6 facing each other apart. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 6, and the address electrodes 8 are covered with the insulator layer 7. The address electrode 8 and the partition 9 are formed on the insulator layer 7 between the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

As shown in FIG. 2, the electrode of the plasma display panel has a matrix structure of n × m. In the column direction, address electrodes A ₁ -A _m are arranged, and in the row direction, n rows of scan electrodes Y ₁ -Y _n and sustain electrodes X ₁ -X _n are arranged in pairs.

As a method of driving a conventional plasma display panel, there is a method described in US Publication No. US 2002/0075206 A1 to Takeda et al. The conventional driving method is a method of applying a ramp waveform falling in a reset period to a negative voltage level.

3 is a driving waveform diagram of a plasma display panel disclosed in the United States under the above number according to the prior art.

As shown in Fig. 3, each subfield includes a reset period, an address period, and a sustain period.

The reset section serves to erase the wall charge state of the previous sustain discharge and to set up wall charge in order to stably perform the next address discharge. The address period is a period in which a wall charge is accumulated in a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on in the panel. The sustain period is a period in which discharge for actually displaying an image on the addressed cell is performed.

Hereinafter, the operation of the conventional reset period will be described in more detail. As shown in Fig. 3, the conventional reset section includes an erase section, a scan electrode ramp up section, and a scan electrode ramp down section.

In the erase section, after the sustain discharge is completed, the erase ramp voltage is gradually applied to the sustain electrode X from 0 (V) to + Ve (V). Then, the wall charges formed on the sustain electrode X and the scan electrode Y gradually disappear.

The address electrode and sustain electrode X are held at 0 V during the scan electrode ramp up period, and a ramp voltage that rises slowly from the voltage Vs toward the voltage Vset is applied to the scan electrode Y. While this ramp voltage is rising, the first weak reset discharge occurs in all the discharge cells from the scan electrode Y to the address electrode and the sustain electrode X, respectively. As a result, negative wall charges are accumulated on the scan electrode Y, and positive wall charges are accumulated on the address electrode and the sustain electrode X at the same time.

Next, the scan electrode ramp falling section is a ramp that slowly descends to Vnf (negative voltage level) from the voltage Vs to the voltage Vs while maintaining the sustain electrode X at a constant voltage Ve. Apply voltage. While this ramp voltage is falling, again a second weak reset discharge occurs in every discharge cell. By this discharge, the wall charges formed in the sustain electrode X, the scan electrode Y and the address electrode A are partially erased and set to a state suitable for addressing. In addition, as shown in FIG. 3, in the falling section, a ramp voltage that drops to Onf (V) to Vnf, which is the last negative level, is applied. This is because the voltage difference between the scan electrode Y and the sustain electrode X becomes larger. The generation of wall charges is made more smooth, which is known to form wall charges favorable to the address discharge.

However, when the voltage is slowly lowered to the negative voltage level when the ramp is applied in the reset section as in the related art, a large amount of electrons are accumulated in the sustain electrode X, but the potential of the scan electrode Y is Vnf, which is a negative level. As compared with the case where the voltage falls to O (V), less electrons are accumulated in the scan electrode Y. In addition, if less electrons are accumulated in the scan electrode Y, addressing discharge of the address period may not occur. The driving voltage margin is also reduced.

The technical problem to be achieved by the present invention is to solve the problems of the prior art as described above, and to increase the contrast by suppressing unnecessary discharge generated in the case of going down to the negative voltage level in the falling ramp section of the reset section.

In addition, by forming a suitable wall charge in the reset period to prevent mis-discharge.

A plasma display panel driving method according to an aspect of the present invention for achieving the above object is a plasma comprising a first electrode, a second electrode, and a panel capacitor formed between the first electrode and the second electrode. A method of driving a display panel, the method comprising: (a) applying a first voltage waveform gradually decreasing from a first voltage to a second voltage to the first electrode during a first period; And (b) applying a second voltage waveform gradually decreasing from a third voltage to a fourth voltage in the second section, which is a partial section of the first section. An apparatus for driving a plasma display panel according to another aspect of the present invention is a device for driving a plasma display panel including a first electrode, a second electrode and a panel capacitor formed between the first electrode and the second electrode, A first voltage waveform electrically connected between the first electrode and a first power supply for supplying a first voltage, the first voltage waveform being turned on during a first period of a reset period and gradually decreasing to the first voltage to the first electrode; A first switch; And electrically connected between the second electrode and a second power supply for supplying a second voltage, and turned on in a second section, which is a section of the first section, to apply the second voltage to the first electrode. And a second switch that is turned off in a third section continuous to the second section of the first section to float the second electrode. In another aspect of the present invention, there is provided a apparatus for driving a plasma display panel, wherein the apparatus for driving a plasma display panel includes a first electrode, a second electrode, and a panel capacitor formed between the first electrode and the second electrode. And a first voltage waveform electrically connected between the first electrode and a first power supply for supplying a first voltage, the first voltage waveform being turned on during a first period of a reset period and gradually falling down to the first voltage at the first electrode. Applying a first switch; An electrical connection between the first electrode and a second power supply for supplying a second voltage lower than the first voltage, the electrode being turned on for a second period of the reset period and gradually decreasing to the second voltage at the first electrode; A second switch for applying a second voltage waveform; And a third section electrically connected between the second electrode and a third power supply for supplying a third voltage, and turned on in a third section, which is a section of a sum of the first section and the second section. And a third switch configured to apply a third voltage and to be turned off in a fourth section, the fourth section being a portion of the sum of the first section and the second section to float the second electrode.

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DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

4 illustrates a plasma display panel (PDP) according to an embodiment of the present invention.

As shown in FIG. 4, the PDP according to the embodiment of the present invention includes a plasma panel 100, an address driver 200, a scan driver 320, a sustain driver 340, and a controller 400.

The plasma panel 100 includes a plurality of address electrodes A1 to Am arranged in the column direction, scan electrodes Y1 to Yn arranged in the row direction, and sustain electrodes X1 to Xn.

The address driver 200 receives an address driving control signal SA from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode.

The scan driver 320 and the sustain driver 340 receive the scan electrode driving signal SY and the sustain electrode driving signal SX from the controller 200 and apply them to the scan electrode and the sustain electrode, respectively.

The controller 400 receives an image signal from an external source, generates an address driving control signal SA, a scan electrode driving signal SY, and a sustain electrode driving signal SX, respectively, and generates an address driver 200 and a scan driver 320, respectively. And to the holding driver 340.

5 is a view showing a driving waveform of the plasma display according to the first embodiment of the present invention. In Fig. 5, reference numerals X, Y, and A denote waveforms applied to the sustain electrode, the scan electrode, and the address electrode, respectively.

A driving method of the plasma display panel according to the first embodiment of the present invention will be described in more detail with reference to FIG. 5.

First, in the erase period, the voltage applied to the sustain electrode X is continuously raised from the ground voltage to the voltage Ve (for example, 190 V). Here, the ground voltages are applied to the scan electrodes Y1, ..., Yn and the address electrodes A1, ..., Am, respectively. As a result, a weak discharge occurs between the sustain electrode X and the scan electrode Y, and between the sustain electrode X and the address electrode, and negative wall charges are formed around the sustain electrode X. FIG.

The reset period may be divided into a rising section and a falling section. Hereinafter, the two sections will be described.

In the rising period of the reset period, the voltage applied to the scan electrode Y is continuously raised from the Vs voltage slightly lower than the Ve voltage to the Vset voltage much higher than the Ve voltage, and the ground voltage is applied to the address electrode and the sustain electrode X. Is authorized. While this ramp voltage is rising, the first weak reset discharge occurs in all the discharge cells from the scan electrode Y to the address electrode and the sustain electrode X, respectively. As a result, negative wall charges are accumulated on the sustain electrode Y, and positive wall charges are accumulated on the address electrode and the sustain electrode X at the same time.

In the falling section of the reset period, the sustain electrode X is first maintained at the Ve voltage, and the voltage applied to the scan electrode Y is continuously lowered from the Vs voltage to the negative voltage Vnf. When the voltage applied to the scan electrode Y is continuously lowered past 0 (V) to Vnf, which is a negative voltage level, the sustain electrode X has a Ve- | Vnf | Apply a continuously falling voltage until In this case, in FIG. 5, the voltage applied to the sustain electrode X is decreased when the voltage applied to the scan electrode Y passes 0 (V), but at this point, the voltage applied to the scan electrode Y is 0 ( At a point slightly higher or a little lower than V), the voltage applied to the sustain electrode X can be lowered.

Such a falling voltage can be directly supplied from the sustain driver, but as described below, the outputs of the sustain driver can all be electrically floating, that is, high impedance, so that the same effect can be obtained.

Next, in the address period, an address voltage Va is applied and addressed to the discharge cells to be displayed while the plurality of scan electrodes Y are scanned to select the discharge cells to be displayed from among the discharge cells.

Finally, in the sustain period to the discharge cells selected in the address period is generated by applying a sustain voltage V _s intersection between the scan electrode (Y) and the sustain electrode (X). In the sustain period, discharge occurs through a value corresponding to the sum of the wall charge voltage and the sustain voltage. As shown in Fig. 5, the waveforms of the address period and the sustain period are the same as in the prior art, so detailed description thereof will be omitted below.

As the falling voltage is applied to the sustain electrode X when the voltage applied to the scan electrode Y passes 0 (V) in the falling period of the reset period as described above, the electrons present in the scan electrode Y No longer removed.

Fig. 7 is a diagram showing the wall charge state after the reset period in the first embodiment of the present invention. Fig. 7A shows a conventional wall charge state after the reset period (refer to the wall charge state after the reset period in the case of the waveform as shown in Fig. 3), and Fig. 7B shows a first embodiment of the present invention. The wall charge state after the example reset period is shown.

7 (a) and 7 (b) show that more negative wall charges exist in the scan electrode Y after the reset period of the first embodiment of the present invention. This is because the voltage difference between the scan electrode Y and the sustain electrode X is kept constant from the moment when the scan electrode Y becomes negative in the falling period of the reset period, so that the electrons in the scan electrode Y It is no longer removed.

This forms a more advantageous wall charge state at the time of address discharge in the address period. That is, addressing can be performed by applying a lower external voltage in the address period. In addition, the discharge generated between the scan electrode (Y) and the sustain electrode (X) in the reset period is reduced to improve the contrast of the PDP.

6 is a view showing a driving waveform of the plasma display panel according to the second embodiment of the present invention.

As shown in Fig. 6, in the driving waveform of the second embodiment of the present invention, when the voltage applied to the scan electrode Y is dropped in the falling period of the reset period, the voltage applied to the scan electrode Y is 0 (V). At this point, the voltage applied to the scan electrode Y is lowered to Vnf, which is a negative voltage level more gently. At this time, the voltage applied to the sustain electrode X is equal to the falling voltage slope applied to the scan electrode Y, and the voltage Ve- | Vnf | Apply a continuously falling voltage until In other periods, the description is the same as in the first embodiment of the present invention. Also, the driving waveforms as in the second embodiment of the present invention can achieve the same effects as those in the first embodiment of the present invention. Further, in the second embodiment of the present invention, since there is a section that is more gentle, it is possible to evenly accumulate the wall charges.

 7 is a diagram illustrating a detailed circuit diagram of the sustain driver 320 and the scan driver 340 according to the first embodiment of the present invention.

According to the scan driver 320 according to the first embodiment of the present invention, the transistors M1 and M2 are connected in series between the sustain voltage Vs and the ground voltage, and the contacts between the transistors M1 and M2 are connected. And the first terminal (i.e., scan electrode Y) of the panel capacitor Cp (where the panel capacitor is an equivalent representation of the capacitance component between the sustain electrode X and the scan electrode Y). Transistor M3 is connected. The first terminal of the capacitor C1 is connected to the contact between the transistors M1 and M2, and the diode D1 is connected between the voltage Vset-Vs and the second terminal of the capacitor C1. A transistor M4 for applying a rising ramp voltage to the scan electrode Y is formed between the first terminal of the panel capacitor Cp and the capacitor C1, and is negatively connected to the first terminal of the panel capacitor Cp. Between the voltages Vnf, a transistor M5 for applying a ramp voltage that falls to the negative voltage Vnf to the scan electrode Y is formed. In the transistors M4 and M5, capacitors C2 and C3 are formed between the drain and the gate to supply a constant current between the source and the drain, respectively.

Meanwhile, according to the sustaining electrode X driving unit 340 according to the first embodiment of the present invention, the transistor M8 is formed between the voltage Ve and the second terminal (ie, the X electrode) of the panel capacitor Cp. The transistor M7 is formed between the second terminal of the panel capacitor Cp and the ground. The transistor M8 floats between the second terminal of the panel capacitor Cp and the Ve voltage to make a high impedance state, thereby applying a falling voltage to the sustain electrode X in the falling section of the reset section as described with reference to FIG. 5. It plays a role.

Between the voltage Ve and the second terminal of the panel capacitor Cp, a transistor M6 for applying an erase waveform to the sustain electrode X is formed. A capacitor C4 is formed between the drain and the gate of the transistor M6 to allow a constant current to flow between the source and the drain.

Next, the driving method in the reset period of the driving method according to the first embodiment of the present invention will be described in more detail with reference to FIGS. 5 and 8.

First, it is assumed that the voltage Vset-Vs is charged in the capacitor C1. This charging of the voltage can be easily performed by turning on the transistor M2.

The erase period is implemented by turning on the transistor M6 with the transistors M2 and M3 turned on. Then, since the constant current is supplied to the second terminal (holding electrode X) of the panel capacitor Cp, the erase lamp voltage rising from the ground voltage to the voltage Ve is applied to the sustaining electrode X as shown in FIG. do.

In the rising period of the reset period, the transistors M2 and M3 are turned off and the transistors M1 and M4 are turned on while the transistor M7 is turned on. Then, since the voltage Vs is supplied to the first terminal of the capacitor C1 and the voltage Vset-Vs is charged in advance to the capacitor C1, the voltage of the second terminal of the capacitor C1 is set to Vset. do. The voltage of the voltage Vset of the second terminal of the capacitor C1 is supplied to the first terminal (scan electrode Y) of the panel capacitor Cp through the transistor M4. At this time, since the constant current flows between the source and the drain due to the influence of the capacitor C2, the transistor M4 rises from the voltage Vs to the voltage Vset at the first terminal (scan electrode Y) of the capacitor Cp. Voltage is applied. At this time, since the transistor M7 is turned on, the second terminal (the sustain electrode X) of the panel capacitor Cp is maintained with O (V).

Next, when the first terminal (scan electrode Y) of the panel capacitor Cp rises to the voltage Vset, the transistors M3 and M8 are turned on and the transistor M1 remains turned on as it is. Then, the first terminal (scanning electrode Y) of the panel capacitor Cp becomes the voltage Vs and the second terminal (holding electrode X) of the panel capacitor Cp turns on the transistor M8 to turn on the voltage Ve. It becomes a state.

The falling section of the reset period turns off the transistor M1 and turns on the transistor M5 while the transistor M3 is turned on. The transistor M8 maintains a turn on state. Then, the voltage at the first terminal (scanning electrode Y) of the panel capacitor Cp drops to the voltage Vnf from the voltage Vs to the negative voltage level.

At this time, during the period in which the voltage of the first terminal (scan electrode Y) of the panel capacitor falls from the voltage Vs to the negative voltage level Vnf, the voltage of the scan electrode Y is 0 (V) in FIG. The transistor M8 is turned off. Then, since the second terminal (holding electrode X) of the panel capacitor Cp held at the voltage Ve is in a floating state, the voltage of the second terminal (holding electrode X) of the panel capacitor Cp is floated. (Hereinafter referred to as 'floating voltage') is changed in correspondence with the voltage of the first terminal (scanning electrode Y) of the panel capacitor Cp as shown in FIG. That is, since the voltage of the second terminal (sustaining electrode X) of the panel capacitor Cp corresponds to a value obtained by subtracting the voltage charged in the panel capacitor Cp from the voltage of the scan electrode Y, the sustain electrode X The voltage of the electrode corresponds to the voltage of the scan electrode Y and the voltage Ve- | Vnf | Will descend. In Fig. 5, the specific time point for turning off the transistor M8 is defined as the time point at which the voltage of the scan electrode Y becomes 0 (V). It may be a point.

9 is a diagram illustrating a detailed circuit diagram of the sustain driver 320 and the scan driver 340 according to the second embodiment of the present invention.

As shown in FIG. 9, a detailed circuit diagram of the holding and scanning driver according to the second embodiment of the present invention is similar to FIG. However, the transistor M5 is not connected to the voltage Vnf, but is connected to the ground point, and further includes a transistor M9 connected between the contacts of the transistors M1 and M2 and the negative voltage Vnf. In addition, a capacitor C4 for supplying a constant current is connected between the gate and the drain of the transistor M9, and the value of the capacitor C4 is larger than that of the capacitor C3. Since the capacitor C4 has a larger capacity than the capacitor C3, the ramp lowered by the transistor M9 is more gently implemented as shown in FIG.

The driving method of the reset period in the driving method of the second embodiment of the present invention through this is similar to the first embodiment of the present invention. Some of the falling sections of the reset period turn off the transistor M1 and turn on the transistor M5 while the transistor M3 is turned on. As a result, the voltage applied to the first terminal (scan electrode Y) of the panel capacitor drops from the voltage Vs to the ground voltage. At this time, when the voltage applied to the panel capacitor first terminal (scanning electrode Y) becomes the ground voltage, a part of the falling section of the reset period turns off the transistor M8 and at the same time turns on the transistor M5. Off and turn on transistor M9. As a result, the voltage applied to the first terminal (scanning electrode Y) of the panel capacitor drops from the voltage 0 (V) to the negative voltage Vnf, and the falling slope is maintained more smoothly. In addition, the voltage applied to the second terminal (holding electrode X) of the panel capacitor changes in response to the voltage of the first terminal (scanning electrode Y) of the panel capacitor due to the turn-off of the transistor M8. Therefore, the voltage applied to the sustain electrode X is changed from the voltage Ve to Ve- | Vnf | It will descend even more slowly. The driving method in other sections is the same as that of the first embodiment of the present invention, and detailed description thereof will be omitted.

As described above, according to the reset driving method of the first and second embodiments of the present invention, the sustain electrode X and the scan electrode Y are floated by floating the sustain electrode X at some point in the falling section of the reset period. Since there is no variation in the voltage difference applied therebetween, the loss of the negative wall charges present in the scan electrode Y can be prevented. As a result, the addressing operation becomes a more favorable state of wall charge, and the contrast of the plasma display panel can be improved.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, the sustain electrode is floated at a specific point in the falling section of the reset section so that the voltage difference between the sustain electrode and the scan electrode does not change, thereby preventing the loss of negative wall charges formed in the scan electrode. have. This results in a more favorable state of wall charge in the addressing operation. In addition, since the discharge between the sustain electrode and the scan electrode does not occur after a specific point in the reset period, the contrast of the plasma display panel can be increased.

1 is a partial perspective view of a plasma display panel.

2 is an arrangement diagram of electrodes of a plasma display panel.

3 is a driving waveform diagram of a conventional plasma display panel.

4 is a diagram illustrating a plasma display panel according to an exemplary embodiment of the present invention.

5 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

6 is a driving waveform diagram of a plasma display panel according to a second embodiment of the present invention.

7 illustrates a wall charge state (a) according to a conventional driving method and a wall charge state (b) according to a first embodiment of the present invention.

FIG. 8 is a diagram illustrating an example of a circuit diagram used to apply the driving waveform shown in FIG. 5.

FIG. 9 is a diagram illustrating an example of a circuit diagram used to apply the drive waveform shown in FIG. 6.

Claims (11)

A method of driving a plasma display panel comprising a first electrode, a second electrode, and a panel capacitor formed between the first electrode and the second electrode. In the reset period, (a) applying a first voltage waveform gradually decreasing from a first voltage to a second voltage to the first electrode during the first period; And (b) applying a second voltage waveform gradually decreasing from a third voltage to a fourth voltage to the second electrode in a second section, which is a partial section of the first section. . The method of claim 1,  And driving the second electrode in the second section to apply the second voltage waveform to the second electrode. The method according to claim 1 or 2, And applying a voltage gradually rising from a fifth voltage to a sixth voltage to the first electrode before the first period. The method of claim 2, And a time point at which the second electrode is floated is a time point at which a voltage applied to the first electrode passes a ground voltage. The method according to claim 1 or 2, And the second voltage is a negative voltage level. The method according to claim 1 or 2, And a method of applying the third voltage to the second electrode during the first period. The method according to claim 1 or 2, And the first voltage waveform has a section having a different slope. An apparatus for driving a plasma display panel comprising a first electrode, a second electrode, and a panel capacitor formed between the first electrode and the second electrode. A first voltage waveform electrically connected between the first electrode and a first power supply for supplying a first voltage, the first voltage waveform being turned on during a first period of a reset period and gradually decreasing to the first voltage to the first electrode; A first switch; And Electrically connected between the second electrode and a second power supply for supplying a second voltage, and turned on in a second section, which is a section of the first section, to apply the second voltage to the first electrode; And a second switch that is turned off in a third section continuous to the second section of the first section to float the second electrode. The method of claim 8, A third switch electrically connected between the first electrode and a third power supply for supplying a third voltage, the third switch being turned on before the first period to apply a second voltage waveform gradually rising to the second electrode; Driving device for a plasma display panel comprising. The method according to claim 8 or 9, And the first voltage is a negative voltage. An apparatus for driving a plasma display panel comprising a first electrode, a second electrode, and a panel capacitor formed between the first electrode and the second electrode. A first voltage waveform electrically connected between the first electrode and a first power supply for supplying a first voltage, the first voltage waveform being turned on during a first period of a reset period and gradually decreasing to the first voltage to the first electrode; A first switch; An electrical connection between the first electrode and a second power supply for supplying a second voltage lower than the first voltage, the electrode being turned on for a second period of the reset period and gradually decreasing to the second voltage at the first electrode; A second switch for applying a second voltage waveform; And An electrical connection between the second electrode and a third power supply for supplying a third voltage, the second electrode being turned on in a third section, which is a section of a sum of the first section and the second section, and the second electrode; And a third switch configured to apply three voltages and to be turned off in a fourth section, the fourth section being a portion of the sum of the first section and the second section to float the second electrode.