KR100536492B1 - Flash memory having page-buffer for shared latch - Google Patents

Abstract

By having two page-buffers in which the latches are shared, a flash memory is disclosed that reduces the overall write time and internal data movement time. The flash memory controller for controlling the read / write / erase operation of the flash memory; Two memory cell arrays for storing data; A Y-buffer latch and decoder for controlling a bit line of a memory cell array to read / write data in accordance with a control and address signal of the controller; Two X-buffer latches and decoders controlling word lines of a memory cell array to read / write data in accordance with control and address signals of the controller; Two page-buffers, each connected to the two memory cell arrays, for reading / writing data to the two memory cell arrays; And receiving data from an I / O buffer and a latch and transferring the data to the page-buffer or outputting data of a page-buffer detected from a selected memory cell to the I / O buffer and the latch according to an output signal of the controller. Y-gating circuits.

Description

Flash memory having page-buffer for shared latch

The present invention relates to nonvolatile memory and, more particularly, to a flash memory having two page-buffers in which latches are shared.

Flash memory that writes and erases data using tunneling is not only a nonvolatile memory having excellent data retention, but also has a low power consumption and strong external shock compared to a hard disk. In the flash memory, a process of reading data stored in a flash memory cell includes reading a data stored in a flash memory cell and storing the data stored in an internal register and a data stored in the internal register. The second step of outputting out of the flash memory chip (memory chip). In addition, a process of programming data in a flash memory cell may include a first step of inputting write data into a flash memory and storing the data in an internal register, and then moving the data stored in the internal register back to the flash memory cell. As a result, a second step of preserving data even when the power supply to the memory chip is cut off.

In the case of flash memory, the time to read data is very fast (1 byte read time = tens [ns] to number [us]), while the time to write data is very slow (1 byte program time = tens [ us] to hundreds [us]). To compensate for this drawback, a method of improving the overall read / write time by reading and writing data in units of pages, that is, reading and writing data in units of hundreds to hundreds of bytes at a time. Is being used. Therefore, in order to further improve read / write time, a larger page unit should be used. However, when the unit of the page becomes larger, when storing data in the flash memory cell, the time of the second step of moving the data stored in the internal register to the flash memory cell is shortened, but the time of the first step of storing the data in the internal register is shortened. As it increases, there is a limit to the improvement of the overall recording time.

In addition, due to the physical characteristics of the flash memory, when data is programmed / erased more than tens of thousands of times, an error-bit cell that can no longer be recorded / deleted occurs. Data of a block in which the same error-bit cell has occurred should be replaced with another block. Therefore, in a flash memory, a function of reading data of a block including an error-bit cell and writing to a block not containing an error-bit cell is required. Even in this case, if the page size is large, a large amount of time is required in the second step of reading data and the first step of writing data, so that the read / write speed of the memory chip cannot be sufficiently improved. have.

Accordingly, an object of the present invention is to improve the overall write time by performing a second step of storing data in a flash memory cell and a first step of storing write data in an internal register in a programming process. To provide a flash memory.

Another object of the present invention is to register a page-buffer register by means of a Y-gating circuit in order to move the block to another block simply and quickly in case of an error-bit cell during use of the memory. It provides flash memory for sharing with each other.

Another object of the present invention is to provide a flash memory which minimizes the size increase of a flash memory chip by realizing the above object by using one controller and one high voltage generator.

In order to achieve the above object, the present invention provides a controller for controlling a read / write / erase operation of a flash memory; Two memory cell arrays for storing data; A Y-buffer latch and decoder for controlling a bit line of a memory cell array to read / write data in accordance with a control and address signal of the controller; Two X-buffer latches and decoders controlling word lines of a memory cell array to read / write data in accordance with control and address signals of the controller; Two page-buffers, each connected to the two memory cell arrays, for reading / writing data to the two memory cell arrays; Y that receives data from an I / O buffer and a latch and transfers the data to the page-buffer or outputs data of a page-buffer detected from a selected memory cell to the I / O buffer and the latch according to the output signal of the controller. Provide a flash memory including a gating circuit.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a block diagram showing the overall configuration of a NAND flash memory according to an embodiment of the present invention. In FIG. 1, the number of memory cells is 2 ¹⁰ (A0 to A11), and the number of memory blocks is 2 ¹⁴ ( A12 ~ A27) The case of the personal flash memory is shown. As shown in FIG. 1, the flash memory according to the present invention includes a controller 120, Y-buffer latches and decoders 130, two X-buffer latches and decoders 111 and 112, and Y-. Gating circuit 160, two page-buffers 151 and 152, two memory cell arrays 181 and 182, and I / O buffers and latches 190, If necessary, global buffers 140 may be further included.

The controller 120 controls other components of the flash memory according to a read / write / erase command, and includes a command register and a flash to store a flash memory control command. A high voltage generator for generating a high voltage necessary for reading, writing, erasing, etc. of a memory, and a flash memory for indicating a high voltage generated by the high voltage generator in the command register. In order to apply to the location, it may include a power switch state machine (PSSM) for controlling the power. The Y-buffer latch and decoder 130 is a bit line (B / L) of the memory cell arrays 181 and 182 to read / write data according to the control and address signals A0 to A11 of the controller 120. bit-line, and the two X-buffer latches and decoders 111 and 112 read / write data according to the control and address signals A12 to A27 of the controller 120. In order to control the word line (W / L) of the memory cell array (181, 182). The Y-gating circuit 160 writes an I / O buffer and a latch 190 to write data to a memory cell selected by the Y-buffer latch and the decoder 130 according to an output signal of the controller 120. Receives data from the page buffers 151 and 152 or transfers the data of the page buffers 151 and 152 detected from the selected memory cells 181 and 182 to the I / O buffer and the latch 190. Function as a mux-circuit. The Y-gating circuit 160 also shares the latches of the two page-buffers 151 and 152 internally for internal data replacement.

The two page-buffers 151 and 152 are to read / write data to / from the two memory cell arrays 181 and 182 and are connected to each other by one Y-gating circuit 160. Each memory cell array and its corresponding page-buffers 181, 151, 182, and 152 are distinguished by addresses given from outside (addresses A0 to A11 and A12 to A27). In addition, the I / O buffer and the latch 190 are for inputting and outputting the data, and function to interconnect data of the global buffer 140 and the Y-gating circuit 160. The global buffer 140 is used to collectively input and output data input / output, address signals A0 to A11, A12 to A27, and various commands, and may be used as necessary. As shown in FIG. 1, the flash memory chip according to the present invention uses two controllers 181 and 182 and two pages using one controller 120 and a Y-buffer latch and decoder 130. -Drive the buffers (151, 152).

2 is a block diagram illustrating an example of the page-buffers 151 and 152 used in the flash memory according to the present invention. As shown in FIG. 2, in the flash memory according to an embodiment of the present invention, two identical page-buffers 151 and 152 are interconnected by one Y-gating circuit 160. Each of the first and second page-buffers 151, 152 transmits a bias to the first and second memory cell arrays 181, 182, respectively. ), First and second sensing means 213 and 223 for data sensing, and first and second latches 214 for latching sensed data and program data. 224). The first and second latches 214, 224 may be interconnected to exchange data through one or more switches controlled by the controller 120, preferably in the Y-gating circuit 160. May be interconnected. For example, one or more switches connecting the first and second latches 214 and 224 may include data in each page-buffer 151 in the Y-gating circuit 160, as shown in FIG. 152 may be used.

3 is a diagram illustrating a process of reading data stored in the memory cell array 181 by the page buffer 151 in the flash memory according to the present invention, and FIG. 4 shows the page buffer 151 as a memory. A timing diagram of a process of reading data of the cell array 181 is shown. As shown in FIG. 3, a command to perform a read operation from the command register of the controller 120 and any bit, even or odd, from the Y-buffer latch and decoder 130. When a command to read a bit-line is transmitted, an operation for reading data stored in the flash memory cell 181 is performed. To read the data stored in the flash memory cell 181, (i) transistors M102 (hereinafter simply referred to as "M102") and M104 are turned off, and M101 and M103 are turned on to turn on the bit-line ( BLue & BLuo) is initialized using BLPWR. Then, BLuo turns off M104 and M103 on during the read operation to maintain the initialization state using BLPWR (first step, indicated by "1" in FIG. 4). ). (ii) M101 is turned off and M105, M102 are turned on to pre-charge the bit-line (BLue) to Vdd. At this time, the bias level pre-charged in the bit-line BLue is adjusted to the bias level of BLSHFue. Then, M106 is turned on to initialize the latch 214 (second step, indicated by "2" in FIG. 4). (iii) M102 and M106 are turned off and wait until the bias pre-charged in the bit-line BLue is discharged through the flash memory cell 181. At this time, if the flash memory cell 181 is erased, all of the biases pre-charged in the bit-line BLue are discharged through the flash memory cell 181, and the flash memory cell 181 is written. When programmed, the bias pre-charged in the bit-line BLue is not discharged through the flash memory cell 181 and remains as it is (third step, indicated by "3" in FIG. 4). (iv) M105 is turned off and M102 is turned on to charge share the charge at the gate of bit-line (BLue) and M107. At this time, the charge sharing amount is adjusted to the bias level of BLSHFue (fourth step, indicated by "4" in FIG. 4) (v) M108 is turned on to perform a sensing operation. At this time, if the flash memory cell 181 is erased, all of the biases pre-charged in the bit-line BLue are discharged through the flash memory cell 181, and thus 0 [0] is applied to the gate of M107. v] is applied and the latch 214 value is kept at its initial value, and if the flash memory cell 181 is programmed, the bias pre-charged in the bit-line BLue is flash memory cell 181. The Vcc value is applied to the gate of M107 so that the latch 214 value is inverted (indicated by " 5 " in FIG. 4). As described above, according to a read command given from the outside, the data of the flash memory cell 181 is read, stored in a register, and then all biases applied to the page buffer 151 are initialized (sixth step). 4, when the output signal is input from the outside, the standby state is maintained in order to output the data of the register in a short time (seventh step, indicated by "7" in FIG. 4).

5 is a diagram illustrating a process in which the page buffer 151 writes data to the memory cell array 181 in the flash memory according to the present invention, and FIG. A timing diagram of a process of writing data to the cell array 181. As shown in FIG. 5, the data to be programmed from the outside is stored in the page-buffer 151, the stored data is again stored in the memory cell 181, and the page-buffer 151 is stored. Test the results. A command to perform a write operation from the command register of the controller 120 and a command to write any bit-line, even or odd, from the Y-buffer latch and decoder 130 are provided. When transferred, a write operation to store data in flash memory cell 181 is performed. First, (i) the control signal output from the command register of the controller 120 turns off M102, M104, M106, M109, M110, and M113, turns on M105 and M108 to latch 214. Is initialized ("0"), and then M105 and M108 are turned off (indicated by "1" in the first step, FIGS. 5 and 6). (ii) The write data input from the outside is controlled by the Y-buffer latch and decoder 130 and stored in the latch 214 through M301, M302, and M112. At this time, if the write data value input from the outside is "0", the value "1" is held in the latch 214, and if the write data value input from the outside is "1", the value "0" is held in the latch 214. (Indicated by "2" in the second step, Figures 5 and 6). (iii) M101 is turned off, and M102 and M109 are turned on to transfer the value ("0" or "1") stored in the latch 214 to the bit-line BLue. Then, the unselected bit-line BLuo is initialized using BLPWR by turning on M103 (indicated by "5" in the third step, FIGS. 5 and 6). (iv) After a certain period of time, a reading operation (Sensing) of the page-buffer 151 is performed to test whether the writing is successful at once through M111. (v) If the recording was successful, the data recording program ends, and if it fails, the process returns to the above step (iii) to repeat the data recording. In FIG. 6, steps "3" and "4" are steps for generating high voltages necessary for recording data, and steps "6" and "7" are pass / fail for all data. ), The program bias is again applied only to the data that failed to be recorded.

FIG. 7 is a diagram illustrating a process in which page-buffers 151 and 152 perform an internal data replacement operation in a flash memory according to the present invention. FIG. A timing diagram of a process of performing a move. If an error-bit cell that can no longer be written / deleted occurs during writing / deleting / reading in the flash memory cells 181 and 182, as shown in FIG. 7, the page buffers 151 and 152 have an error- The data of the block in which the bit cell is generated is read and replaced with another block. (i) The page-buffer 151 reads the flash memory cell 181 data by receiving a read command for the internal data movement operation from the command register of the controller 120. The data read in this way is stored in the page-buffer 151 and is not output to the flash memory chip, but is moved to another block by receiving a write command for moving the internal data. (ii) The second latch 224 is initialized by turning on M206, and then turned off. All others are turned off. (iii) M113, M302, M303, and M212 are turned on to store the value inverted from the first latch 214 to the second latch 224 (to " 7 " in FIG. 7). Display). Turn off M113 and M212. (iv) M106 is turned on to initialize the value of the first latch 214. Turn M106 off. (v) M213, M302, M303, and M110 are turned on to transfer the value of the second latch 224 to the gate of M107. Next, M108 is turned on to store the value of the second latch 224 equally in the first latch 214. M213, M302, M303, and M110 are turned off. (vi) Receive a write command for the internal data movement operation from the command register of the controller 120, perform a data write operation to move the data of the first or second latch 224 to another block. By thus allowing the latch values of the page-buffers to be shared with each other, that is, by allowing the latch values of one page-buffer to be transferred to the latch values of the other page-buffer, the speed of data movement in the flash memory can be significantly increased. .

9 is a diagram illustrating a process of performing a double speed program operation by a page buffer in a flash memory according to the present invention, and FIG. 10 is a diagram illustrating a process of performing a double speed write by a page buffer. Timing diagram. (i) A command for double speed write operation is received from the command register of the controller 120 to perform double speed write. (ii) The write data input from the outside is controlled by the Y-buffer latch and the decoder 130 and stored in the first or second latch 214 or 224. At this time, the recording data storage and recording method (program flow, 1U, 2U, 3U, and 1D, 2D, and 3D of FIG. 10) made are the same as those of the data recording operation (programs 1, 2, and 3 of FIG. 6). Do. (iii) If the first page-buffer 151 is performing the write operation, since the second page-buffer 152 does not perform the write operation, the second page-buffer 152 does not have data to be externally recorded. Save the file and record it. At this time, first, a write operation of the first page buffer 151 performing the write operation (4, 5, 6, 7 in the upper part of FIG. 10) and the second page buffer 152 to perform the new write operation (Fig. 10, 4, 5, 6, and 7 at the bottom do not coincide with each other, so the first page- starts recording of the second page-buffer 152, which is started late by the power switch state machine (PSSM). Synchronize with the start of recording of the buffer 151. (iv) Since one page-buffer 151 has performed the write operation first, the writing is completed before the other page-buffer 152. At this time, the second page-buffer 152 performs the recording operation, but since the first page-buffer 151 has completed the recording operation, the second page-buffer 151 stores the data to be externally recorded in the page-buffer 151 before recording. Run again. (v) Repeat the above operation. As described above, in the flash memory according to the present invention, the two page-buffers read / write data separately with a predetermined time difference, thereby increasing the read / write speed of the data.

FIG. 11 is a diagram illustrating a reduction in writing time when the page-buffers 151 and 152 perform a double speed write operation in the flash memory according to the present invention. The case where the buffers 151 and 152 are used is shown, and the lower figure of FIG. 11 shows the case where one page-buffer is used. From Fig. 11, it can be seen that when using the flash memory of the present invention (top view in Fig. 11) than the conventional programming (program in the bottom view in Fig. 11), the writing speed is doubled. 12 is a view showing a time required when the page-buffers 151 and 152 perform internal data movement in the flash memory according to the present invention. In the case of replacing data by the conventional method from FIG. 12, since additional time is required for reading and loading data, data movement is performed by performing internal data movement using the flash memory of the present invention. It can be seen that the speed is about 2 times improved. Although the present invention has been described only in the case of two memory cell arrays, the same concept as described above may be applied to the case of three or more memory cell arrays.

As described above, the flash memory cell according to the present invention not only solves the problems caused by the slow writing speed of a conventional flash memory cell through a circuit configuration change, but also enables a faster writing speed and internal data movement. In this case, the performance of the flash memory is greatly improved.

1 is a block diagram showing the overall configuration of a flash memory according to an embodiment of the present invention.

2 is a block diagram showing an example of a page-buffer used in a flash memory according to the present invention;

3 is a view for explaining a process in which a page buffer reads data stored in a memory cell array in a flash memory according to the present invention;

4 is a timing diagram of a data reading process shown in FIG. 3;

FIG. 5 is a view for explaining a process in which a page buffer writes data to a memory cell array in a flash memory according to the present invention; FIG.

FIG. 6 is a timing diagram of a data writing process shown in FIG. 5; FIG.

7 is a view for explaining a process of performing a page-buffer internal data movement operation in the flash memory according to the present invention.

8 is a timing diagram of an internal data movement process shown in FIG.

9 is a view for explaining a process of performing a double-speed write operation by a page-buffer in a flash memory according to the present invention.

FIG. 10 is a timing diagram of the double speed recording process shown in FIG.

Fig. 11 is a diagram showing a reduction in writing time when a page-buffer performs a double speed write operation in the flash memory according to the present invention.

12 illustrates a time required when a page-buffer performs internal data movement in a flash memory according to the present invention.

Claims (6)

A controller for controlling read / write / erase operations of the flash memory; Two memory cell arrays for storing data; A Y-buffer latch and decoder for controlling a bit line of a memory cell array to read / write data in accordance with a control and address signal of the controller; Two X-buffer latches and decoders controlling word lines of a memory cell array to read / write data in accordance with control and address signals of the controller; Two page-buffers, each connected to the two memory cell arrays, for reading / writing data to the two memory cell arrays; And Y that receives data from an I / O buffer and a latch and transfers the data to the page-buffer or outputs data of a page-buffer detected from a selected memory cell to the I / O buffer and the latch according to the output signal of the controller. A flash memory comprising a gating circuit. 2. The flash memory of claim 1, wherein the memory cell array and corresponding page-buffer are selected by an address given from the outside. The flash memory of claim 1, wherein the controller includes a command register, a power switch state controller (PSSM), and a high voltage generator. 2. The flash of claim 1 wherein the page-buffer comprises a bias means for delivering a bias to a memory cell array, a sensing means for data sensing, and a latch for latching sensed data and write data. Memory. The flash memory of claim 1, wherein the latch value of one page-buffer is transferred to the latch value of another page-buffer. The flash memory of claim 1, wherein the two page-buffers read / write data separately with a predetermined time difference.