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KR100545208B1 - Semiconductor device manufacturing apparatus and manufacturing method - Google Patents

Semiconductor device manufacturing apparatus and manufacturing method Download PDF

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KR100545208B1
KR100545208B1 KR1020030068852A KR20030068852A KR100545208B1 KR 100545208 B1 KR100545208 B1 KR 100545208B1 KR 1020030068852 A KR1020030068852 A KR 1020030068852A KR 20030068852 A KR20030068852 A KR 20030068852A KR 100545208 B1 KR100545208 B1 KR 100545208B1
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wafer
semiconductor device
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reticle
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KR20050032871A (en
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김상원
이용석
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동부아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/682—Mask-wafer alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

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  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

본 발명은 레티클의 오적용 및 노광량의 오설정을 용이하게 확인할 수 있는 반도체 소자 제조장치 및 제조 방법에 관한 것으로, 본 발명의 반도체 소자 제조 방법은, 반도체 소자를 제조하기 위한 사진 공정에 있어서, 웨이퍼 에지 노광 공정에서 노광을 진행하는 동안 웨이퍼에 패터닝된 레티클 아이디(ID)를 판독함과 아울러, 노광량 오설정에 의해 형성된 비정상적인 이미지를 판독함으로써, 레티클 오적용 및 노광량 오설정으로 인한 문제점을 제거한 반도체 소자 제조장치 및 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device manufacturing apparatus and a manufacturing method capable of easily confirming misapplication of a reticle and incorrect setting of an exposure amount. The semiconductor device manufacturing method of the present invention provides a wafer in a photographic process for manufacturing a semiconductor device. The semiconductor device eliminates problems caused by reticle misapplication and exposure dose misalignment by reading a patterned reticle ID (ID) on the wafer during exposure in the edge exposure process and by reading an abnormal image formed by exposure dose misconfiguration. A manufacturing apparatus and a manufacturing method are related.

현상, 사진, 검사, 노광량, 레티클 Development, photography, inspection, exposure dose, reticle

Description

반도체 소자 제조장치 및 제조 방법{APPARATUS AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}Semiconductor device manufacturing apparatus and manufacturing method {APPARATUS AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

도 1은 종래 기술에 따른 반도체 소자 제조 방법을 나타내는 블록도이고,1 is a block diagram showing a method of manufacturing a semiconductor device according to the prior art,

도 2는 본 발명의 실시예에 따른 반도체 소자 제조 방법을 나타내는 블록도이며,2 is a block diagram illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 3은 본 발명의 실시예에 따른 반도체 소자 제조장치를 나타내는 개략 구성도이고,3 is a schematic block diagram showing a semiconductor device manufacturing apparatus according to an embodiment of the present invention,

도 4a 내지 4c는 노광량에 따라 가변하는 이미지를 나타내는 평면도이다.4A to 4C are plan views showing images which vary according to the exposure amount.

본 발명은 반도체 소자 제조장치 및 제조 방법에 관한 것으로, 보다 상세하게는 반도체 소자에 특정 패턴을 형성하는 사진 공정에 있어서, 레티클의 오적용 및 노광량의 오설정을 용이하게 확인할 수 있는 반도체 소자 제조장치 및 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing apparatus and a manufacturing method, and more particularly, to a semiconductor device manufacturing apparatus which can easily confirm misapplication of a reticle and incorrect setting of an exposure amount in a photographic process of forming a specific pattern on a semiconductor device. And to a manufacturing method.

일반적으로, 반도체 제품을 생산하기 위해서는 매우 정밀한 반도체 제조 공정은 물론, 반도체 제조 공정을 수행하는 반도체 제조 설비를 필요로 한다.In general, the production of semiconductor products requires a highly precise semiconductor manufacturing process, as well as a semiconductor manufacturing equipment that performs the semiconductor manufacturing process.

상기 반도체 제조 설비는 크게 선행 반도체 제조 설비와 후속 반도체 제조 설비로 구분할 수 있는 바, 선행 반도체 제조 설비는 순수 실리콘 웨이퍼에 반도체 박막 패턴을 형성하기 위한 선행 공정인 사진 공정(photolithography)을 수행하고, 후속 반도체 제조 설비는 웨이퍼에 패터닝된 포토레지스트 박막을 매개로 웨이퍼에 소정의 특성을 갖는 불순물을 주입하는 이온 주입 공정, 이미 형성된 반도체 박막을 식각하여 패터닝하는 식각 공정, 웨이퍼에 소정 박막을 부가하는 증착 공정, 미세 박막 회로 패턴을 연결하는 메탈 공정 등을 수행한다.The semiconductor manufacturing equipment can be largely classified into a preceding semiconductor manufacturing equipment and a subsequent semiconductor manufacturing equipment. The preceding semiconductor manufacturing equipment performs a photolithography process, which is a preliminary process for forming a semiconductor thin film pattern on a pure silicon wafer. The semiconductor manufacturing equipment includes an ion implantation process for injecting impurities having predetermined characteristics into the wafer through a photoresist thin film patterned on the wafer, an etching process for etching and patterning a previously formed semiconductor thin film, and a deposition process for adding a predetermined thin film to the wafer And a metal process for connecting the fine thin film circuit pattern.

이 중에서, 종래의 사진 공정은 도 1에 도시한 바와 같이, 포토레지스트(PR: Photoresist) 도포 단계→베이크(bake) 단계→냉각(chill) 단계→웨이퍼 에지 노광(wafer edge exposure) 단계→노광(exposure) 단계→노광후 베이크(post exposure bake) 단계→현상(develope) 단계→베이크(bake) 단계→오버레이(overlay) 검사 단계→임계치수(critical dimension) 검사 단계→검사(inspection) 단계를 포함하여 이루어진다.Among these, the conventional photolithography process is performed by applying a photoresist (PR) step → bake step → chill step → wafer edge exposure step → exposure (as shown in FIG. 1). including the exposure stage → post exposure bake stage → developer stage → bak stage → overlay inspection stage → critical dimension inspection stage → inspection stage. Is done.

그런데, 상기한 종래의 사진 공정에 의하면, 노광 단계에서 노광을 진행할 때 레티클 오적용에 따른 품질 사고가 빈번하게 발생하고, 레티클 오적용를 검사하기 위해서는 별도의 검사 장비를 이용해야 하며, 상기한 검사 장비를 이용하더라도 레티클 오적용 여부를 발견하는 것이 용이하지 않다.By the way, according to the conventional photographic process, when the exposure is performed in the exposure step, quality accidents frequently occur due to the misapplication of the reticle, and in order to inspect the misapplication of the reticle, separate inspection equipment should be used, and the inspection equipment described above. It is not easy to detect whether or not the reticle is misapplied.

따라서, 레티클 오적용이 추후에 발견된 경우에는 이미 진행된 로트(lot) 전체를 감광액 제거 공정을 거쳐야 한다.Therefore, if a reticle misapplication is found later, the entire lot that has already been processed must go through a photoresist removal process.

또한, 임계치수 검사 공정을 거치지 않는 레이어, 예를 들어 N-웰, P-웰 형 성을 위한 마스크 공정들은 노광량 오설정시 엄청난 손실을 초래하게 되며, 상기한 노광량 오설정은 최종 검사 단계에서도 확인이 어려운 문제점이 있다.In addition, mask processes for forming layers that are not subjected to the critical dimension inspection process, for example, N-well and P-well formation, cause huge losses when the exposure dose is incorrectly set. There is this difficult problem.

이에 본 발명은 상기한 문제점을 해결하기 위한 것으로, 본 발명은 웨이퍼 에지 노광 공정에서 노광을 진행하는 동안 웨이퍼에 패터닝된 레티클 아이디(ID)를 판독함과 아울러, 노광량 오설정에 의해 형성된 비정상적인 이미지를 판독함으로써, 레티클 오적용 및 노광량 오설정으로 인한 문제점을 제거한 반도체 소자 제조장치 및 제조 방법을 제공함에 목적이 있다.Accordingly, the present invention is to solve the above problems, the present invention is to read the reticle ID (pattern) patterned on the wafer during the exposure in the wafer edge exposure process, and also to detect the abnormal image formed by the incorrect exposure dose setting It is an object of the present invention to provide a semiconductor device manufacturing apparatus and a manufacturing method which eliminates the problems caused by reticle misapplication and exposure amount missetting by reading.

상기한 목적을 달성하기 위하여 본 발명은,The present invention to achieve the above object,

반도체 소자를 제조하기 위한 사진 공정에 있어서,In the photographic process for manufacturing a semiconductor device,

(A) 웨이퍼의 표면에 포토레지스트를 도포하는 단계와;(A) applying a photoresist to the surface of the wafer;

(B) 웨이퍼의 에지를 노광하는 동안 상기 웨이퍼에 패터닝된 레티클 아이디, 또는 노광량에 따라 가변하는 이미지, 또는 상기 레티클 아이디 및 이미지를 판독하는 단계와;(B) reading the reticle ID patterned on the wafer, or the image varying according to the exposure dose, or the reticle ID and image while exposing the edge of the wafer;

(C) 상기 (B)단계에서의 판독 결과에 따라 추후 공정 진행 여부를 판단하는 단계;(C) determining whether to proceed with the process later according to the reading result in the step (B);

를 포함하는 반도체 소자 제조 방법을 제공한다.It provides a semiconductor device manufacturing method comprising a.

그리고, 상기 (B)단계를 수행하기 위한 반도체 소자 제조장치는,In addition, the semiconductor device manufacturing apparatus for performing the step (B),

웨이퍼 에지 노광장치로서,As a wafer edge exposure apparatus,

웨이퍼를 정렬하는 정렬부와;An alignment portion for aligning the wafer;

상기 웨이퍼에 빛을 입사시키는 조명부와;An illumination unit for injecting light into the wafer;

상기 웨이퍼의 특정 지역에 패터닝된 레티클 아이디, 또는 노광량에 따라 가변하는 이미지, 또는 상기 레티클 아이디 및 이미지를 판독하는 검사부;An inspection unit configured to read a reticle ID patterned on a specific region of the wafer or an image variable according to an exposure amount, or the reticle ID and image;

를 포함한다.It includes.

본 발명의 바람직한 실시예에 의하면, 상기 정렬부는 웨이퍼에 형성된 노치를 감지하여 웨이퍼를 정렬하는 노치 정렬용 엘이디(LED)로 이루어지고, 판독부는 고체 촬상 소자(CCD)로 이루어진다.According to a preferred embodiment of the present invention, the alignment unit is made of a notch alignment LED (LED) for aligning the wafer by sensing the notch formed on the wafer, the reading unit is a solid-state imaging device (CCD).

그리고, 상기 이미지는 저배율에서도 판독이 용이한 마름모꼴 형상으로 형성된다.The image is formed in a rhombus shape that is easy to read even at low magnification.

이하, 첨부도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 실시예에 따른 반도체 소자 제조 방법의 개략적인 구성을 나타내는 블록도를 도시한 것이다.2 is a block diagram showing a schematic configuration of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

본 실시예의 소자 제조 방법은 웨이퍼 에지 노광 단계에서 레티클 오적용 및/또는 노광량 오설정을 검사하고, 검사 결과에 따라 추후 공정의 진행 여부를 판단하는 것을 특징으로 한다.The device fabrication method of the present embodiment is characterized in that the reticle misapplication and / or exposure dose missetting is inspected in the wafer edge exposure step, and it is determined whether or not to proceed with the subsequent process according to the inspection result.

즉, 본 실시예의 소자 제조 방법은, PR(Photoresist) 도포 단계→베이크(bake) 단계→냉각(chill) 단계→웨이퍼 에지 노광(wafer edge exposure)→레티클 아이디 및/또는 이미지 판독 단계를 포함한다. 그리고, 도시하 지는 않았지만, 상기 판독 단계에서의 결과가 양호하다고 판단되면 추후 공정, 예를 들어 노광(exposure) 단계→노광후 베이크(post exposure bake) 단계→현상(develope) 단계→베이크(bake) 단계→오버레이(overlay) 검사 단계→임계치수(critical dimension) 검사 단계를 진행한다.That is, the device manufacturing method of this embodiment includes a photoresist coating step → bake step → chill step → wafer edge exposure → reticle ID and / or image reading step. Although not shown, if it is determined that the result in the reading step is good, a subsequent process, for example, an exposure step → a post exposure bake step → a development step → a bake Proceed with step → overlay inspection step → critical dimension inspection step.

그리고, 상기 판독 단계에서의 결과가 양호하지 않다고 판단되면, 레티클을 다른 종류의 것으로 적용하거나, 또는 노광량을 재설정한 후 다시 작업한다.If it is determined that the result in the reading step is not good, the reticle is applied to another kind, or the exposure amount is reset and the operation is performed again.

도 3은 본 실시예에 따른 반도체 소자 제조장치의 개략적인 구성도를 도시한 것이고, 도 4a 내지 4c는 웨이퍼에 패터닝되는 이미지의 형상을 도시한 것이다.3 illustrates a schematic configuration diagram of a semiconductor device manufacturing apparatus according to the present embodiment, and FIGS. 4A to 4C illustrate the shape of an image patterned on a wafer.

도 3에서, 미설명 도면부호 10는 웨이퍼 반송 로봇(12)을 구비하며 포토레지스트 도포 공정이 진행되는 트랙 유닛(track unit)을 나타내고, 도면부호 14는 베이크 유닛(bake unit)을 나타내며, 도면부호 16은 웨이퍼 에지 노광 유닛(wafer edge exposure unit)을 나타내고, 도면부호 18는 현상 유닛(develope)을 나타낸다.In FIG. 3, reference numeral 10 denotes a track unit having a wafer transfer robot 12 and a photoresist application process is performed, reference numeral 14 denotes a bake unit, and 16 denotes a wafer edge exposure unit, and 18 denotes a development unit.

이 중에서, 상기한 웨이퍼 에지 노광 유닛(16)에는 웨이퍼를 정렬하는 정렬부(16a)와, 상기 웨이퍼에 빛을 입사시키는 조명부(16b)와, 웨이퍼의 특정 지역에 패터닝된 레티클 아이디, 또는 웨이퍼의 스크라이브 라인에 패터닝되며 노광량에 따라 가변하는 이미지(20,20',20"), 또는 상기 레티클 아이디 및 이미지를 판독하는 검사부(16c)와, 웨이퍼 에지 노광용 광원(16d)가 구비된다.Among these, the wafer edge exposure unit 16 includes an alignment unit 16a for aligning the wafer, an illumination unit 16b for injecting light into the wafer, a reticle ID patterned in a specific area of the wafer, or a wafer. An image 20, 20 ′, 20 ″ patterned on a scribe line and varying according to the exposure amount, or an inspection unit 16c for reading the reticle ID and the image, and a light source 16d for wafer edge exposure are provided.

상기 정렬부(16a)는 웨이퍼에 형성된 노치를 감지하여 웨이퍼를 정렬하는 노치 정렬용 엘이디(LED)로 이루어질 수 있고, 판독부(16c)는 통상의 고체 촬상 소자(CCD)로 이루어질 수 있다.The alignment unit 16a may be formed of a notch alignment LED (LED) for aligning the wafers by sensing a notch formed in the wafer, and the reading unit 16c may be formed of a conventional solid-state imaging device (CCD).

그리고, 상기 이미지(20,20',20")를 형성하는 이미지 패턴은 저배율에서도 판독이 용이하며 레티클에 형성하기 쉬운 마름모꼴 형상으로 구성한다. 물론, 상기 이미지 패턴의 형상은 다양한 형상으로 변경할 수 있다.The image patterns forming the images 20, 20 'and 20 "are formed in a rhombus shape that is easy to read even at low magnification and easy to form on the reticle. Of course, the shape of the image pattern may be changed into various shapes. .

도 4a는 적정량으로 노광된 경우의 이미지(20)를 도시하고 있고, 도 4b는 과도한 양으로 노광된 경우의 이미지(20')를 도시하고 있으며, 도 4c는 부족한 양으로 노광된 경우의 이미지(20")를 도시하고 있다.FIG. 4A shows an image 20 when exposed to an appropriate amount, and FIG. 4B shows an image 20 'when exposed in an excessive amount, and FIG. 4C shows an image when exposed in an insufficient amount ( 20 ").

따라서, 상기한 이미지(20,20',20")의 판독 결과에 따라 노광량의 오설정 여부를 판독할 수 있으며, 상기한 이미지를 형성하기 위한 이미지 패턴은 웰 형성용 레티클에 적용하는 것이 바람직하다.Therefore, it is possible to read whether or not the exposure dose is set incorrectly according to the reading result of the above-described images 20, 20 'and 20 ", and it is preferable to apply the image pattern for forming the image to the well forming reticle. .

이상에서 설명한 바와 같이 본 발명은, 웨이퍼 에지를 노광하는 동안 레티클 아이디를 판독하여 레티클 오적용 여부를 검사하고, 또한 노광량을 측정할 수 있는 이미지를 판독하여 노광량의 오설정 여부를 검사한 후 추후 공정 진행 여부를 판단하게 되므로, 레티클 오적용으로 인한 로트 전체의 감광액 제거 공정을 실시할 필요가 없으며, 임계치수 검사 공정을 거치지 않는 웰 형성 공정에서 노광량 오설정으로 인한 손실을 방지할 수 있는 효과가 있다.As described above, according to the present invention, the reticle ID is read during the exposure of the wafer edge to check whether the reticle is misapplied, and the subsequent step is performed by reading the image capable of measuring the exposure dose to check whether the exposure amount is incorrectly set. Since it is determined whether or not to proceed, there is no need to perform the entire photoresist removal process due to misapplication of the reticle, and there is an effect that can prevent the loss due to incorrect exposure setting in the well forming process that does not go through the critical dimension inspection process. .

Claims (5)

반도체 소자를 제조하기 위한 사진 공정에 있어서,In the photographic process for manufacturing a semiconductor device, (A) 웨이퍼의 표면에 포토레지스트를 도포하는 단계와;(A) applying a photoresist to the surface of the wafer; (B) 웨이퍼의 에지를 노광하는 동안 상기 웨이퍼에 패터닝된 노광량에 따라 가변하는 이미지를 판독하는 단계와;(B) reading an image that varies with the amount of exposure patterned on the wafer while exposing the edge of the wafer; (C) 상기 (B)단계에서의 판독 결과에 따라 추후 공정 진행 여부를 판단하는 단계;(C) determining whether to proceed with the process later according to the reading result in the step (B); 를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a. 웨이퍼 에지 노광장치로서,As a wafer edge exposure apparatus, 웨이퍼를 정렬하는 정렬부와;An alignment portion for aligning the wafer; 상기 웨이퍼에 빛을 입사시키는 조명부와;An illumination unit for injecting light into the wafer; 상기 웨이퍼의 특정 지역에 패터닝된 노광량에 따라 가변하는 이미지를 판독하는 검사부;An inspection unit which reads an image variable according to an exposure amount patterned on a specific region of the wafer; 를 포함하는 반도체 소자 제조장치.Semiconductor device manufacturing apparatus comprising a. 제 2항에 있어서, 상기 정렬부는 웨이퍼에 형성된 노치를 감지하여 웨이퍼를 정렬하는 노치 정렬용 엘이디(LED)로 이루어지는 반도체 소자 제조장치.The semiconductor device manufacturing apparatus of claim 2, wherein the alignment unit comprises a notch alignment led (LED) for aligning the wafer by sensing a notch formed in the wafer. 제 2항에 있어서, 상기 판독부는 고체 촬상 소자(CCD)로 이루어지는 반도체 소자 제조장치.The apparatus of claim 2, wherein the reading unit comprises a solid-state imaging device (CCD). 제 2항에 있어서, 상기 이미지는 마름모꼴 형상으로 형성되는 반도체 소자 제조장치.The apparatus of claim 2, wherein the image is formed in a rhombic shape.
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