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KR100546111B1 - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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KR100546111B1
KR100546111B1 KR1019990063579A KR19990063579A KR100546111B1 KR 100546111 B1 KR100546111 B1 KR 100546111B1 KR 1019990063579 A KR1019990063579 A KR 1019990063579A KR 19990063579 A KR19990063579 A KR 19990063579A KR 100546111 B1 KR100546111 B1 KR 100546111B1
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layer
word line
tungsten
etching
manufacturing
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KR20010061095A (en
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이상익
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주식회사 하이닉스반도체
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144Manufacturing their gate insulating layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0147Manufacturing their gate sidewall spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684Smoothing; Planarisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 다머신(Damascene) 워드 라인(Word Line) 형성 공정에서 베리어(Barrier) 금속층/텅스텐(W)층 형성 후 상기 텅스텐층을 층간 산화막을 식각 종말점으로 시엠피(Chemical Mechanical Polishing:CMP) 공정을 하고 다시 에치 백(Etch Back) 공정을 하여 상기 워드 라인의 측벽쪽 텅스텐층과 워드 라인 중심의 텅스텐층을 동일한 높이로 형성하기 위한 반도체 소자의 제조 방법에 관한 것이다.In the present invention, a barrier metal layer / tungsten (W) layer is formed in a damascene word line forming process, and the tungsten layer is formed of a SiMP process using an interlayer oxide layer as an etching end point. And an etch back process to form a tungsten layer on the sidewall of the word line and a tungsten layer at the center of the word line at the same height.

본 발명의 반도체 소자의 제조 방법은 다머신 공정을 이용하여 워드 라인 형성시, 베리어 금속/텅스텐 형성 후 에치 백 방법 대신 CMP 방법으로 산화막까지 텅스텐을 제거한 후 에치 백 방법으로 텅스텐을 식각하여 균일한 텅스텐층을 갖는 워드 라인을 형성하므로, 후속 콘택 형성 에치 백 공정시 측벽의 손상에 따른 텅스텐층의 노출을 방지하여 누설 전류 및 배선간의 쇼트(Short)를 억제하므로 워드 라인의 신뢰성을 향상시키고 소자의 안정성 및 수율을 향상시키는 특징이 있다.In the method of manufacturing a semiconductor device according to the present invention, when forming a word line using a damascene process, after tungsten metal / tungsten formation, tungsten is removed to the oxide layer by the CMP method instead of the etch back method, and the tungsten is etched by the etch back method to uniform tungsten. By forming a word line having a layer, it prevents the exposure of the tungsten layer due to damage of the sidewall during the subsequent contact formation etch back process, thereby suppressing leakage current and short circuit between wirings, thereby improving the reliability of the word line and the stability of the device. And improving yield.

Description

반도체 소자의 제조 방법{Method for manufacturing semiconductor device}Method for manufacturing semiconductor device

도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자 중 워드 라인의 제조 방법을 나타낸 공정 단면도1A to 1C are cross-sectional views illustrating a method of manufacturing a word line of a semiconductor device according to the related art.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자 중 워드 라인의 제조 방법을 나타낸 공정 단면도2A through 2C are cross-sectional views illustrating a method of manufacturing a word line in a semiconductor device according to an embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

31: 반도체 기판 32: 제 1 질화막 측벽31 semiconductor substrate 32 first nitride film sidewalls

33: 층간 산화막 34: 게이트 산화막33: interlayer oxide film 34: gate oxide film

35: 베리어 금속층 36: 텅스텐층35: barrier metal layer 36: tungsten layer

37: 제 2 질화막 38: 콘택홀37: second nitride film 38: contact hole

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 균일한 텅스텐(W)층을 갖는 워드 라인(Word Line)을 형성하여 소자의 특성, 신뢰성 및 수율을 향상시키는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device in which a word line having a uniform tungsten (W) layer is formed to improve characteristics, reliability, and yield of the device.

종래 기술에 따른 반도체 소자 중 워드 라인의 제조 방법은 도 1a에서와 같 이, 다머신(Damascene) 공정에 의한 것으로 반도체 기판(11)상에 열 산화 공정에 의해 패드(Pad) 산화막(도시하지 않음)을 성장시킨다.The method of manufacturing a word line among the semiconductor devices according to the related art is by a damascene process, as shown in FIG. 1A, and may be a pad oxide film (not illustrated) by a thermal oxidation process on the semiconductor substrate 11. Grow).

그리고, 상기 패드 산화막상에 다결정 실리콘층(도시하지 않음)과 제 1 감광막(도시하지 않음)을 형성한 후, 상기 제 1 감광막을 워드 라인이 형성될 부위에만 남도록 선택적으로 노광 및 현상한다.After forming a polycrystalline silicon layer (not shown) and a first photoresist film (not shown) on the pad oxide film, the first photoresist film is selectively exposed and developed so that only the portion where the word line is to be formed remains.

이어, 상기 선택적으로 노광 및 현상된 제 1 감광막을 마스크로 상기 다결정 실리콘층을 선택적으로 식각한 후, 상기 제 1 감광막을 제거한다.Subsequently, the polycrystalline silicon layer is selectively etched using the selectively exposed and developed first photoresist film, and then the first photoresist film is removed.

그 후, 전면에 제 1 질화막을 형성하고 에치 백(Etch Back)하여 상기 선택 식각된 다결정 실리콘층 양측의 패드 산화막상에 제 1 질화막 측벽(12)을 형성한다.Thereafter, the first nitride film is formed on the entire surface and etched back to form the first nitride film sidewall 12 on the pad oxide films on both sides of the selectively etched polycrystalline silicon layer.

여기서, 상기 제 1 질화막 측벽(12)은 후속 공정에서 엘디디(Lightly Doped Drain:LDD) 이온 주입시 마스크 역할을 하고 비트 라인(Bit Line) 콘택 또는 캐패시터의 하부 전극 콘택 형성 공정시 에스에이시(Self-Aligned-Contact:SAC) 베리어(Barrier)층으로서 역할을 한다.Here, the first nitride film sidewall 12 serves as a mask during lightly doped drain (LDD) ion implantation in a subsequent process, and is formed during the process of forming a bit line contact or a lower electrode contact of a capacitor. Self-Aligned-Contact (SAC) serves as a barrier layer.

이어, 상기 제 1 질화막 측벽(12)을 포함한 전면에 층간 산화막(13)을 형성하고 상기 다결정 실리콘층의 식각 종말점으로 에치 백 또는 시엠피(Chemical Mechanical Polishing:CMP) 방법에 의해 식각한다.Subsequently, an interlayer oxide layer 13 is formed on the entire surface including the first nitride layer sidewall 12 and etched by an etch back or chemical mechanical polishing (CMP) method as an etching end point of the polycrystalline silicon layer.

그리고, 상기 다결정 실리콘층을 제거하여 상기 워드 라인이 형성될 부위의 반도체 기판(11)을 노출시킨다.The polycrystalline silicon layer is removed to expose the semiconductor substrate 11 at the site where the word line is to be formed.

그 다음, 상기 노출된 반도체 기판(11)을 포함한 전면에 게이트 산화막(14), 베리어 금속층(15) 및 텅스텐층(16)을 형성한다.Next, the gate oxide film 14, the barrier metal layer 15, and the tungsten layer 16 are formed on the entire surface including the exposed semiconductor substrate 11.

도 1b에서와 같이, 상기 텅스텐층(16)을 상기 층간 산화막(13)의 식각 종말점으로 에치 백 방법에 의해 식각하여 워드 라인을 형성한다.As shown in FIG. 1B, the tungsten layer 16 is etched by an etch back method to an etching end point of the interlayer oxide layer 13 to form a word line.

도 1c에서와 같이, 상기 식각된 텅스텐층(16)을 포함한 층간 산화막(13)상에 제 2 질화막(17)을 형성하고 상기 제 1 질화막 측벽(12) 사이의 워드 라인상에 상기 제 2 질화막(17)이 잔존하도록 CMP 방법에 의해 식각한다.As shown in FIG. 1C, a second nitride film 17 is formed on the interlayer oxide film 13 including the etched tungsten layer 16 and the second nitride film is formed on a word line between the first nitride film sidewalls 12. It etches by the CMP method so that (17) may remain.

그리고, 상기 잔존한 제 2 질화막(17)을 포함한 전면에 제 2 감광막을 도포하고, 상기 제 2 감광막을 비트 라인 및 캐패시터 콘택이 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.Then, a second photoresist film is applied to the entire surface including the remaining second nitride film 17, and the second photoresist film is selectively exposed and developed so as to be removed only at a portion where bit lines and capacitor contacts are to be formed.

이어, 상기 선택적으로 노광 및 현상된 제 2 감광막을 마스크로 상기 층간 산화막(13)을 식각하여 콘택홀(18)을 형성한 후, 상기 제 2 감광막을 제거한다.Subsequently, the interlayer oxide layer 13 is etched using the selectively exposed and developed second photoresist layer to form a contact hole 18, and then the second photoresist layer is removed.

이때, 상기 콘택홀(18) 형성시, 상기 제 2 질화막(17)과 제 1 질화막 측벽(12)이 손상되어 상기 텅스텐층(16)이 노출(A)된다.In this case, when forming the contact hole 18, the second nitride layer 17 and the first nitride layer sidewall 12 are damaged to expose the tungsten layer 16.

즉, 상기 텅스텐층(16) 형성시 상기 워드 라인 중심부에 굴곡이 발생되어 상기 워드 라인 중심부보다 상기 제 1 질화막 측벽(12)쪽 텅스텐층이 높게 형성되기 때문에 상기 제 2 질화막(17)과 제 1 질화막 측벽(12)이 손상으로 상기 텅스텐층(16)이 노출(A)된다.That is, when the tungsten layer 16 is formed, bending occurs in the center of the word line, so that the tungsten layer on the sidewall 12 of the first nitride layer is formed higher than the center of the word line, so that the second nitride layer 17 and the first nitride layer 17 are formed. The tungsten layer 16 is exposed (A) due to damage to the nitride film sidewall 12.

그러나 종래의 반도체 소자의 제조 방법은 다머신 워드 라인 형성 공정에서 베리어 금속층/텅스텐층 형성 후 에치 백 공정을 하여 워드 라인 형성시, 형성시에 발생된 굴곡으로 인해 상기 워드 라인의 측벽쪽 텅스텐층이 워드 라인 중심보다 높게 형성되기 때문에 후속 콘택 형성 에치 백 공정시 상기 워드 라인의 측벽 손상으로 상기 텅스텐층이 노출되어 누설 전류 및 배선간의 쇼트(Short)가 발생하므로 소자의 특성 및 신뢰성을 저하시키는 문제점이 있었다.However, in the conventional method of manufacturing a semiconductor device, the tungsten layer on the sidewall of the word line is formed due to the bending caused during the formation of the word line by performing the etch back process after forming the barrier metal layer / tungsten layer in the damascene word line forming process. Since it is formed higher than the center of the word line, the tungsten layer is exposed by damage to the sidewall of the word line during the subsequent contact formation etch back process, so that a short circuit between the leakage current and the wiring occurs, thereby deteriorating device characteristics and reliability. there was.

본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 다머신 워드 라인 형성 공정에서 베리어 금속층/텅스텐층 형성 후 상기 텅스텐층을 층간 산화막을 식각 종말점으로 CMP 공정을 하고 다시 에치 백 공정을 하여 상기 워드 라인의 측벽쪽 텅스텐층과 워드 라인 중심의 텅스텐층을 동일한 높이로 형성하는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and after forming the barrier metal layer / tungsten layer in the damascene word line forming process, the tungsten layer is subjected to the CMP process with the interlayer oxide layer as an etching end point and then etched back to the word line. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which the tungsten layer at the sidewall side and the tungsten layer at the center of the word line are formed at the same height.

본 발명의 반도체 소자는 워드 라인이 형성될 부위가 정의된 기판을 마련하는 단계, 기판상에 패드 절연막과 더미층을 형성하는 단계, 상기 더미층을 상기 워드 라인이 형성될 부위에만 남도록 선택 식각하는 단계, 상기 선택 식각된 더미층 양측의 패드 절연막상에 제 1 절연막 측벽을 형성하는 단계, 전면에 층간 절연막을 형성하는 단계, 상기 층간 절연막을 상기 더미층의 식각 종말점으로 전면 식각하는 단계, 상기 워드 라인이 형성될 부위의 기판이 노출되도록 상기 더미층과 패드 절연막을 제거하는 단계, 상기 노출된 기판을 포함한 전면에 게이트 절연막, 베리어 금속층 및 금속층을 형성하는 단계 및 상기 금속층을 상기 층간 절연막의 식각 종말점으로 CMP 방법에 의해 식각한 후, 상기 층간 절연막의 상부 부위가 돌출되도록 에치 백하여 상기 균일한 금속층을 갖는 워드 라인을 형성하는 단계를 포함하여 이 루어짐을 특징으로 한다.The semiconductor device of the present invention comprises the steps of: providing a substrate having a portion where a word line is to be defined, forming a pad insulating film and a dummy layer on the substrate, and selectively etching the dummy layer so that only the portion where the word line is to be formed is left. Forming a first insulating film sidewall on the pad insulating films on both sides of the selectively etched dummy layer, forming an interlayer insulating film on the entire surface, and etching the entire interlayer insulating film to the etching end point of the dummy layer; Removing the dummy layer and the pad insulating layer so that the substrate of the portion where the line is to be formed is exposed, forming a gate insulating layer, a barrier metal layer and a metal layer on the entire surface including the exposed substrate, and etching the metal layer to an etching end point of the interlayer insulating layer. After etching by the CMP method, the bacteria were etched back to protrude the upper portion of the interlayer insulating film. And forming a word line having a single metal layer.

상기와 같은 본 발명에 따른 반도체 소자의 제조 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings a preferred embodiment of the method for manufacturing a semiconductor device according to the present invention as follows.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자 중 워드 라인의 제조 방법을 나타낸 공정 단면도이다.2A through 2C are cross-sectional views illustrating a method of manufacturing a word line in a semiconductor device according to an embodiment of the present invention.

본 발명의 실시 예에 따른 반도체 소자 중 금속 워드 라인의 제조 방법은 도 2a에서와 같이, 다머신 공정에 의한 것으로 반도체 기판(31)상에 패드 산화막(도시하지 않음), 다결정 실리콘층(도시하지 않음) 및 제 1 감광막(도시하지 않음)을 형성한다.A method of manufacturing a metal word line among semiconductor devices according to an exemplary embodiment of the present invention is based on a multi-machine process, as shown in FIG. And a first photosensitive film (not shown).

여기서, 상기 패드 산화막을 LP(Low Pressure) 또는 PE(Plasma Enhanced) 방법으로 400 ∼ 1300℃의 온도하에 40 ∼ 100Å의 두께로 형성한다.Here, the pad oxide film is formed to a thickness of 40 to 100 Pa by a low pressure (LP) or plasma enhanced (PE) method at a temperature of 400 to 1300 ° C.

상기 다결정 실리콘층을 400 ∼ 1200℃의 온도하에 500 ∼ 3000Å의 두께로 형성하고 또한 도핑된 다결정 실리콘층 또는 비정질 실리콘층으로 대신하여 형성할 수 있다.The polycrystalline silicon layer may be formed at a thickness of 500 to 3000 kPa under a temperature of 400 to 1200 ° C, and may be formed instead of the doped polycrystalline silicon layer or the amorphous silicon layer.

그리고, 상기 제 1 감광막을 워드 라인이 형성될 부위에만 남도록 선택적으로 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 제 1 감광막을 마스크로 상기 다결정 실리콘층을 선택적으로 식각한 후, 상기 제 1 감광막을 제거한다.And selectively exposing and developing the first photoresist film so as to remain only in a portion where a word line is to be formed, and then selectively etching the polycrystalline silicon layer using the selectively exposed and developed first photoresist film as a mask, and then Remove the photoresist.

그 후, 전면에 제 1 질화막을 LP 또는 PE 방법으로 400 ∼ 1300℃의 온도하에 100 ∼ 1000Å의 두께로 형성하고 에치 백하여 상기 선택 식각된 다결정 실리콘층 양측의 패드 산화막상에 제 1 질화막 측벽(32)을 형성한다.Subsequently, the first nitride film is formed on the entire surface by LP or PE at a temperature of 400 to 1300 ° C., etched back, and etched back to form a first nitride film sidewall on the pad oxide films on both sides of the selectively etched polycrystalline silicon layer. 32).

여기서, 상기 제 1 질화막 측벽(32)은 후속 공정에서 LDD 이온 주입시 마스크 역할을 하고 비트 라인 콘택 또는 캐패시터의 하부 전극 콘택 형성 공정시 SAC 베리어층으로서 역할을 한다.In this case, the first nitride layer sidewall 32 serves as a mask during LDD ion implantation in a subsequent process and serves as a SAC barrier layer during a bit line contact or a lower electrode contact forming process of a capacitor.

이어, 상기 제 1 질화막 측벽(32)을 포함한 전면에 3000 ∼ 10000Å 두께의 층간 산화막(33)을 형성하고 선택적으로 300 ∼ 1000℃의 온도로 열처리한 후, 상기 다결정 실리콘층의 식각 종말점으로 에치 백 또는 CMP 방법에 의해 식각한다.Subsequently, an interlayer oxide film 33 having a thickness of 3000 to 10000 Pa is formed on the entire surface including the first nitride film sidewall 32, and optionally heat treated at a temperature of 300 to 1000 ° C., and then etch back to the etching end point of the polycrystalline silicon layer. Or by the CMP method.

여기서, 상기 층간 산화막(33)을 BPSG, PSG, FSG, PE-TEOS, PE-SiH4, HEP USG, H에 PSG 및 APL 중 하나로 형성할 수 있다.The interlayer oxide layer 33 may be formed of one of PSG and APL in BPSG, PSG, FSG, PE-TEOS, PE-SiH4, HEP USG, and H.

그리고, 상기 다결정 실리콘층을 제거하여 상기 워드 라인이 형성될 부위의 반도체 기판(31)을 노출시킨다.The polycrystalline silicon layer is removed to expose the semiconductor substrate 31 at the site where the word line is to be formed.

그 다음, 상기 노출된 반도체 기판(31)을 포함한 전면에 40 ∼ 100Å 두께의 게이트 산화막(34) 그리고 베리어 금속층(35) 및 텅스텐층(36)을 형성한다.Subsequently, a gate oxide layer 34, a barrier metal layer 35, and a tungsten layer 36 having a thickness of 40 to 100 μm are formed on the entire surface including the exposed semiconductor substrate 31.

여기서, 상기 게이트 산화막(34) 대신에 HTO, Al2O3 및 Ta2O5 중 하나로 형성할 수 있다.In this case, the gate oxide layer 34 may be formed of one of HTO, Al 2 O 3, and Ta 2 O 5.

상기 베리어 금속층(35)을 스퍼터링(Sputtering) 방법, PVD 또는 CVD 방법에 의해 50 ∼ 800Å 두께로 형성한 다음, 선택적으로 N2 분위기에서 400 ∼ 800℃의 온도로 열처리하며, Ti, TiN, TiAlN, TiSiN, TaN 및 WN TiSi2 중 하나로 대신하여 형성할 수 있다.The barrier metal layer 35 is formed to a thickness of 50 to 800 kPa by a sputtering method, a PVD or a CVD method, and then optionally heat-treated at a temperature of 400 to 800 ° C. in an N 2 atmosphere, and the Ti, TiN, TiAlN, TiSiN , TaN and WN can be formed instead of one of TiSi2.

상기 텅스텐층(36)을 스퍼터링, PVD 및 CVD 방법으로 300 ∼ 1000℃의 온도하에 2000 ∼ 5000Å 두께로 형성하고, 구리(Cu)로 대신하여 형성할 수 있다.The tungsten layer 36 may be formed to a thickness of 2000 to 5000 kPa under a temperature of 300 to 1000 ° C. by sputtering, PVD, and CVD, and may be formed instead of copper (Cu).

그리고, 상기 텅스텐층(36)을 상기 층간 산화막(33)의 식각 종말점으로 실리카(Silica) 또는 알루미나(Alumina) 계통의 업레이시브(Abrasive)를 각각 또는 동시에 포함하며 0.5 ∼ 10wt% 농도의 과산화수소가 첨가된 슬러리를 이용 후 곧바로 0.0001 ∼ 1wt% 농도의 HNO3, HF, HCl, H2SO4가 단독 또는 적절한 조합으로 포함된 슬러리를 이용하여 CMP 방법에 의해 식각한 후, 상기 층간 산화막(33)의 상부 부위가 돌출되도록 에치 백하여 상기 균일한 텅스텐층(36)을 갖는 워드 라인을 형성한다.In addition, the tungsten layer 36 includes silica or alumina-based abrasives each or simultaneously as an etching end point of the interlayer oxide layer 33, and hydrogen peroxide having a concentration of 0.5 to 10 wt% Immediately after using the added slurry, the upper portion of the interlayer oxide layer 33 was etched by CMP using a slurry containing 0.0001 to 1wt% of HNO 3, HF, HCl, and H 2 SO 4 alone or in an appropriate combination. It is etched back to protrude to form a word line having the uniform tungsten layer 36.

도 2b에서와 같이, 상기 워드 라인을 포함한 전면에 LP 방법 또는 PE 방법으로 400 ∼ 1300℃의 온도하에 200 ∼ 800Å 두께의 제 2 질화막(37)을 형성한 후, 상기 제 1 질화막 측벽(32) 사이의 워드 라인상에 상기 제 2 질화막(37)이 잔존하도록 상기 층간 산화막(33)을 식각 종말점으로 50 ∼ 500nm 크기의 일반적인 실리카 계열 산화막 슬러리를 pH 2 ∼ 12로 유지하면서 에치 백 또는 CMP 방법에 의해 식각한다.As shown in FIG. 2B, after the second nitride film 37 having a thickness of 200 to 800 占 퐉 is formed on the entire surface including the word line by the LP method or the PE method, the first nitride film sidewall 32 is formed. The interlayer oxide film 33 is etched to the end of the etch back or CMP method while maintaining a general silica-based oxide film slurry having a pH of 2 to 12 with a size of 50 to 500 nm as the end point of etching so that the second nitride film 37 remains on the word line therebetween. By etching.

도 2c에서와 같이, 상기 잔존한 제 2 질화막(37)을 포함한 전면에 제 2 감광막을 도포하고, 상기 제 2 감광막을 비트 라인 및 캐패시터 콘택이 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 2C, a second photoresist film is applied to the entire surface including the remaining second nitride film 37, and the second photoresist film is selectively exposed and developed so as to be removed only at a portion where a bit line and a capacitor contact are to be formed.

그리고, 상기 선택적으로 노광 및 현상된 제 2 감광막을 마스크로 상기 층간 산화막(33)을 식각하여 콘택홀(38)을 형성한 후, 상기 제 2 감광막을 제거한다.The interlayer oxide layer 33 is etched using the selectively exposed and developed second photoresist layer to form a contact hole 38, and then the second photoresist layer is removed.

이때, 상기 콘택홀(38) 형성시, 상기 제 2 질화막(37)과 제 1 질화막 측벽(32)이 손상되지만 상기 워드 라인이 균일한 텅스텐층(36)을 가지므로 상기 텅 스텐층(36)이 노출되지 않는다.In this case, when the contact hole 38 is formed, the tungsten layer 36 is damaged because the second nitride layer 37 and the first nitride layer sidewall 32 are damaged, but the word line has a uniform tungsten layer 36. This is not exposed.

본 발명의 반도체 소자의 제조 방법은 다머신 공정을 이용하여 워드 라인 형성시, 베리어 금속/텅스텐 형성 후 에치 백 방법 대신 CMP 방법으로 산화막까지 텅스텐을 제거한 후 에치 백 방법으로 텅스텐을 식각하여 균일한 텅스텐층을 갖는 워드 라인을 형성하므로, 후속 콘택 형성 에치 백 공정시 측벽의 손상에 따른 텅스텐층의 노출을 방지하여 누설 전류 및 배선간의 쇼트를 억제하므로 워드 라인의 신뢰성을 향상시키고 소자의 안정성 및 수율을 향상시키는 효과가 있다.In the method of manufacturing a semiconductor device according to the present invention, when forming a word line using a damascene process, after tungsten metal / tungsten formation, tungsten is removed to the oxide layer by the CMP method instead of the etch back method, and the tungsten is etched by the etch back method to uniform tungsten. By forming a word line having a layer, it prevents exposure of the tungsten layer due to damage of the side wall during the subsequent contact forming etch back process, thereby suppressing leakage current and short circuit between wirings, thereby improving word line reliability and improving device stability and yield. It is effective to improve.

Claims (8)

워드 라인이 형성될 부위가 정의된 기판을 마련하는 단계;Providing a substrate defining a portion where a word line is to be formed; 기판상에 패드 절연막과 더미층을 형성하는 단계;Forming a pad insulating film and a dummy layer on the substrate; 상기 더미층을 상기 워드 라인이 형성될 부위에만 남도록 선택 식각하는 단계;Selectively etching the dummy layer so that only the portion where the word line is to be formed remains; 상기 선택 식각된 더미층 양측의 패드 절연막상에 제 1 절연막 측벽을 형성하는 단계;Forming sidewalls of a first insulating layer on pad insulating layers on both sides of the selectively etched dummy layer; 전면에 층간 절연막을 형성하는 단계;Forming an interlayer insulating film on the entire surface; 상기 층간 절연막을 상기 더미층의 식각 종말점으로 전면 식각하는 단계;Etching the interlayer insulating layer to an etch end point of the dummy layer; 상기 워드 라인이 형성될 부위의 기판이 노출되도록 상기 더미층과 패드 절연막을 제거하는 단계;Removing the dummy layer and the pad insulating layer so that the substrate of the portion where the word line is to be formed is exposed; 상기 노출된 기판을 포함한 전면에 게이트 절연막, 베리어 금속층 및 금속층을 형성하는 단계;Forming a gate insulating film, a barrier metal layer, and a metal layer on the entire surface including the exposed substrate; 상기 금속층을 상기 층간 절연막의 식각 종말점으로 화학 기계적 연마 방법에 의해 식각한 후, 상기 층간 절연막의 상부 부위가 돌출되도록 전면 식각하여 상기 균일한 금속층을 갖는 워드 라인을 형성하는 단계를 포함하여 이루어짐을 특징으로 하는 반도체 소자의 제조 방법.And etching the metal layer by the chemical mechanical polishing method to the etching end point of the interlayer insulating layer, and then etching the entire surface to protrude the upper portion of the interlayer insulating layer to form a word line having the uniform metal layer. The manufacturing method of the semiconductor element made into. 제 1 항에 있어서,The method of claim 1, 상기 패드 절연막을 LP 또는 PE 방법으로 400 ∼ 1300℃의 온도하에 40 ∼ 100Å의 두께로 형성함을 특징으로 하는 반도체 소자의 제조 방법.A method for manufacturing a semiconductor device, wherein the pad insulating film is formed to a thickness of 40 to 100 kPa by a LP or PE method at a temperature of 400 to 1300 ° C. 제 1 항에 있어서,The method of claim 1, 상기 더미층을 500 ∼ 3000Å 두께의 다결정 실리콘층, 도핑된 다결정 실리콘층 및 비정질 실리콘층 중 하나로 400 ∼ 1200℃의 온도하에 형성함을 특징으로 하는 반도체 소자의 제조 방법.The dummy layer is formed of a polycrystalline silicon layer, a doped polycrystalline silicon layer, and an amorphous silicon layer having a thickness of 500 to 3000 GPa under a temperature of 400 to 1200 ° C. 제 1 항에 있어서,The method of claim 1, 상기 층간 절연막을 3000 ∼ 10000Å 두께의 BPSG, PSG, FSG, PE-TEOS, PE-SiH4, HEP USG, H에 PSG 및 APL 중 하나로 형성하고 선택적으로 300 ∼ 1000℃의 온도로 열처리함을 특징으로 하는 반도체 소자의 제조 방법.The interlayer insulating film is formed of one of PSG and APL in BPSG, PSG, FSG, PE-TEOS, PE-SiH4, HEP USG, H having a thickness of 3000 to 10000Å and selectively heat-treated at a temperature of 300 to 1000 ° C. Method of manufacturing a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 게이트 절연막을 40 ∼ 100Å 두께의 산화막, HTO, Al2O3 및 Ta2O5 중 하나로 형성함을 특징으로 하는 반도체 소자의 제조 방법.And the gate insulating film is formed of one of an oxide film having a thickness of 40 to 100 kV, HTO, Al2O3, and Ta2O5. 제 1 항에 있어서,The method of claim 1, 상기 베리어 금속층을 스퍼터링 방법, PVD 또는 CVD 방법에 의해 50 ∼ 800Å 두께로 형성한 다음, 선택적으로 N2 분위기에서 400 ∼ 800℃의 온도로 열처리 하며, Ti, TiN, TiAlN, TiSiN, TaN 및 WN TiSi2 중 하나로 형성함을 특징으로 하는 반도체 소자의 제조 방법.The barrier metal layer is formed to a thickness of 50 to 800 kPa by a sputtering method, a PVD or a CVD method, and then optionally heat treated at a temperature of 400 to 800 ° C. in an N 2 atmosphere, and among Ti, TiN, TiAlN, TiSiN, TaN, and WN TiSi 2. Method for manufacturing a semiconductor device, characterized in that formed in one. 제 1 항에 있어서,The method of claim 1, 상기 금속층을 스퍼터링, PVD 및 CVD 방법으로 300 ∼ 1000℃의 온도하에 2000 ∼ 5000Å 두께의 텅스텐 또는 구리로 형성함을 특징으로 하는 반도체 소자의 제조 방법.The metal layer is formed of tungsten or copper having a thickness of 2000 to 5000 kPa under a temperature of 300 to 1000 ° C. by sputtering, PVD and CVD methods. 제 7 항에 있어서,The method of claim 7, wherein 상기 텅스텐층을 상기 층간 절연막의 식각 종말점으로 실리카 또는 알루미나 계통의 업레이시브를 각각 또는 동시에 포함하며 0.5 ∼ 10wt% 농도의 과산화수소가 첨가된 슬러리를 이용 후 곧바로 0.0001 ∼ 1wt% 농도의 HNO3, HF, HCl, H2SO4가 단독 또는 적절한 조합으로 포함된 슬러리를 이용하여 CMP 방법에 의해 식각함을 특징으로 하는 반도체 소자의 제조 방법.The tungsten layer includes silica or alumina-type up-slave, respectively or simultaneously, as an etching end point of the interlayer insulating layer, and immediately after using a slurry containing 0.5-10 wt% hydrogen peroxide, HNO 3, HF, Method for manufacturing a semiconductor device, characterized in that the etching by the CMP method using a slurry containing HCl, H2SO4 alone or in a suitable combination.
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