[go: up one dir, main page]

KR100546843B1 - Transistor manufacturing method of semiconductor device - Google Patents

Transistor manufacturing method of semiconductor device Download PDF

Info

Publication number
KR100546843B1
KR100546843B1 KR1020030102075A KR20030102075A KR100546843B1 KR 100546843 B1 KR100546843 B1 KR 100546843B1 KR 1020030102075 A KR1020030102075 A KR 1020030102075A KR 20030102075 A KR20030102075 A KR 20030102075A KR 100546843 B1 KR100546843 B1 KR 100546843B1
Authority
KR
South Korea
Prior art keywords
source
device isolation
forming
germanium
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020030102075A
Other languages
Korean (ko)
Other versions
KR20050069717A (en
Inventor
이정호
Original Assignee
동부아남반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 동부아남반도체 주식회사 filed Critical 동부아남반도체 주식회사
Priority to KR1020030102075A priority Critical patent/KR100546843B1/en
Publication of KR20050069717A publication Critical patent/KR20050069717A/en
Application granted granted Critical
Publication of KR100546843B1 publication Critical patent/KR100546843B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 소자의 트랜지스터 제조방법에 관한 것으로, 보다 자세하게는 소자분리막과 소오스/드레인 영역의 계면에 게르마늄을 이온주입함으로써 소오스/드레인의 보론이 소자분리막으로 확산하는 것을 방지하여 누설전류의 발생을 억제할 수 있는 방법에 관한 것이다.The present invention relates to a method for manufacturing a transistor of a semiconductor device, and more particularly, by injecting germanium into an interface between a device isolation film and a source / drain region, the boron of the source / drain is prevented from diffusing into the device isolation film to prevent leakage current. It is about the method which can be suppressed.

본 발명의 반도체 소자의 트랜지스터 제조방법은 실리콘 기판에 소자분리막과 게이트 산화막 그리고 스페이서를 구비한 게이트 전극을 형성하는 단계; 상기 소자분리막 측면의 계면영역에 게르마늄을 이온주입하는 단계; 상기 패턴을 제거하고 소오스/드레인 영역을 형성하고 열처리하는 단계; 및 상기 소오스/드레인 영역의 상부 표면에 실리사이드를 형성하는 단계로 이루어짐에 기술적 특징이 있다.A transistor manufacturing method of a semiconductor device of the present invention comprises the steps of forming a gate electrode having a device isolation film, a gate oxide film and a spacer on a silicon substrate; Implanting germanium into an interface region of the side surface of the device isolation layer; Removing the pattern, forming a source / drain region, and heat-treating; And forming a silicide on the upper surface of the source / drain region.

따라서, 본 발명의 반도체 소자의 트랜지스터 제조방법은 소자분리막과 소오스/드레인 영역의 계면에 게르마늄을 이온주입함으로써 소오스/드레인의 보론이 소자분리막으로 확산하는 것을 방지하여 누설전류의 발생을 억제할 수 있는 효과가 있다.Therefore, the transistor manufacturing method of the semiconductor device of the present invention can prevent the diffusion of the boron of the source / drain to the device isolation film by ion implantation of germanium at the interface between the device isolation film and the source / drain region to suppress the occurrence of leakage current It works.

게르마늄, 보론 확산, PMOSGermanium, Boron Diffusion, PMOS

Description

반도체 소자의 트랜지스터 제조방법 {Method for fabricating transistor of semiconductor device} Method for fabricating transistor of semiconductor device             

도 1a 내지 도 1c는 종래기술에 의한 PMOS 트랜지스터 제조방법의 단면도.1A to 1C are cross-sectional views of a PMOS transistor manufacturing method according to the prior art.

도 2a 내지 도 2c는 본 발명에 의한 PMOS 트랜지스터 제조방법의 단면도.2A to 2C are cross-sectional views of a PMOS transistor manufacturing method according to the present invention.

본 발명은 반도체 소자의 트랜지스터 제조방법에 관한 것으로, 보다 자세하게는 소자분리막과 소오스/드레인 영역의 계면에 게르마늄(Germanium; Ge)을 이온주입함으로써 소오스/드레인의 보론(Boron; B)이 소자분리막으로 확산하는 것을 방지하여 누설전류(leakage current)의 발생을 억제할 수 있는 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device, and more particularly, boron (B) of a source / drain to a device isolation layer by ion implantation of germanium (Ge) at an interface between the device isolation layer and a source / drain region. The present invention relates to a method of preventing diffusion and preventing occurrence of leakage current.

일반적으로 CMOS(complementary metal-oxide-semiconductor) 트랜지스터의 소오스/드레인의 접합은 LOCOS(local oxidation of silicon) 또는 STI(shallow trench isolatin)의 소자분리막과의 경계면에서 접합깊이(junction depth)가 작다. 특히 NMOS(n-type MOS)보다 보론을 이온주입하여 소오스/드레인 영역을 형성하는 PMOS(p-type MOS)의 소자분리막 경계면에서 접합깊이가 작아진다. 이와 같이 접합깊이가 작을 경우엔 소오스/드레인의 표면에 형성된 실리사이드(silicide)와 소오스/드레인의 접합간의 거리가 가까워져서 누설전류가 흐르게 된다. 상기 누설전류는 소자의 특성을 악화시키는 주요 원인중 하나로서 작용한다.In general, the source / drain junction of a complementary metal-oxide-semiconductor (CMOS) transistor has a small junction depth at the interface with a device isolation layer of a local oxidation of silicon (LOCOS) or shallow trench isolatin (STI). In particular, the junction depth of P-type MOS (p-type MOS), which forms source / drain regions by ion implantation of boron rather than n-type MOS, is smaller. In this case, when the junction depth is small, the distance between the silicide formed on the surface of the source / drain and the junction of the source / drain becomes close, so that a leakage current flows. The leakage current acts as one of the main causes of deterioration of device characteristics.

종래기술에서 소오스/드레인 접합깊이가 작아지는 것은 일반적인 현상이다. 상술한 바와 같이 특히 PMOS에서는 소오스/드레인 형성물질로 보론이 사용되는데, 상기 보론은 물질 자체의 특성상 열처리에 민감하게 반응하여 확산이 매우 크다. 특히 주위에 산화막이 존재하는 경우에는 산화막으로의 확산이 다른 물질에 비해 매우 커서 편석(segregation)이 발생하게 된다.It is a common phenomenon that the source / drain junction depth becomes small in the prior art. As described above, in particular, in PMOS, boron is used as a source / drain forming material. The boron is sensitive to heat treatment due to the nature of the material itself, and thus has a large diffusion. In particular, when an oxide film is present in the surroundings, diffusion into the oxide film is much larger than that of other materials, and segregation occurs.

도 1a 내지 도 1c는 종래의 PMOS 제조공정을 보여주는 단면도이다. 1A to 1C are cross-sectional views illustrating a conventional PMOS manufacturing process.

먼저, 도 1a는 소자분리막(1)과 스페이서(2)를 구비한 게이트 전극(3)이 형성된 실리콘 기판(4)에 소오스/드레인 영역(5)을 형성하는 단계를 보여주는 단면도이다. 우선 실리콘 기판에 STI 소자분리막을 형성하고 게이트 산화막을 형성한 후에 폴리실리콘을 증착한다. 이후 반응성 이온식각(reactive ion etching; RIE) 공정으로 폴리실리콘을 부분식각하여 게이트 전극을 형성한다. 이후 TEOS(Tetraethylorthosilicate)와 질화막의 복합막을 적층하고 비등방성 식각을 통해 게이트 측벽에 스페이서(spacer)를 형성한다.First, FIG. 1A is a cross-sectional view illustrating a step of forming a source / drain region 5 in a silicon substrate 4 on which a gate electrode 3 having a device isolation film 1 and a spacer 2 is formed. First, an STI device isolation film is formed on a silicon substrate, and a gate oxide film is formed, followed by deposition of polysilicon. Thereafter, polysilicon is partially etched by a reactive ion etching (RIE) process to form a gate electrode. Thereafter, a composite film of TEOS (Tetraethylorthosilicate) and a nitride film is laminated and spacers are formed on the sidewalls of the gate through anisotropic etching.

이후 게이트 전극과 소자분리막 사이에 소오스/드레인을 형성하기 위해 포토레지스트 패턴과 스페이서를 구비한 게이트 전극을 마스크로 하여 이온주입 공정을 실시한다. 이때 PMOS 트랜지스터를 구현하기 위해 보론 이온을 주입한다. Thereafter, an ion implantation process is performed using a gate electrode having a photoresist pattern and a spacer as a mask to form a source / drain between the gate electrode and the device isolation layer. In this case, boron ions are implanted to implement the PMOS transistor.

다음, 도 1b는 이온 주입후 열처리 단계를 보여주는 단면도이다. 보론 이온을 주입한 후에는 상기 이온을 활성화시키기 위한 열처리를 실시한다. 이때 주입된 보론이온이 산화막으로 구성된 소자분리막 영역으로 우선 확산하게 된다. Next, Figure 1b is a cross-sectional view showing a heat treatment step after the ion implantation. After injecting boron ions, a heat treatment is performed to activate the ions. In this case, the implanted boron ions first diffuse into the device isolation layer region formed of the oxide film.

다음, 도 1c는 실리사이드(6)를 형성하는 단계를 보여주는 단면도이다. 상기 활성화 열처리가 끝나면 소오스/드레인 영역의 상부 표면에 실리사이드를 형성한다. 상기 실리사이드는 소정의 금속을 증착한 후 열처리를 통해 실리콘과 반응하여 형성된다. 이와 같이 주입된 이온의 활성화를 위한 열처리 단계와 실리사이드를 형성하기 위한 열처리 단계를 거치면서 주입된 보론이온이 소자분리막 영역으로 확산하게 되어 소자분리막 계면영역의 보론이 고갈되어 접합깊이가 작아지는 결과를 낳게 된다(점선 영역 참고). 접합깊이가 작아질수록 실리사이드와 소오스/드레인 접합영역 사이의 거리가 가까워지게 되고 누설전류가 증가하는 문제점이 발생한다.Next, FIG. 1C is a cross-sectional view showing the step of forming the silicide 6. After the activation heat treatment, silicide is formed on the upper surface of the source / drain region. The silicide is formed by depositing a predetermined metal and then reacting with silicon through heat treatment. As a result of the heat treatment step for activating the implanted ions and the heat treatment step for forming the silicide, the implanted boron ions diffuse into the device isolation region, resulting in depletion of the boron at the interface region of the device isolation layer to reduce the junction depth. (See dotted line). As the junction depth decreases, the distance between the silicide and the source / drain junction region gets closer and the leakage current increases.

따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 소자분리막과 소오스/드레인 영역의 계면에 게르마늄을 이온주입함으로써 소오스/드레인의 보론이 소자분리막으로 확산하는 것을 방지하여 누설전류의 발생을 억제할 수 있는 방법을 제공함에 본 발명의 목적이 있다.
Accordingly, the present invention is to solve the problems of the prior art as described above, by preventing the diffusion of boron of the source / drain to the device isolation film by ion implantation of germanium at the interface between the device isolation film and the source / drain region. It is an object of the present invention to provide a method which can suppress the occurrence.

본 발명의 상기 목적은 실리콘 기판에 소자분리막과 게이트 산화막 그리고 스페이서를 구비한 게이트 전극을 형성하는 단계; 상기 소자분리막 측면의 계면영역에 게르마늄을 이온주입하는 단계; 상기 패턴을 제거하고 소오스/드레인 영역을 형성하고 열처리하는 단계; 및 상기 소오스/드레인 영역의 상부 표면에 실리사이드를 형성하는 단계로 이루어진 반도체 소자의 트랜지스터 제조방법에 의해 달성된다.The object of the present invention is to form a gate electrode having a device isolation film, a gate oxide film and a spacer on a silicon substrate; Implanting germanium into an interface region of the side surface of the device isolation layer; Removing the pattern, forming a source / drain region, and heat-treating; And forming a silicide on an upper surface of the source / drain region.

게르마늄은 보론의 확산을 억제하는 특성을 갖고 있어 본 발명에서는 이와 같은 게르마늄의 특성을 이용하여 접합영역의 누설전류를 줄이고자 한다.Germanium has a property of suppressing the diffusion of boron, and in the present invention, it is intended to reduce the leakage current in the junction region by using such a property of germanium.

본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

먼저, 도 2a는 소자분리막 측면의 계면영역을 개방하는 포토레지스트 패턴(15)을 형성하는 단계를 보여주는 단면도이다. 우선 실리콘 기판(10)에 STI 소자분리막(11)을 형성하고 게이트 산화막(12)을 형성한 후에 폴리실리콘(15)을 증착한다. 이후 반응성 이온식각(reactive ion etching; RIE) 공정으로 폴리실리콘을 부분식각하여 게이트 전극을 형성한다. 이후 TEOS(Tetraethylorthosilicate)와 질화막의 복합막을 적층하고 비등방성 식각을 통해 게이트 측벽에 스페이서(spacer, 13)를 형성한다. 이후 소자분리막 측면의 계면영역을 개방하는 포토레지스트 패턴(15)을 형성하고, 상기 패턴을 마스크로 하여 게르마늄 이온을 주입한다. 이때 이온주입은 50 내지 70keV의 에너지와 4 내지 5×1014의 도즈(dose) 조건으로 실시 한다. 이온주입된 게르마늄은 소자분리막과 소오스/드레인의 계면 영역(16)에 걸쳐서 존재한다. First, FIG. 2A is a cross-sectional view illustrating a step of forming a photoresist pattern 15 that opens an interface region of a side surface of an isolation layer. First, the STI device isolation film 11 is formed on the silicon substrate 10 and the gate oxide film 12 is formed, and then polysilicon 15 is deposited. Thereafter, polysilicon is partially etched by a reactive ion etching (RIE) process to form a gate electrode. Thereafter, a composite film of TEOS (Tetraethylorthosilicate) and a nitride film is laminated and spacers 13 are formed on the sidewalls of the gate through anisotropic etching. Thereafter, a photoresist pattern 15 is formed to open the interface region of the side surface of the isolation layer, and germanium ions are implanted using the pattern as a mask. In this case, ion implantation is performed under an energy of 50 to 70 keV and a dose condition of 4 to 5 × 10 14 . Ion implanted germanium is present over the interface region 16 of the device isolation film and the source / drain.

다음 도 2b는 게이트 전극과 소자분리막 사이에 소오스/드레인을 형성하기 위해 포토레지스트 패턴(17)과 스페이서를 구비한 게이트 전극을 마스크로 하여 이온주입 공정을 실시한다. 이때 PMOS 트랜지스터를 구현하기 위해 보론 이온을 주입한다. 이후 이온주입된 보론을 활성화시키기 위한 열처리 공정을 실시하는데, 상기 게르마늄의 영향으로 후속 이온주입된 보론은 소자분리막 영역으로의 확산이 억제된다.Next, in FIG. 2B, an ion implantation process is performed using a gate electrode having a photoresist pattern 17 and a spacer as a mask to form a source / drain between the gate electrode and the device isolation layer. In this case, boron ions are implanted to implement the PMOS transistor. Thereafter, a heat treatment process for activating the ion-implanted boron is performed. Subsequently, the ion-implanted boron is suppressed from diffusing into the region of the device isolation layer under the influence of germanium.

다음 도 2c는 상기 게르마늄이 확산장벽의 역할을 함으로써 보론의 확산이 억제되어 소오스/드레인의 접합영역이 소자분리막과의 계면에서 줄어들지 않은 모습을 보여주는 단면도이다. 따라서 접합영역과 실리사이드와의 거리가 멀어져서 누설전류의 발생을 억제하게 된다. Next, FIG. 2C is a cross-sectional view showing that germanium acts as a diffusion barrier and boron diffusion is suppressed so that a junction region of a source / drain is not reduced at an interface with an isolation layer. As a result, the distance between the junction region and the silicide is increased to suppress the occurrence of leakage current.

상세히 설명된 본 발명에 의하여 본 발명의 특징부를 포함하는 변화들 및 변형들이 당해 기술 분야에서 숙련된 보통의 사람들에게 명백히 쉬워질 것임이 자명하다. 본 발명의 그러한 변형들의 범위는 본 발명의 특징부를 포함하는 당해 기술 분야에 숙련된 통상의 지식을 가진 자들의 범위 내에 있으며, 그러한 변형들은 본 발명의 청구항의 범위 내에 있는 것으로 간주된다.It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.

따라서, 본 발명의 반도체 소자의 트랜지스터 제조방법은 소자분리막과 소오 스/드레인 영역의 계면에 게르마늄을 이온주입함으로써 소오스/드레인의 보론이 소자분리막으로 확산하는 것을 방지하여 누설전류의 발생을 억제할 수 있는 효과가 있다.
Therefore, in the transistor manufacturing method of the semiconductor device of the present invention, by injecting germanium into the interface between the device isolation film and the source / drain region, the boron of the source / drain can be prevented from diffusing into the device isolation film to suppress the occurrence of leakage current. It has an effect.

Claims (4)

반도체 소자의 트랜지스터 제조방법에 있어서,In the transistor manufacturing method of a semiconductor element, 실리콘 기판에 소자분리막과 게이트 산화막 그리고 스페이서를 구비한 게이트 전극을 형성하는 단계;Forming a gate electrode having a device isolation layer, a gate oxide layer, and a spacer on a silicon substrate; 상기 소자분리막 측면의 계면영역에 게르마늄을 이온주입하는 단계;Implanting germanium into an interface region of the side surface of the device isolation layer; 소오스/드레인 영역을 형성하고 열처리하는 단계; 및Forming and heat treating a source / drain region; And 상기 소오스/드레인 영역의 상부 표면에 실리사이드를 형성하는 단계Forming silicide on the top surface of the source / drain regions 를 포함하여 이루어짐을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.Transistor manufacturing method of a semiconductor device comprising the. 제 1항에 있어서,The method of claim 1, 상기 게르마늄을 이온주입하는 단계는 소자분리막 측면의 계면영역을 개방하는 포토레지스트 패턴을 형성하여 실시함을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.The ion implantation of the germanium is formed by forming a photoresist pattern to open the interface region of the side of the device isolation layer. 제 1항에 있어서,The method of claim 1, 상기 게르마늄을 이온주입하는 단계는 50 내지 70keV의 에너지와 4 내지 5×1014의 도즈(dose) 조건으로 실시함을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.The ion implantation of germanium is a method for manufacturing a transistor of a semiconductor device, characterized in that the energy is carried out under a condition of 50 to 70 keV and a dose condition of 4 to 5 × 10 14 . 제 1항에 있어서,The method of claim 1, 상기 소오스/드레인을 형성하는 단계는 소자분리막 상부의 포토레지스트 패턴과 게이트 전극 및 스페이서를 마스크로 하여 보론을 이온주입하여 PMOS 트랜지스터를 형성함을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.The forming of the source / drain may include forming a PMOS transistor by implanting boron using a photoresist pattern on the device isolation layer, a gate electrode, and a spacer as a mask.
KR1020030102075A 2003-12-31 2003-12-31 Transistor manufacturing method of semiconductor device Expired - Fee Related KR100546843B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020030102075A KR100546843B1 (en) 2003-12-31 2003-12-31 Transistor manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020030102075A KR100546843B1 (en) 2003-12-31 2003-12-31 Transistor manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
KR20050069717A KR20050069717A (en) 2005-07-05
KR100546843B1 true KR100546843B1 (en) 2006-01-25

Family

ID=37260079

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020030102075A Expired - Fee Related KR100546843B1 (en) 2003-12-31 2003-12-31 Transistor manufacturing method of semiconductor device

Country Status (1)

Country Link
KR (1) KR100546843B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107785422A (en) * 2016-08-29 2018-03-09 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and its manufacture method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107785422A (en) * 2016-08-29 2018-03-09 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and its manufacture method

Also Published As

Publication number Publication date
KR20050069717A (en) 2005-07-05

Similar Documents

Publication Publication Date Title
US6255152B1 (en) Method of fabricating CMOS using Si-B layer to form source/drain extension junction
JP2005167252A (en) Integrated circuit structure
KR100837555B1 (en) Semiconductor device and manufacturing method thereof
US20080054363A1 (en) Dual gate cmos semiconductor device and method for manufacturing the same
CN100356550C (en) CMOS image sensor and manufacturing method thereof
US6051460A (en) Preventing boron penetration through thin gate oxide of P-channel devices by doping polygate with silicon
US6380021B1 (en) Ultra-shallow junction formation by novel process sequence for PMOSFET
KR20020025460A (en) Semiconductor device and fabricating method thereof
KR100305681B1 (en) semiconductor device and method for manufacturing the same
US6265255B1 (en) Ultra-shallow junction formation for deep sub-micron complementary metal-oxide-semiconductor
KR100546843B1 (en) Transistor manufacturing method of semiconductor device
KR100655069B1 (en) Dual gate MOS transistor manufacturing method
US20080160710A1 (en) Method of fabricating mosfet device
US20080286920A1 (en) Method for manufacturing semiconductor device
US20050153498A1 (en) Method of manufacturing p-channel MOS transistor and CMOS transistor
KR100818521B1 (en) Transistor manufacturing method of semiconductor device
KR100910477B1 (en) Semiconductor device manufacturing method
KR100519507B1 (en) Method for Forming Semi-conductor Device
US6093595A (en) Method of forming source and drain regions in complementary MOS transistors
KR100546124B1 (en) Transistor Formation Method of Semiconductor Device
KR100597462B1 (en) Method for fabricating transistor of semiconductor device
KR100613341B1 (en) Semiconductor device and method of manufacturing the same
KR100529447B1 (en) Method for manufacturing mos transistor
KR100679810B1 (en) Semiconductor Device Preventing Boron Penetration and Manufacturing Method Thereof
KR100609235B1 (en) Manufacturing Method of Semiconductor Device

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

N231 Notification of change of applicant
PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

D13-X000 Search requested

St.27 status event code: A-1-2-D10-D13-srh-X000

D14-X000 Search report completed

St.27 status event code: A-1-2-D10-D14-srh-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

FPAY Annual fee payment

Payment date: 20111220

Year of fee payment: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20130120

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20130120

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000